sacc_hpcarm.c revision 1.4.4.1
1 /* $NetBSD: sacc_hpcarm.c,v 1.4.4.1 2006/09/09 02:39:38 rpaulo Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Platform dependent part for SA-11[01]1 companion chip on hpcarm. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: sacc_hpcarm.c,v 1.4.4.1 2006/09/09 02:39:38 rpaulo Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/types.h> 49 #include <sys/conf.h> 50 #include <sys/device.h> 51 #include <sys/kernel.h> 52 #include <sys/malloc.h> 53 #include <sys/uio.h> 54 55 #include <machine/bus.h> 56 #include <machine/platid.h> 57 #include <machine/platid_mask.h> 58 59 #include <arm/sa11x0/sa11x0_reg.h> 60 #include <arm/sa11x0/sa11x0_var.h> 61 #include <arm/sa11x0/sa11x0_gpioreg.h> 62 #include <arm/sa11x0/sa1111_reg.h> 63 #include <arm/sa11x0/sa1111_var.h> 64 65 static void sacc_attach(struct device *, struct device *, void *); 66 static int sacc_intr(void *); 67 68 struct platid_data sacc_platid_table[] = { 69 { &platid_mask_MACH_HP_JORNADA_7XX, (void *)1 }, 70 { NULL, NULL } 71 }; 72 73 CFATTACH_DECL(sacc, sizeof(struct sacc_softc), 74 sacc_probe, sacc_attach, NULL, NULL); 75 76 #ifdef INTR_DEBUG 77 #define DPRINTF(arg) printf arg 78 #else 79 #define DPRINTF(arg) 80 #endif 81 82 static void 83 sacc_attach(struct device *parent, struct device *self, void *aux) 84 { 85 int i, gpiopin; 86 uint32_t skid; 87 struct sacc_softc *sc = (struct sacc_softc *)self; 88 struct sa11x0_softc *psc = (struct sa11x0_softc *)parent; 89 struct sa11x0_attach_args *sa = aux; 90 struct platid_data *p; 91 92 printf("\n"); 93 94 sc->sc_iot = sa->sa_iot; 95 sc->sc_piot = psc->sc_iot; 96 sc->sc_gpioh = psc->sc_gpioh; 97 98 p = platid_search_data(&platid, sacc_platid_table); 99 if (p == NULL) 100 return; 101 102 gpiopin = (int)p->data; 103 sc->sc_gpiomask = 1 << gpiopin; 104 105 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 106 &sc->sc_ioh)) { 107 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 108 return; 109 } 110 111 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID); 112 113 printf("%s: SA-1111 rev %d.%d\n", sc->sc_dev.dv_xname, 114 (skid & 0xf0) >> 4, skid & 0xf); 115 116 for (i = 0; i < SACCIC_LEN; i++) 117 sc->sc_intrhand[i] = NULL; 118 119 /* initialize SA-1111 interrupt controller */ 120 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 121 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 122 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 123 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 124 SACCIC_INTSTATCLR0, 0xffffffff); 125 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 126 SACCIC_INTSTATCLR1, 0xffffffff); 127 128 /* connect to SA-1110's GPIO intr */ 129 sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc); 130 131 /* attach each devices */ 132 config_search_ia(sa1111_search, self, "sacc", NULL); 133 } 134 135 static int 136 sacc_intr(void *arg) 137 { 138 int i; 139 uint32_t mask; 140 struct sacc_intrvec intstat; 141 struct sacc_softc *sc = arg; 142 struct sacc_intrhand *ih; 143 144 intstat.lo = 145 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 146 intstat.hi = 147 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 148 DPRINTF(("sacc_intr: %x %x\n", intstat.lo, intstat.hi)); 149 150 /* clear SA-1110's GPIO intr status */ 151 bus_space_write_4(sc->sc_piot, sc->sc_gpioh, 152 SAGPIO_EDR, sc->sc_gpiomask); 153 154 for (i = 0, mask = 1; i < 32; i++, mask <<= 1) 155 if (intstat.lo & mask) { 156 /* 157 * Clear intr status before calling intr handlers. 158 * This cause stray interrupts, but clearing 159 * after calling intr handlers cause intr lossage. 160 */ 161 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 162 SACCIC_INTSTATCLR0, 1 << i); 163 164 for (ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 165 softintr_schedule(ih->ih_soft); 166 } 167 for (i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1) 168 if (intstat.hi & mask) { 169 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 170 SACCIC_INTSTATCLR1, 1 << i); 171 for (ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 172 softintr_schedule(ih->ih_soft); 173 } 174 return 1; 175 } 176
Indexes created Thu Sep 25 16:09:42 GMT 2025