uda1341.c revision 1.1
1 /* $NetBSD: uda1341.c,v 1.1 2001/07/15 20:19:31 ichiro Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA (ichiro (at) ichiro.org). 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of The NetBSD Foundation nor the names of its 22 * contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 26 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/conf.h> 42 #include <sys/file.h> 43 #include <sys/device.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/malloc.h> 47 48 #include <machine/bus.h> 49 50 #include <hpcarm/dev/ipaq_saipvar.h> 51 #include <hpcarm/dev/ipaq_gpioreg.h> 52 #include <hpcarm/dev/uda1341.h> 53 #include <hpcarm/sa11x0/sa11x0_gpioreg.h> 54 #include <hpcarm/sa11x0/sa11x0_sspreg.h> 55 56 struct uda1341_softc { 57 struct device sc_dev; 58 bus_space_tag_t sc_iot; 59 bus_space_handle_t sc_ioh; 60 struct ipaq_softc *sc_parent; 61 }; 62 63 static int uda1341_match(struct device *, struct cfdata *, void *); 64 static void uda1341_attach(struct device *, struct device *, void *); 65 static int uda1341_print(void *, const char *); 66 static int uda1341_search(struct device *, struct cfdata *, void *); 67 68 static void uda1341_output_high(struct uda1341_softc *); 69 static void uda1341_output_low(struct uda1341_softc *); 70 static void uda1341_L3_init(struct uda1341_softc *); 71 static void uda1341_init(struct uda1341_softc *); 72 static void uda1341_reset(struct uda1341_softc *); 73 static void uda1341_reginit(struct uda1341_softc *); 74 75 static int L3_getbit(struct uda1341_softc *); 76 static void L3_sendbit(struct uda1341_softc *, int); 77 static u_int8_t L3_getbyte(struct uda1341_softc *, int); 78 static void L3_sendbyte(struct uda1341_softc *, u_int8_t, int); 79 static int L3_read(struct uda1341_softc *, u_int8_t, u_int8_t *, int); 80 static int L3_write(struct uda1341_softc *, u_int8_t, u_int8_t *, int); 81 82 struct cfattach uda_ca = { 83 sizeof(struct uda1341_softc), uda1341_match, uda1341_attach 84 }; 85 86 /* 87 * Philips L3 bus support. 88 * GPIO lines are used for clock, data and mode pins. 89 */ 90 #define L3_DATA GPIO_H3600_L3_DATA 91 #define L3_MODE GPIO_H3600_L3_MODE 92 #define L3_CLK GPIO_H3600_L3_CLK 93 94 static struct { 95 u_int8_t data0; /* direct addressing register */ 96 } DIRECT_REG = {0}; 97 98 static struct { 99 u_int8_t data0; /* extended addressing register 1 */ 100 u_int8_t data1; /* extended addressing register 2 */ 101 } EXTEND_REG = {0, 0}; 102 103 /* 104 * register space access macros 105 */ 106 #define GPIO_WRITE(sc, reg, val) \ 107 bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg, val) 108 #define GPIO_READ(sc, reg) \ 109 bus_space_read_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg) 110 #define EGPIO_WRITE(sc) \ 111 bus_space_write_2(sc->sc_iot, sc->sc_parent->sc_egpioh, \ 112 0, sc->sc_parent->ipaq_egpio) 113 #define SSP_WRITE(sc, reg, val) \ 114 bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_ssph, reg, val) 115 116 static int 117 uda1341_match(parent, cf, aux) 118 struct device *parent; 119 struct cfdata *cf; 120 void *aux; 121 { 122 return (1); 123 } 124 125 static void 126 uda1341_attach(parent, self, aux) 127 struct device *parent; 128 struct device *self; 129 void *aux; 130 { 131 struct uda1341_softc *sc = (struct uda1341_softc *)self; 132 struct ipaq_softc *psc = (struct ipaq_softc *)parent; 133 134 printf("\n"); 135 printf("%s: UDA1341 CODEC\n", sc->sc_dev.dv_xname); 136 137 sc->sc_iot = psc->sc_iot; 138 sc->sc_ioh = psc->sc_ioh; 139 sc->sc_parent = (struct ipaq_softc *)parent; 140 141 uda1341_L3_init(sc); 142 uda1341_init(sc); 143 144 uda1341_reset(sc); 145 146 uda1341_reginit(sc); 147 148 149 /* 150 * Attach each devices 151 */ 152 153 config_search(uda1341_search, self, NULL); 154 } 155 156 static int 157 uda1341_search(parent, cf, aux) 158 struct device *parent; 159 struct cfdata *cf; 160 void *aux; 161 { 162 if ((*cf->cf_attach->ca_match)(parent, cf, NULL) > 0) 163 config_attach(parent, cf, NULL, uda1341_print); 164 return 0; 165 } 166 167 168 static int 169 uda1341_print(aux, name) 170 void *aux; 171 const char *name; 172 { 173 return (UNCONF); 174 } 175 176 static void 177 uda1341_output_high(sc) 178 struct uda1341_softc *sc; 179 { 180 int cr; 181 182 GPIO_WRITE(sc, SAGPIO_PSR, (L3_DATA | L3_MODE | L3_CLK)); 183 cr = GPIO_READ(sc, SAGPIO_PDR) | (L3_DATA | L3_MODE | L3_CLK); 184 GPIO_WRITE(sc, SAGPIO_PDR, cr); 185 } 186 187 static void 188 uda1341_output_low(sc) 189 struct uda1341_softc *sc; 190 { 191 int cr; 192 193 cr = GPIO_READ(sc, SAGPIO_PDR); 194 cr &= ~(L3_DATA | L3_MODE | L3_CLK); 195 GPIO_WRITE(sc, SAGPIO_PDR, cr); 196 } 197 198 static void 199 uda1341_L3_init(sc) 200 struct uda1341_softc *sc; 201 { 202 int cr; 203 204 cr = GPIO_READ(sc, SAGPIO_AFR); 205 cr &= ~(L3_DATA | L3_MODE | L3_CLK); 206 GPIO_WRITE(sc, SAGPIO_AFR, cr); 207 208 uda1341_output_low(sc); 209 } 210 211 static void 212 uda1341_init(sc) 213 struct uda1341_softc *sc; 214 { 215 int cr; 216 217 /* GPIO initialize */ 218 cr = GPIO_READ(sc, SAGPIO_AFR); 219 cr &= ~(GPIO_ALT_SSP_TXD | GPIO_ALT_SSP_RXD | GPIO_ALT_SSP_SCLK | 220 GPIO_ALT_SSP_SFRM); 221 cr |= GPIO_ALT_SSP_CLK; 222 GPIO_WRITE(sc, SAGPIO_AFR, cr); 223 224 cr = GPIO_READ(sc, SAGPIO_PDR); 225 cr &= ~GPIO_ALT_SSP_CLK; 226 GPIO_WRITE(sc, SAGPIO_PDR, cr); 227 228 /* SSP initialize & enable */ 229 SSP_WRITE(sc, SASSP_CR1, CR1_ECS); 230 cr = 0xF | (CR0_FRF_MASK & (1<<4)) | (CR0_SCR_MASK & (3<<8)) | CR0_SSE; 231 SSP_WRITE(sc, SASSP_CR0, cr); 232 233 /* Enable the audio power */ 234 sc->sc_parent->ipaq_egpio |= 235 (EGPIO_H3600_AUD_PWRON | EGPIO_H3600_AUD_ON); 236 sc->sc_parent->ipaq_egpio &= 237 ~(EGPIO_H3600_CODEC_RESET | EGPIO_H3600_QMUTE); 238 EGPIO_WRITE(sc); 239 240 /* external clock configured for 44100 samples/sec */ 241 cr = GPIO_READ(sc, SAGPIO_PDR); 242 cr |= (GPIO_H3600_CLK_SET0 | GPIO_H3600_CLK_SET1); 243 GPIO_WRITE(sc, SAGPIO_PDR, cr); 244 GPIO_WRITE(sc, SAGPIO_PSR, GPIO_H3600_CLK_SET0); 245 GPIO_WRITE(sc, SAGPIO_PCR, GPIO_H3600_CLK_SET1); 246 247 /* wait for power on */ 248 delay(100*1000); 249 sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CODEC_RESET; 250 EGPIO_WRITE(sc); 251 252 /* Wait for the UDA1341 to wake up */ 253 delay(100*1000); 254 } 255 256 static void 257 uda1341_reset(sc) 258 struct uda1341_softc *sc; 259 { 260 u_int8_t command; 261 262 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_STATUS; 263 DIRECT_REG.data0 = STATUS0_RST | STATUS0_SC_256 | STATUS0_IF_LSB16; 264 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 265 266 sc->sc_parent->ipaq_egpio &= ~EGPIO_H3600_CODEC_RESET; 267 EGPIO_WRITE(sc); 268 sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CODEC_RESET; 269 EGPIO_WRITE(sc); 270 271 DIRECT_REG.data0 &= ~STATUS0_RST; 272 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 273 } 274 275 static void 276 uda1341_reginit(sc) 277 struct uda1341_softc *sc; 278 { 279 u_int8_t command; 280 281 /* STATUS 0 */ 282 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_STATUS; 283 DIRECT_REG.data0 = STATUS0_SC_256 | STATUS0_IF_LSB16; 284 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 285 286 /* STATUS 1 */ 287 DIRECT_REG.data0 = STATUS1_OGS | STATUS1_IGS | (1<<7); 288 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 289 290 /* DATA 0 */ 291 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_DATA0; 292 DIRECT_REG.data0 = DATA0_VC(100) | DATA0_COMMON; 293 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 294 295 /* DATA 1 */ 296 DIRECT_REG.data0 = DATA1_BB(0) | DATA1_TR(0) | DATA1_COMMON; 297 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 298 299 /* DATA 2*/ 300 DIRECT_REG.data0 = DATA2_PP | DATA2_COMMON; 301 L3_write(sc, command, (u_int8_t *) &DIRECT_REG, 1); 302 303 /* Extended DATA 0 */ 304 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E0; 305 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ; 306 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 307 308 /* Extended DATA 1 */ 309 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E1; 310 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ; 311 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 312 313 /* Extended DATA 2 */ 314 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E2; 315 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E2_MS(30); 316 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 317 318 /* Extended DATA 3 */ 319 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E3; 320 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E3_IG_L(0); 321 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 322 323 /* Extended DATA 4 */ 324 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E4; 325 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E4_IG_H(0); 326 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 327 328 /* Extended DATA 5 */ 329 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E5; 330 EXTEND_REG.data1 = EXT_DATA_COMMN; 331 L3_write(sc, command, (u_int8_t *) &EXTEND_REG, 2); 332 } 333 334 static int 335 L3_getbit(sc) 336 struct uda1341_softc *sc; 337 { 338 int cr, data; 339 340 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 341 delay(L3_CLK_LOW); 342 343 cr = GPIO_READ(sc, SAGPIO_PLR); 344 data = (cr & L3_DATA) ? 1 : 0; 345 346 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 347 delay(L3_CLK_HIGH); 348 349 return (data); 350 } 351 352 static void 353 L3_sendbit(sc, bit) 354 struct uda1341_softc *sc; 355 int bit; 356 { 357 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 358 359 if (bit & 0x01) 360 GPIO_WRITE(sc, SAGPIO_PSR, L3_DATA); 361 else 362 GPIO_WRITE(sc, SAGPIO_PCR, L3_DATA); 363 364 delay(L3_CLK_LOW); 365 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 366 delay(L3_CLK_HIGH); 367 } 368 369 static u_int8_t 370 L3_getbyte(sc, mode) 371 struct uda1341_softc *sc; 372 int mode; 373 { 374 int i; 375 u_int8_t data; 376 377 switch (mode) { 378 case 0: /* Address mode */ 379 case 1: /* First data byte */ 380 break; 381 default: /* second data byte via halt-Time */ 382 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 383 delay(L3_HALT); 384 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 385 break; 386 } 387 388 delay(L3_MODE_SETUP); 389 390 for (i = 0; i < 8; i++) 391 data |= (L3_getbit(sc) << i); 392 393 delay(L3_MODE_HOLD); 394 395 return (data); 396 } 397 398 static void 399 L3_sendbyte(sc, data, mode) 400 struct uda1341_softc *sc; 401 u_int8_t data; 402 int mode; 403 { 404 int i; 405 406 switch (mode) { 407 case 0: /* Address mode */ 408 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 409 break; 410 case 1: /* First data byte */ 411 break; 412 default: /* second data byte via halt-Time */ 413 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 414 delay(L3_HALT); 415 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 416 break; 417 } 418 419 delay(L3_MODE_SETUP); 420 421 for (i = 0; i < 8; i++) 422 L3_sendbit(sc, data >> i); 423 424 if (mode == 0) /* Address mode */ 425 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 426 427 delay(L3_MODE_HOLD); 428 } 429 430 static int 431 L3_read(sc, addr, data, len) 432 struct uda1341_softc *sc; 433 u_int8_t addr, *data; 434 int len; 435 { 436 int cr, mode; 437 mode = 0; 438 439 uda1341_output_high(sc); 440 L3_sendbyte(sc, addr, mode++); 441 442 cr = GPIO_READ(sc, SAGPIO_PDR); 443 cr &= ~(L3_DATA); 444 GPIO_WRITE(sc, SAGPIO_PDR, cr); 445 446 while(len--) 447 *data++ = L3_getbyte(sc, mode++); 448 uda1341_output_low(sc); 449 450 return len; 451 } 452 453 static int 454 L3_write(sc, addr, data, len) 455 struct uda1341_softc *sc; 456 u_int8_t addr, *data; 457 int len; 458 { 459 int mode = 0; 460 461 uda1341_output_high(sc); 462 L3_sendbyte(sc, addr, mode++); 463 while(len--) 464 L3_sendbyte(sc, *data++, mode++); 465 uda1341_output_low(sc); 466 467 return len; 468 } 469
Indexes created Wed Sep 24 14:09:57 GMT 2025