uda1341.c revision 1.15.68.1
1 /* $NetBSD: uda1341.c,v 1.15.68.1 2021/03/20 19:33:35 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA (ichiro (at) ichiro.org). 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: uda1341.c,v 1.15.68.1 2021/03/20 19:33:35 thorpej Exp $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/file.h> 39 #include <sys/device.h> 40 #include <sys/kernel.h> 41 #include <sys/kthread.h> 42 #include <sys/malloc.h> 43 #include <sys/bus.h> 44 45 #include <hpcarm/dev/ipaq_saipvar.h> 46 #include <hpcarm/dev/ipaq_gpioreg.h> 47 #include <hpcarm/dev/uda1341.h> 48 49 #include <arm/sa11x0/sa11x0_gpioreg.h> 50 #include <arm/sa11x0/sa11x0_sspreg.h> 51 52 struct uda1341_softc { 53 device_t sc_dev; 54 bus_space_tag_t sc_iot; 55 bus_space_handle_t sc_ioh; 56 struct ipaq_softc *sc_parent; 57 }; 58 59 static int uda1341_match(device_t, cfdata_t, void *); 60 static void uda1341_attach(device_t, device_t, void *); 61 static int uda1341_print(void *, const char *); 62 static int uda1341_search(device_t, cfdata_t, const int *, void *); 63 64 static void uda1341_output_high(struct uda1341_softc *); 65 static void uda1341_output_low(struct uda1341_softc *); 66 static void uda1341_L3_init(struct uda1341_softc *); 67 static void uda1341_init(struct uda1341_softc *); 68 static void uda1341_reset(struct uda1341_softc *); 69 static void uda1341_reginit(struct uda1341_softc *); 70 71 #if 0 72 static int L3_getbit(struct uda1341_softc *); 73 #endif 74 static void L3_sendbit(struct uda1341_softc *, int); 75 #if 0 76 static uint8_t L3_getbyte(struct uda1341_softc *, int); 77 #endif 78 static void L3_sendbyte(struct uda1341_softc *, uint8_t, int); 79 #if 0 80 static int L3_read(struct uda1341_softc *, uint8_t, uint8_t *, int); 81 #endif 82 static int L3_write(struct uda1341_softc *, uint8_t, uint8_t *, int); 83 84 CFATTACH_DECL_NEW(uda, sizeof(struct uda1341_softc), 85 uda1341_match, uda1341_attach, NULL, NULL); 86 87 /* 88 * Philips L3 bus support. 89 * GPIO lines are used for clock, data and mode pins. 90 */ 91 #define L3_DATA GPIO_H3600_L3_DATA 92 #define L3_MODE GPIO_H3600_L3_MODE 93 #define L3_CLK GPIO_H3600_L3_CLK 94 95 static struct { 96 uint8_t data0; /* direct addressing register */ 97 } DIRECT_REG = {0}; 98 99 static struct { 100 uint8_t data0; /* extended addressing register 1 */ 101 uint8_t data1; /* extended addressing register 2 */ 102 } EXTEND_REG = {0, 0}; 103 104 /* 105 * register space access macros 106 */ 107 #define GPIO_WRITE(sc, reg, val) \ 108 bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg, val) 109 #define GPIO_READ(sc, reg) \ 110 bus_space_read_4(sc->sc_iot, sc->sc_parent->sc_gpioh, reg) 111 #define EGPIO_WRITE(sc) \ 112 bus_space_write_2(sc->sc_iot, sc->sc_parent->sc_egpioh, \ 113 0, sc->sc_parent->ipaq_egpio) 114 #define SSP_WRITE(sc, reg, val) \ 115 bus_space_write_4(sc->sc_iot, sc->sc_parent->sc_ssph, reg, val) 116 117 static int 118 uda1341_match(device_t parent, cfdata_t cf, void *aux) 119 { 120 return (1); 121 } 122 123 static void 124 uda1341_attach(device_t parent, device_t self, void *aux) 125 { 126 struct uda1341_softc *sc = device_private(self); 127 struct ipaq_softc *psc = device_private(parent); 128 129 aprint_normal("\n"); 130 aprint_normal_dev(self, "UDA1341 CODEC\n"); 131 132 sc->sc_dev = self; 133 sc->sc_iot = psc->sc_iot; 134 sc->sc_ioh = psc->sc_ioh; 135 sc->sc_parent = psc; 136 137 uda1341_L3_init(sc); 138 uda1341_init(sc); 139 140 uda1341_reset(sc); 141 142 uda1341_reginit(sc); 143 144 145 /* 146 * Attach each devices 147 */ 148 149 config_search(self, NULL, 150 CFARG_SUBMATCH, uda1341_search, 151 CFARG_IATTR, "udaif", 152 CFARG_EOL); 153 } 154 155 static int 156 uda1341_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 157 { 158 if (config_match(parent, cf, NULL) > 0) 159 config_attach(parent, cf, NULL, uda1341_print); 160 return 0; 161 } 162 163 164 static int 165 uda1341_print(void *aux, const char *name) 166 { 167 return (UNCONF); 168 } 169 170 static void 171 uda1341_output_high(struct uda1341_softc *sc) 172 { 173 int cr; 174 175 GPIO_WRITE(sc, SAGPIO_PSR, (L3_DATA | L3_MODE | L3_CLK)); 176 cr = GPIO_READ(sc, SAGPIO_PDR) | (L3_DATA | L3_MODE | L3_CLK); 177 GPIO_WRITE(sc, SAGPIO_PDR, cr); 178 } 179 180 static void 181 uda1341_output_low(struct uda1341_softc *sc) 182 { 183 int cr; 184 185 cr = GPIO_READ(sc, SAGPIO_PDR); 186 cr &= ~(L3_DATA | L3_MODE | L3_CLK); 187 GPIO_WRITE(sc, SAGPIO_PDR, cr); 188 } 189 190 static void 191 uda1341_L3_init(struct uda1341_softc *sc) 192 { 193 int cr; 194 195 cr = GPIO_READ(sc, SAGPIO_AFR); 196 cr &= ~(L3_DATA | L3_MODE | L3_CLK); 197 GPIO_WRITE(sc, SAGPIO_AFR, cr); 198 199 uda1341_output_low(sc); 200 } 201 202 static void 203 uda1341_init(struct uda1341_softc *sc) 204 { 205 int cr; 206 207 /* GPIO initialize */ 208 cr = GPIO_READ(sc, SAGPIO_AFR); 209 cr &= ~(GPIO_ALT_SSP_TXD | GPIO_ALT_SSP_RXD | GPIO_ALT_SSP_SCLK | 210 GPIO_ALT_SSP_SFRM); 211 cr |= GPIO_ALT_SSP_CLK; 212 GPIO_WRITE(sc, SAGPIO_AFR, cr); 213 214 cr = GPIO_READ(sc, SAGPIO_PDR); 215 cr &= ~GPIO_ALT_SSP_CLK; 216 GPIO_WRITE(sc, SAGPIO_PDR, cr); 217 218 /* SSP initialize & enable */ 219 SSP_WRITE(sc, SASSP_CR1, CR1_ECS); 220 cr = 0xF | (CR0_FRF_MASK & (1<<4)) | (CR0_SCR_MASK & (3<<8)) | CR0_SSE; 221 SSP_WRITE(sc, SASSP_CR0, cr); 222 223 /* Enable the audio power */ 224 sc->sc_parent->ipaq_egpio |= 225 (EGPIO_H3600_AUD_PWRON | EGPIO_H3600_AUD_ON); 226 sc->sc_parent->ipaq_egpio &= 227 ~(EGPIO_H3600_CODEC_RESET | EGPIO_H3600_QMUTE); 228 EGPIO_WRITE(sc); 229 230 /* external clock configured for 44100 samples/sec */ 231 cr = GPIO_READ(sc, SAGPIO_PDR); 232 cr |= (GPIO_H3600_CLK_SET0 | GPIO_H3600_CLK_SET1); 233 GPIO_WRITE(sc, SAGPIO_PDR, cr); 234 GPIO_WRITE(sc, SAGPIO_PSR, GPIO_H3600_CLK_SET0); 235 GPIO_WRITE(sc, SAGPIO_PCR, GPIO_H3600_CLK_SET1); 236 237 /* wait for power on */ 238 delay(100*1000); 239 sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CODEC_RESET; 240 EGPIO_WRITE(sc); 241 242 /* Wait for the UDA1341 to wake up */ 243 delay(100*1000); 244 } 245 246 static void 247 uda1341_reset(struct uda1341_softc *sc) 248 { 249 uint8_t command; 250 251 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_STATUS; 252 DIRECT_REG.data0 = STATUS0_RST | STATUS0_SC_256 | STATUS0_IF_LSB16; 253 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 254 255 sc->sc_parent->ipaq_egpio &= ~EGPIO_H3600_CODEC_RESET; 256 EGPIO_WRITE(sc); 257 sc->sc_parent->ipaq_egpio |= EGPIO_H3600_CODEC_RESET; 258 EGPIO_WRITE(sc); 259 260 DIRECT_REG.data0 &= ~STATUS0_RST; 261 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 262 } 263 264 static void 265 uda1341_reginit(struct uda1341_softc *sc) 266 { 267 uint8_t command; 268 269 /* STATUS 0 */ 270 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_STATUS; 271 DIRECT_REG.data0 = STATUS0_SC_256 | STATUS0_IF_LSB16; 272 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 273 274 /* STATUS 1 */ 275 DIRECT_REG.data0 = STATUS1_OGS | STATUS1_IGS | (1<<7); 276 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 277 278 /* DATA 0 */ 279 command = (L3_ADDRESS_COM << 2) | L3_ADDRESS_DATA0; 280 DIRECT_REG.data0 = DATA0_VC(100) | DATA0_COMMON; 281 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 282 283 /* DATA 1 */ 284 DIRECT_REG.data0 = DATA1_BB(0) | DATA1_TR(0) | DATA1_COMMON; 285 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 286 287 /* DATA 2*/ 288 DIRECT_REG.data0 = DATA2_PP | DATA2_COMMON; 289 L3_write(sc, command, (uint8_t *) &DIRECT_REG, 1); 290 291 /* Extended DATA 0 */ 292 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E0; 293 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ; 294 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 295 296 /* Extended DATA 1 */ 297 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E1; 298 EXTEND_REG.data1 = EXT_DATA_COMMN | 0x4 ; 299 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 300 301 /* Extended DATA 2 */ 302 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E2; 303 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E2_MS(30); 304 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 305 306 /* Extended DATA 3 */ 307 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E3; 308 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E3_IG_L(0); 309 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 310 311 /* Extended DATA 4 */ 312 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E4; 313 EXTEND_REG.data1 = EXT_DATA_COMMN | DATA_E4_IG_H(0); 314 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 315 316 /* Extended DATA 5 */ 317 EXTEND_REG.data0 = EXT_ADDR_COMMON | EXT_ADDR_E5; 318 EXTEND_REG.data1 = EXT_DATA_COMMN; 319 L3_write(sc, command, (uint8_t *) &EXTEND_REG, 2); 320 } 321 322 #if 0 323 static int 324 L3_getbit(struct uda1341_softc *sc) 325 { 326 int cr, data; 327 328 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 329 delay(L3_CLK_LOW); 330 331 cr = GPIO_READ(sc, SAGPIO_PLR); 332 data = (cr & L3_DATA) ? 1 : 0; 333 334 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 335 delay(L3_CLK_HIGH); 336 337 return (data); 338 } 339 #endif 340 341 static void 342 L3_sendbit(struct uda1341_softc *sc, int bit) 343 { 344 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 345 346 if (bit & 0x01) 347 GPIO_WRITE(sc, SAGPIO_PSR, L3_DATA); 348 else 349 GPIO_WRITE(sc, SAGPIO_PCR, L3_DATA); 350 351 delay(L3_CLK_LOW); 352 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 353 delay(L3_CLK_HIGH); 354 } 355 356 #if 0 357 static uint8_t 358 L3_getbyte(struct uda1341_softc *sc, int mode) 359 { 360 int i; 361 uint8_t data; 362 363 switch (mode) { 364 case 0: /* Address mode */ 365 case 1: /* First data byte */ 366 break; 367 default: /* second data byte via halt-Time */ 368 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 369 delay(L3_HALT); 370 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 371 break; 372 } 373 374 delay(L3_MODE_SETUP); 375 376 for (i = 0; i < 8; i++) 377 data |= (L3_getbit(sc) << i); 378 379 delay(L3_MODE_HOLD); 380 381 return (data); 382 } 383 #endif 384 385 static void 386 L3_sendbyte(struct uda1341_softc *sc, uint8_t data, int mode) 387 { 388 int i; 389 390 switch (mode) { 391 case 0: /* Address mode */ 392 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 393 break; 394 case 1: /* First data byte */ 395 break; 396 default: /* second data byte via halt-Time */ 397 GPIO_WRITE(sc, SAGPIO_PCR, L3_CLK); /* Clock down */ 398 delay(L3_HALT); 399 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 400 break; 401 } 402 403 delay(L3_MODE_SETUP); 404 405 for (i = 0; i < 8; i++) 406 L3_sendbit(sc, data >> i); 407 408 if (mode == 0) /* Address mode */ 409 GPIO_WRITE(sc, SAGPIO_PSR, L3_CLK); /* Clock up */ 410 411 delay(L3_MODE_HOLD); 412 } 413 414 #if 0 415 static int 416 L3_read(struct uda1341_softc *sc, uint8_t addr, uint8_t *data, int len) 417 { 418 int cr, mode; 419 mode = 0; 420 421 uda1341_output_high(sc); 422 L3_sendbyte(sc, addr, mode++); 423 424 cr = GPIO_READ(sc, SAGPIO_PDR); 425 cr &= ~(L3_DATA); 426 GPIO_WRITE(sc, SAGPIO_PDR, cr); 427 428 while(len--) 429 *data++ = L3_getbyte(sc, mode++); 430 uda1341_output_low(sc); 431 432 return len; 433 } 434 #endif 435 436 static int 437 L3_write(struct uda1341_softc *sc, uint8_t addr, uint8_t *data, int len) 438 { 439 int mode = 0; 440 441 uda1341_output_high(sc); 442 L3_sendbyte(sc, addr, mode++); 443 while(len--) 444 L3_sendbyte(sc, *data++, mode++); 445 uda1341_output_low(sc); 446 447 return len; 448 } 449
Indexes created Wed Oct 01 19:09:53 GMT 2025