wzero3_ssp.c revision 1.3.2.2
1 1.3.2.2 rmind /* $NetBSD: wzero3_ssp.c,v 1.3.2.2 2010/05/30 05:16:51 rmind Exp $ */ 2 1.3.2.2 rmind 3 1.3.2.2 rmind /* 4 1.3.2.2 rmind * Copyright (c) 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 1.3.2.2 rmind * All rights reserved. 6 1.3.2.2 rmind * 7 1.3.2.2 rmind * Redistribution and use in source and binary forms, with or without 8 1.3.2.2 rmind * modification, are permitted provided that the following conditions 9 1.3.2.2 rmind * are met: 10 1.3.2.2 rmind * 1. Redistributions of source code must retain the above copyright 11 1.3.2.2 rmind * notice, this list of conditions and the following disclaimer. 12 1.3.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 13 1.3.2.2 rmind * notice, this list of conditions and the following disclaimer in the 14 1.3.2.2 rmind * documentation and/or other materials provided with the distribution. 15 1.3.2.2 rmind * 16 1.3.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 1.3.2.2 rmind * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 1.3.2.2 rmind * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 1.3.2.2 rmind * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 1.3.2.2 rmind * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 1.3.2.2 rmind * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 1.3.2.2 rmind * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 1.3.2.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 1.3.2.2 rmind * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.3.2.2 rmind * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.3.2.2 rmind * SUCH DAMAGE. 27 1.3.2.2 rmind */ 28 1.3.2.2 rmind 29 1.3.2.2 rmind #include <sys/cdefs.h> 30 1.3.2.2 rmind __KERNEL_RCSID(0, "$NetBSD: wzero3_ssp.c,v 1.3.2.2 2010/05/30 05:16:51 rmind Exp $"); 31 1.3.2.2 rmind 32 1.3.2.2 rmind #include <sys/param.h> 33 1.3.2.2 rmind #include <sys/systm.h> 34 1.3.2.2 rmind #include <sys/device.h> 35 1.3.2.2 rmind #include <sys/mutex.h> 36 1.3.2.2 rmind #include <sys/pmf.h> 37 1.3.2.2 rmind #include <sys/bus.h> 38 1.3.2.2 rmind 39 1.3.2.2 rmind #include <machine/bootinfo.h> 40 1.3.2.2 rmind #include <machine/platid.h> 41 1.3.2.2 rmind #include <machine/platid_mask.h> 42 1.3.2.2 rmind 43 1.3.2.2 rmind #include <arm/xscale/pxa2x0reg.h> 44 1.3.2.2 rmind #include <arm/xscale/pxa2x0var.h> 45 1.3.2.2 rmind #include <arm/xscale/pxa2x0_gpio.h> 46 1.3.2.2 rmind 47 1.3.2.2 rmind #include <hpcarm/dev/wzero3_reg.h> 48 1.3.2.2 rmind #include <hpcarm/dev/wzero3_sspvar.h> 49 1.3.2.2 rmind 50 1.3.2.2 rmind #define WS003SH_SSCR0_MAX1233 0x0000048f /* 16bit/SPI/div by 5 */ 51 1.3.2.2 rmind #define WS007SH_SSCR0_ADS7846 0x000006ab /* 12bit/Microwire/div by 7 */ 52 1.3.2.2 rmind #define WS011SH_SSCR0_AK4184_TP 0x0010068f /* 32bit/SPI/div by 7 */ 53 1.3.2.2 rmind #define WS011SH_SSCR0_AK4184_TENKEY 0x0000068f /* 16bit/SPI/div by 7 */ 54 1.3.2.2 rmind 55 1.3.2.2 rmind struct wzero3ssp_model; 56 1.3.2.2 rmind struct wzero3ssp_softc { 57 1.3.2.2 rmind device_t sc_dev; 58 1.3.2.2 rmind bus_space_tag_t sc_iot; 59 1.3.2.2 rmind bus_space_handle_t sc_ioh; 60 1.3.2.2 rmind kmutex_t sc_mtx; 61 1.3.2.2 rmind const struct wzero3ssp_model *sc_model; 62 1.3.2.2 rmind }; 63 1.3.2.2 rmind 64 1.3.2.2 rmind static int wzero3ssp_match(device_t, cfdata_t, void *); 65 1.3.2.2 rmind static void wzero3ssp_attach(device_t, device_t, void *); 66 1.3.2.2 rmind 67 1.3.2.2 rmind CFATTACH_DECL_NEW(wzero3ssp, sizeof(struct wzero3ssp_softc), 68 1.3.2.2 rmind wzero3ssp_match, wzero3ssp_attach, NULL, NULL); 69 1.3.2.2 rmind 70 1.3.2.2 rmind static void wzero3ssp_init(struct wzero3ssp_softc *); 71 1.3.2.2 rmind static bool wzero3ssp_resume(device_t dv, const pmf_qual_t *); 72 1.3.2.2 rmind static uint32_t wzero3ssp_read_ads7846(struct wzero3ssp_softc *, uint32_t); 73 1.3.2.2 rmind static uint32_t wzero3ssp_read_max1233(struct wzero3ssp_softc *, uint32_t, 74 1.3.2.2 rmind uint32_t); 75 1.3.2.2 rmind static uint32_t wzero3ssp_read_ak4184(struct wzero3ssp_softc *, uint32_t); 76 1.3.2.2 rmind 77 1.3.2.2 rmind static struct wzero3ssp_softc *wzero3ssp_sc; 78 1.3.2.2 rmind 79 1.3.2.2 rmind static const struct wzero3ssp_model { 80 1.3.2.2 rmind platid_mask_t *platid; 81 1.3.2.2 rmind u_long sspaddr; 82 1.3.2.2 rmind } wzero3ssp_table[] = { 83 1.3.2.2 rmind /* WS003SH */ 84 1.3.2.2 rmind { 85 1.3.2.2 rmind &platid_mask_MACH_SHARP_WZERO3_WS003SH, 86 1.3.2.2 rmind PXA2X0_SSP2_BASE, 87 1.3.2.2 rmind }, 88 1.3.2.2 rmind /* WS004SH */ 89 1.3.2.2 rmind { 90 1.3.2.2 rmind &platid_mask_MACH_SHARP_WZERO3_WS004SH, 91 1.3.2.2 rmind PXA2X0_SSP2_BASE, 92 1.3.2.2 rmind }, 93 1.3.2.2 rmind /* WS007SH */ 94 1.3.2.2 rmind { 95 1.3.2.2 rmind &platid_mask_MACH_SHARP_WZERO3_WS007SH, 96 1.3.2.2 rmind PXA2X0_SSP1_BASE, 97 1.3.2.2 rmind }, 98 1.3.2.2 rmind /* WS011SH */ 99 1.3.2.2 rmind { 100 1.3.2.2 rmind &platid_mask_MACH_SHARP_WZERO3_WS011SH, 101 1.3.2.2 rmind PXA2X0_SSP1_BASE, 102 1.3.2.2 rmind }, 103 1.3.2.2 rmind #if 0 104 1.3.2.2 rmind /* WS0020H */ 105 1.3.2.2 rmind { 106 1.3.2.2 rmind &platid_mask_MACH_SHARP_WZERO3_WS020SH, 107 1.3.2.2 rmind PXA2X0_SSP1_BASE, 108 1.3.2.2 rmind }, 109 1.3.2.2 rmind #endif 110 1.3.2.2 rmind { 111 1.3.2.2 rmind NULL, 0, 112 1.3.2.2 rmind }, 113 1.3.2.2 rmind }; 114 1.3.2.2 rmind 115 1.3.2.2 rmind static const struct wzero3ssp_model * 116 1.3.2.2 rmind wzero3ssp_lookup(void) 117 1.3.2.2 rmind { 118 1.3.2.2 rmind const struct wzero3ssp_model *model; 119 1.3.2.2 rmind 120 1.3.2.2 rmind for (model = wzero3ssp_table; model->platid != NULL; model++) { 121 1.3.2.2 rmind if (platid_match(&platid, model->platid)) { 122 1.3.2.2 rmind return model; 123 1.3.2.2 rmind } 124 1.3.2.2 rmind } 125 1.3.2.2 rmind return NULL; 126 1.3.2.2 rmind } 127 1.3.2.2 rmind 128 1.3.2.2 rmind static int 129 1.3.2.2 rmind wzero3ssp_match(device_t parent, cfdata_t cf, void *aux) 130 1.3.2.2 rmind { 131 1.3.2.2 rmind 132 1.3.2.2 rmind if (strcmp(cf->cf_name, "wzero3ssp") != 0) 133 1.3.2.2 rmind return 0; 134 1.3.2.2 rmind if (wzero3ssp_lookup() == NULL) 135 1.3.2.2 rmind return 0; 136 1.3.2.2 rmind if (wzero3ssp_sc != NULL) 137 1.3.2.2 rmind return 0; 138 1.3.2.2 rmind return 1; 139 1.3.2.2 rmind } 140 1.3.2.2 rmind 141 1.3.2.2 rmind static void 142 1.3.2.2 rmind wzero3ssp_attach(device_t parent, device_t self, void *aux) 143 1.3.2.2 rmind { 144 1.3.2.2 rmind struct wzero3ssp_softc *sc = device_private(self); 145 1.3.2.2 rmind 146 1.3.2.2 rmind sc->sc_dev = self; 147 1.3.2.2 rmind wzero3ssp_sc = sc; 148 1.3.2.2 rmind 149 1.3.2.2 rmind aprint_normal("\n"); 150 1.3.2.2 rmind aprint_naive("\n"); 151 1.3.2.2 rmind 152 1.3.2.2 rmind sc->sc_model = wzero3ssp_lookup(); 153 1.3.2.2 rmind if (sc->sc_model == NULL) { 154 1.3.2.2 rmind aprint_error_dev(self, "unknown model\n"); 155 1.3.2.2 rmind return; 156 1.3.2.2 rmind } 157 1.3.2.2 rmind 158 1.3.2.2 rmind mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_TTY); 159 1.3.2.2 rmind 160 1.3.2.2 rmind sc->sc_iot = &pxa2x0_bs_tag; 161 1.3.2.2 rmind if (bus_space_map(sc->sc_iot, sc->sc_model->sspaddr, PXA2X0_SSP_SIZE, 0, 162 1.3.2.2 rmind &sc->sc_ioh)) { 163 1.3.2.2 rmind aprint_error_dev(sc->sc_dev, "can't map bus space\n"); 164 1.3.2.2 rmind return; 165 1.3.2.2 rmind } 166 1.3.2.2 rmind 167 1.3.2.2 rmind if (!pmf_device_register(sc->sc_dev, NULL, wzero3ssp_resume)) 168 1.3.2.2 rmind aprint_error_dev(sc->sc_dev, 169 1.3.2.2 rmind "couldn't establish power handler\n"); 170 1.3.2.2 rmind 171 1.3.2.2 rmind wzero3ssp_init(sc); 172 1.3.2.2 rmind } 173 1.3.2.2 rmind 174 1.3.2.2 rmind /* 175 1.3.2.2 rmind * Initialize the dedicated SSP unit and disable all chip selects. 176 1.3.2.2 rmind * This function is called with interrupts disabled. 177 1.3.2.2 rmind */ 178 1.3.2.2 rmind static void 179 1.3.2.2 rmind wzero3ssp_init(struct wzero3ssp_softc *sc) 180 1.3.2.2 rmind { 181 1.3.2.2 rmind 182 1.3.2.2 rmind if (sc->sc_model->sspaddr == PXA2X0_SSP1_BASE) 183 1.3.2.2 rmind pxa2x0_clkman_config(CKEN_SSP2, 1); 184 1.3.2.2 rmind else if (sc->sc_model->sspaddr == PXA2X0_SSP2_BASE) 185 1.3.2.2 rmind pxa2x0_clkman_config(CKEN_SSP3, 1); 186 1.3.2.2 rmind 187 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 188 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0); 189 1.3.2.2 rmind 190 1.3.2.2 rmind /* XXX */ 191 1.3.2.2 rmind if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH) 192 1.3.2.2 rmind || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)) { 193 1.3.2.2 rmind pxa2x0_gpio_set_function(39/*GPIO_WS003SH_XXX*/, 194 1.3.2.2 rmind GPIO_OUT|GPIO_SET); 195 1.3.2.2 rmind pxa2x0_gpio_set_function(GPIO_WS003SH_MAX1233_CS, 196 1.3.2.2 rmind GPIO_OUT|GPIO_SET); 197 1.3.2.2 rmind } 198 1.3.2.2 rmind if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) { 199 1.3.2.2 rmind pxa2x0_gpio_set_function(GPIO_WS007SH_ADS7846_CS, 200 1.3.2.2 rmind GPIO_OUT|GPIO_SET); 201 1.3.2.2 rmind } 202 1.3.2.2 rmind if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) { 203 1.3.2.2 rmind pxa2x0_gpio_set_function(GPIO_WS011SH_AK4184_CS, 204 1.3.2.2 rmind GPIO_OUT|GPIO_SET); 205 1.3.2.2 rmind } 206 1.3.2.2 rmind } 207 1.3.2.2 rmind 208 1.3.2.2 rmind static bool 209 1.3.2.2 rmind wzero3ssp_resume(device_t dv, const pmf_qual_t *qual) 210 1.3.2.2 rmind { 211 1.3.2.2 rmind struct wzero3ssp_softc *sc = device_private(dv); 212 1.3.2.2 rmind 213 1.3.2.2 rmind mutex_enter(&sc->sc_mtx); 214 1.3.2.2 rmind wzero3ssp_init(sc); 215 1.3.2.2 rmind mutex_exit(&sc->sc_mtx); 216 1.3.2.2 rmind 217 1.3.2.2 rmind return true; 218 1.3.2.2 rmind } 219 1.3.2.2 rmind 220 1.3.2.2 rmind /* 221 1.3.2.2 rmind * Transmit a single data word to one of the ICs, keep the chip selected 222 1.3.2.2 rmind * afterwards, and don't wait for data to be returned in SSDR. Interrupts 223 1.3.2.2 rmind * must be held off until wzero3ssp_ic_stop() gets called. 224 1.3.2.2 rmind */ 225 1.3.2.2 rmind void 226 1.3.2.2 rmind wzero3ssp_ic_start(int ic, uint32_t cmd) 227 1.3.2.2 rmind { 228 1.3.2.2 rmind struct wzero3ssp_softc *sc; 229 1.3.2.2 rmind 230 1.3.2.2 rmind KASSERT(wzero3ssp_sc != NULL); 231 1.3.2.2 rmind sc = wzero3ssp_sc; 232 1.3.2.2 rmind 233 1.3.2.2 rmind mutex_enter(&sc->sc_mtx); 234 1.3.2.2 rmind 235 1.3.2.2 rmind /* disable other ICs */ 236 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 237 1.3.2.2 rmind if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) { 238 1.3.2.2 rmind if (ic != WZERO3_SSP_IC_ADS7846) 239 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 240 1.3.2.2 rmind } 241 1.3.2.2 rmind if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) { 242 1.3.2.2 rmind if (ic != WZERO3_SSP_IC_AK4184) 243 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 244 1.3.2.2 rmind } 245 1.3.2.2 rmind 246 1.3.2.2 rmind /* activate the chosen one */ 247 1.3.2.2 rmind switch (ic) { 248 1.3.2.2 rmind case WZERO3_SSP_IC_ADS7846: 249 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 250 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 251 1.3.2.2 rmind WS007SH_SSCR0_ADS7846); 252 1.3.2.2 rmind pxa2x0_gpio_clear_bit(GPIO_WS007SH_ADS7846_CS); 253 1.3.2.2 rmind bus_space_write_1(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 254 1.3.2.2 rmind while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 255 1.3.2.2 rmind & SSSR_TNF) != SSSR_TNF) 256 1.3.2.2 rmind continue; /* poll */ 257 1.3.2.2 rmind break; 258 1.3.2.2 rmind case WZERO3_SSP_IC_AK4184: 259 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 260 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 261 1.3.2.2 rmind WS011SH_SSCR0_AK4184_TP); 262 1.3.2.2 rmind pxa2x0_gpio_clear_bit(GPIO_WS011SH_AK4184_CS); 263 1.3.2.2 rmind (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 264 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 265 1.3.2.2 rmind & SSSR_TNF)) 266 1.3.2.2 rmind continue; /* poll */ 267 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd << 16); 268 1.3.2.2 rmind while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 269 1.3.2.2 rmind & SSSR_BUSY) 270 1.3.2.2 rmind continue; /* poll */ 271 1.3.2.2 rmind break; 272 1.3.2.2 rmind case WZERO3_SSP_IC_MAX1233: 273 1.3.2.2 rmind case WZERO3_SSP_IC_NUM: 274 1.3.2.2 rmind default: 275 1.3.2.2 rmind break; 276 1.3.2.2 rmind } 277 1.3.2.2 rmind } 278 1.3.2.2 rmind 279 1.3.2.2 rmind /* 280 1.3.2.2 rmind * Read the last value from SSDR and deactivate all chip-selects. 281 1.3.2.2 rmind */ 282 1.3.2.2 rmind uint32_t 283 1.3.2.2 rmind wzero3ssp_ic_stop(int ic) 284 1.3.2.2 rmind { 285 1.3.2.2 rmind struct wzero3ssp_softc *sc; 286 1.3.2.2 rmind uint32_t rv; 287 1.3.2.2 rmind 288 1.3.2.2 rmind KASSERT(wzero3ssp_sc != NULL); 289 1.3.2.2 rmind sc = wzero3ssp_sc; 290 1.3.2.2 rmind 291 1.3.2.2 rmind switch (ic) { 292 1.3.2.2 rmind case WZERO3_SSP_IC_ADS7846: 293 1.3.2.2 rmind /* read result of last command */ 294 1.3.2.2 rmind while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 295 1.3.2.2 rmind & SSSR_RNE) != SSSR_RNE) 296 1.3.2.2 rmind continue; /* poll */ 297 1.3.2.2 rmind rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 298 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 299 1.3.2.2 rmind break; 300 1.3.2.2 rmind case WZERO3_SSP_IC_AK4184: 301 1.3.2.2 rmind /* read result of last command */ 302 1.3.2.2 rmind while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 303 1.3.2.2 rmind & SSSR_RNE) != SSSR_RNE) 304 1.3.2.2 rmind continue; /* poll */ 305 1.3.2.2 rmind rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 306 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 307 1.3.2.2 rmind break; 308 1.3.2.2 rmind case WZERO3_SSP_IC_MAX1233: 309 1.3.2.2 rmind case WZERO3_SSP_IC_NUM: 310 1.3.2.2 rmind default: 311 1.3.2.2 rmind rv = 0; 312 1.3.2.2 rmind break; 313 1.3.2.2 rmind } 314 1.3.2.2 rmind 315 1.3.2.2 rmind mutex_exit(&sc->sc_mtx); 316 1.3.2.2 rmind 317 1.3.2.2 rmind return rv; 318 1.3.2.2 rmind } 319 1.3.2.2 rmind 320 1.3.2.2 rmind /* 321 1.3.2.2 rmind * Activate one of the chip-select lines, transmit one word value in 322 1.3.2.2 rmind * each direction, and deactivate the chip-select again. 323 1.3.2.2 rmind */ 324 1.3.2.2 rmind uint32_t 325 1.3.2.2 rmind wzero3ssp_ic_send(int ic, uint32_t data, uint32_t data2) 326 1.3.2.2 rmind { 327 1.3.2.2 rmind struct wzero3ssp_softc *sc; 328 1.3.2.2 rmind 329 1.3.2.2 rmind if (wzero3ssp_sc == NULL) { 330 1.3.2.2 rmind aprint_error("%s: not configured\n", __func__); 331 1.3.2.2 rmind return 0; 332 1.3.2.2 rmind } 333 1.3.2.2 rmind sc = wzero3ssp_sc; 334 1.3.2.2 rmind 335 1.3.2.2 rmind switch (ic) { 336 1.3.2.2 rmind case WZERO3_SSP_IC_ADS7846: 337 1.3.2.2 rmind return wzero3ssp_read_ads7846(sc, data); 338 1.3.2.2 rmind case WZERO3_SSP_IC_MAX1233: 339 1.3.2.2 rmind return wzero3ssp_read_max1233(sc, data, data2); 340 1.3.2.2 rmind case WZERO3_SSP_IC_AK4184: 341 1.3.2.2 rmind return wzero3ssp_read_ak4184(sc, data); 342 1.3.2.2 rmind case WZERO3_SSP_IC_NUM: 343 1.3.2.2 rmind default: 344 1.3.2.2 rmind aprint_error("%s: invalid IC %d\n", __func__, ic); 345 1.3.2.2 rmind return 0; 346 1.3.2.2 rmind } 347 1.3.2.2 rmind } 348 1.3.2.2 rmind 349 1.3.2.2 rmind static uint32_t 350 1.3.2.2 rmind wzero3ssp_read_ads7846(struct wzero3ssp_softc *sc, uint32_t cmd) 351 1.3.2.2 rmind { 352 1.3.2.2 rmind uint32_t rv; 353 1.3.2.2 rmind 354 1.3.2.2 rmind mutex_enter(&sc->sc_mtx); 355 1.3.2.2 rmind 356 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 357 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 358 1.3.2.2 rmind WS007SH_SSCR0_ADS7846); 359 1.3.2.2 rmind 360 1.3.2.2 rmind pxa2x0_gpio_clear_bit(GPIO_WS007SH_ADS7846_CS); 361 1.3.2.2 rmind 362 1.3.2.2 rmind /* send cmd */ 363 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 364 1.3.2.2 rmind continue; /* poll */ 365 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 366 1.3.2.2 rmind while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 367 1.3.2.2 rmind continue; /* poll */ 368 1.3.2.2 rmind 369 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 370 1.3.2.2 rmind continue; /* poll */ 371 1.3.2.2 rmind rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 372 1.3.2.2 rmind 373 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 374 1.3.2.2 rmind 375 1.3.2.2 rmind mutex_exit(&sc->sc_mtx); 376 1.3.2.2 rmind 377 1.3.2.2 rmind return rv; 378 1.3.2.2 rmind } 379 1.3.2.2 rmind 380 1.3.2.2 rmind static uint32_t 381 1.3.2.2 rmind wzero3ssp_read_max1233(struct wzero3ssp_softc *sc, uint32_t cmd, uint32_t data) 382 1.3.2.2 rmind { 383 1.3.2.2 rmind uint32_t rv; 384 1.3.2.2 rmind 385 1.3.2.2 rmind mutex_enter(&sc->sc_mtx); 386 1.3.2.2 rmind 387 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 388 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 389 1.3.2.2 rmind WS003SH_SSCR0_MAX1233); 390 1.3.2.2 rmind 391 1.3.2.2 rmind pxa2x0_gpio_set_bit(39/*GPIO_WS003SH_XXX*/); 392 1.3.2.2 rmind pxa2x0_gpio_clear_bit(GPIO_WS003SH_MAX1233_CS); 393 1.3.2.2 rmind 394 1.3.2.2 rmind /* send cmd */ 395 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 396 1.3.2.2 rmind continue; /* poll */ 397 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 398 1.3.2.2 rmind while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 399 1.3.2.2 rmind continue; /* poll */ 400 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 401 1.3.2.2 rmind continue; /* poll */ 402 1.3.2.2 rmind (void)bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 403 1.3.2.2 rmind 404 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 405 1.3.2.2 rmind continue; /* poll */ 406 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data); 407 1.3.2.2 rmind while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 408 1.3.2.2 rmind continue; /* poll */ 409 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 410 1.3.2.2 rmind continue; /* poll */ 411 1.3.2.2 rmind rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 412 1.3.2.2 rmind 413 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS003SH_MAX1233_CS); 414 1.3.2.2 rmind 415 1.3.2.2 rmind mutex_exit(&sc->sc_mtx); 416 1.3.2.2 rmind 417 1.3.2.2 rmind return rv; 418 1.3.2.2 rmind } 419 1.3.2.2 rmind 420 1.3.2.2 rmind static uint32_t 421 1.3.2.2 rmind wzero3ssp_read_ak4184(struct wzero3ssp_softc *sc, uint32_t cmd) 422 1.3.2.2 rmind { 423 1.3.2.2 rmind uint32_t rv; 424 1.3.2.2 rmind 425 1.3.2.2 rmind mutex_enter(&sc->sc_mtx); 426 1.3.2.2 rmind 427 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 428 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 429 1.3.2.2 rmind WS011SH_SSCR0_AK4184_TP); 430 1.3.2.2 rmind 431 1.3.2.2 rmind pxa2x0_gpio_clear_bit(GPIO_WS011SH_AK4184_CS); 432 1.3.2.2 rmind 433 1.3.2.2 rmind (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 434 1.3.2.2 rmind 435 1.3.2.2 rmind /* send cmd */ 436 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 437 1.3.2.2 rmind continue; /* poll */ 438 1.3.2.2 rmind bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd << 16); 439 1.3.2.2 rmind while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 440 1.3.2.2 rmind continue; /* poll */ 441 1.3.2.2 rmind 442 1.3.2.2 rmind while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 443 1.3.2.2 rmind continue; /* poll */ 444 1.3.2.2 rmind rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 445 1.3.2.2 rmind 446 1.3.2.2 rmind pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 447 1.3.2.2 rmind 448 1.3.2.2 rmind mutex_exit(&sc->sc_mtx); 449 1.3.2.2 rmind 450 1.3.2.2 rmind return rv; 451 1.3.2.2 rmind } 452
Indexes created Thu Oct 02 01:09:59 GMT 2025