wzero3_ssp.c revision 1.3
1 /* $NetBSD: wzero3_ssp.c,v 1.3 2010/05/22 15:37:58 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 2010 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: wzero3_ssp.c,v 1.3 2010/05/22 15:37:58 nonaka Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/mutex.h> 36 #include <sys/pmf.h> 37 #include <sys/bus.h> 38 39 #include <machine/bootinfo.h> 40 #include <machine/platid.h> 41 #include <machine/platid_mask.h> 42 43 #include <arm/xscale/pxa2x0reg.h> 44 #include <arm/xscale/pxa2x0var.h> 45 #include <arm/xscale/pxa2x0_gpio.h> 46 47 #include <hpcarm/dev/wzero3_reg.h> 48 #include <hpcarm/dev/wzero3_sspvar.h> 49 50 #define WS003SH_SSCR0_MAX1233 0x0000048f /* 16bit/SPI/div by 5 */ 51 #define WS007SH_SSCR0_ADS7846 0x000006ab /* 12bit/Microwire/div by 7 */ 52 #define WS011SH_SSCR0_AK4184_TP 0x0010068f /* 32bit/SPI/div by 7 */ 53 #define WS011SH_SSCR0_AK4184_TENKEY 0x0000068f /* 16bit/SPI/div by 7 */ 54 55 struct wzero3ssp_model; 56 struct wzero3ssp_softc { 57 device_t sc_dev; 58 bus_space_tag_t sc_iot; 59 bus_space_handle_t sc_ioh; 60 kmutex_t sc_mtx; 61 const struct wzero3ssp_model *sc_model; 62 }; 63 64 static int wzero3ssp_match(device_t, cfdata_t, void *); 65 static void wzero3ssp_attach(device_t, device_t, void *); 66 67 CFATTACH_DECL_NEW(wzero3ssp, sizeof(struct wzero3ssp_softc), 68 wzero3ssp_match, wzero3ssp_attach, NULL, NULL); 69 70 static void wzero3ssp_init(struct wzero3ssp_softc *); 71 static bool wzero3ssp_resume(device_t dv, const pmf_qual_t *); 72 static uint32_t wzero3ssp_read_ads7846(struct wzero3ssp_softc *, uint32_t); 73 static uint32_t wzero3ssp_read_max1233(struct wzero3ssp_softc *, uint32_t, 74 uint32_t); 75 static uint32_t wzero3ssp_read_ak4184(struct wzero3ssp_softc *, uint32_t); 76 77 static struct wzero3ssp_softc *wzero3ssp_sc; 78 79 static const struct wzero3ssp_model { 80 platid_mask_t *platid; 81 u_long sspaddr; 82 } wzero3ssp_table[] = { 83 /* WS003SH */ 84 { 85 &platid_mask_MACH_SHARP_WZERO3_WS003SH, 86 PXA2X0_SSP2_BASE, 87 }, 88 /* WS004SH */ 89 { 90 &platid_mask_MACH_SHARP_WZERO3_WS004SH, 91 PXA2X0_SSP2_BASE, 92 }, 93 /* WS007SH */ 94 { 95 &platid_mask_MACH_SHARP_WZERO3_WS007SH, 96 PXA2X0_SSP1_BASE, 97 }, 98 /* WS011SH */ 99 { 100 &platid_mask_MACH_SHARP_WZERO3_WS011SH, 101 PXA2X0_SSP1_BASE, 102 }, 103 #if 0 104 /* WS0020H */ 105 { 106 &platid_mask_MACH_SHARP_WZERO3_WS020SH, 107 PXA2X0_SSP1_BASE, 108 }, 109 #endif 110 { 111 NULL, 0, 112 }, 113 }; 114 115 static const struct wzero3ssp_model * 116 wzero3ssp_lookup(void) 117 { 118 const struct wzero3ssp_model *model; 119 120 for (model = wzero3ssp_table; model->platid != NULL; model++) { 121 if (platid_match(&platid, model->platid)) { 122 return model; 123 } 124 } 125 return NULL; 126 } 127 128 static int 129 wzero3ssp_match(device_t parent, cfdata_t cf, void *aux) 130 { 131 132 if (strcmp(cf->cf_name, "wzero3ssp") != 0) 133 return 0; 134 if (wzero3ssp_lookup() == NULL) 135 return 0; 136 if (wzero3ssp_sc != NULL) 137 return 0; 138 return 1; 139 } 140 141 static void 142 wzero3ssp_attach(device_t parent, device_t self, void *aux) 143 { 144 struct wzero3ssp_softc *sc = device_private(self); 145 146 sc->sc_dev = self; 147 wzero3ssp_sc = sc; 148 149 aprint_normal("\n"); 150 aprint_naive("\n"); 151 152 sc->sc_model = wzero3ssp_lookup(); 153 if (sc->sc_model == NULL) { 154 aprint_error_dev(self, "unknown model\n"); 155 return; 156 } 157 158 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_TTY); 159 160 sc->sc_iot = &pxa2x0_bs_tag; 161 if (bus_space_map(sc->sc_iot, sc->sc_model->sspaddr, PXA2X0_SSP_SIZE, 0, 162 &sc->sc_ioh)) { 163 aprint_error_dev(sc->sc_dev, "can't map bus space\n"); 164 return; 165 } 166 167 if (!pmf_device_register(sc->sc_dev, NULL, wzero3ssp_resume)) 168 aprint_error_dev(sc->sc_dev, 169 "couldn't establish power handler\n"); 170 171 wzero3ssp_init(sc); 172 } 173 174 /* 175 * Initialize the dedicated SSP unit and disable all chip selects. 176 * This function is called with interrupts disabled. 177 */ 178 static void 179 wzero3ssp_init(struct wzero3ssp_softc *sc) 180 { 181 182 if (sc->sc_model->sspaddr == PXA2X0_SSP1_BASE) 183 pxa2x0_clkman_config(CKEN_SSP2, 1); 184 else if (sc->sc_model->sspaddr == PXA2X0_SSP2_BASE) 185 pxa2x0_clkman_config(CKEN_SSP3, 1); 186 187 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 188 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR1, 0); 189 190 /* XXX */ 191 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS003SH) 192 || platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS004SH)) { 193 pxa2x0_gpio_set_function(39/*GPIO_WS003SH_XXX*/, 194 GPIO_OUT|GPIO_SET); 195 pxa2x0_gpio_set_function(GPIO_WS003SH_MAX1233_CS, 196 GPIO_OUT|GPIO_SET); 197 } 198 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) { 199 pxa2x0_gpio_set_function(GPIO_WS007SH_ADS7846_CS, 200 GPIO_OUT|GPIO_SET); 201 } 202 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) { 203 pxa2x0_gpio_set_function(GPIO_WS011SH_AK4184_CS, 204 GPIO_OUT|GPIO_SET); 205 } 206 } 207 208 static bool 209 wzero3ssp_resume(device_t dv, const pmf_qual_t *qual) 210 { 211 struct wzero3ssp_softc *sc = device_private(dv); 212 213 mutex_enter(&sc->sc_mtx); 214 wzero3ssp_init(sc); 215 mutex_exit(&sc->sc_mtx); 216 217 return true; 218 } 219 220 /* 221 * Transmit a single data word to one of the ICs, keep the chip selected 222 * afterwards, and don't wait for data to be returned in SSDR. Interrupts 223 * must be held off until wzero3ssp_ic_stop() gets called. 224 */ 225 void 226 wzero3ssp_ic_start(int ic, uint32_t cmd) 227 { 228 struct wzero3ssp_softc *sc; 229 230 KASSERT(wzero3ssp_sc != NULL); 231 sc = wzero3ssp_sc; 232 233 mutex_enter(&sc->sc_mtx); 234 235 /* disable other ICs */ 236 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 237 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS007SH)) { 238 if (ic != WZERO3_SSP_IC_ADS7846) 239 pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 240 } 241 if (platid_match(&platid, &platid_mask_MACH_SHARP_WZERO3_WS011SH)) { 242 if (ic != WZERO3_SSP_IC_AK4184) 243 pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 244 } 245 246 /* activate the chosen one */ 247 switch (ic) { 248 case WZERO3_SSP_IC_ADS7846: 249 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 250 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 251 WS007SH_SSCR0_ADS7846); 252 pxa2x0_gpio_clear_bit(GPIO_WS007SH_ADS7846_CS); 253 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 254 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 255 & SSSR_TNF) != SSSR_TNF) 256 continue; /* poll */ 257 break; 258 case WZERO3_SSP_IC_AK4184: 259 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 260 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 261 WS011SH_SSCR0_AK4184_TP); 262 pxa2x0_gpio_clear_bit(GPIO_WS011SH_AK4184_CS); 263 (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 264 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 265 & SSSR_TNF)) 266 continue; /* poll */ 267 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd << 16); 268 while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 269 & SSSR_BUSY) 270 continue; /* poll */ 271 break; 272 case WZERO3_SSP_IC_MAX1233: 273 case WZERO3_SSP_IC_NUM: 274 default: 275 break; 276 } 277 } 278 279 /* 280 * Read the last value from SSDR and deactivate all chip-selects. 281 */ 282 uint32_t 283 wzero3ssp_ic_stop(int ic) 284 { 285 struct wzero3ssp_softc *sc; 286 uint32_t rv; 287 288 KASSERT(wzero3ssp_sc != NULL); 289 sc = wzero3ssp_sc; 290 291 switch (ic) { 292 case WZERO3_SSP_IC_ADS7846: 293 /* read result of last command */ 294 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 295 & SSSR_RNE) != SSSR_RNE) 296 continue; /* poll */ 297 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 298 pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 299 break; 300 case WZERO3_SSP_IC_AK4184: 301 /* read result of last command */ 302 while ((bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) 303 & SSSR_RNE) != SSSR_RNE) 304 continue; /* poll */ 305 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 306 pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 307 break; 308 case WZERO3_SSP_IC_MAX1233: 309 case WZERO3_SSP_IC_NUM: 310 default: 311 rv = 0; 312 break; 313 } 314 315 mutex_exit(&sc->sc_mtx); 316 317 return rv; 318 } 319 320 /* 321 * Activate one of the chip-select lines, transmit one word value in 322 * each direction, and deactivate the chip-select again. 323 */ 324 uint32_t 325 wzero3ssp_ic_send(int ic, uint32_t data, uint32_t data2) 326 { 327 struct wzero3ssp_softc *sc; 328 329 if (wzero3ssp_sc == NULL) { 330 aprint_error("%s: not configured\n", __func__); 331 return 0; 332 } 333 sc = wzero3ssp_sc; 334 335 switch (ic) { 336 case WZERO3_SSP_IC_ADS7846: 337 return wzero3ssp_read_ads7846(sc, data); 338 case WZERO3_SSP_IC_MAX1233: 339 return wzero3ssp_read_max1233(sc, data, data2); 340 case WZERO3_SSP_IC_AK4184: 341 return wzero3ssp_read_ak4184(sc, data); 342 case WZERO3_SSP_IC_NUM: 343 default: 344 aprint_error("%s: invalid IC %d\n", __func__, ic); 345 return 0; 346 } 347 } 348 349 static uint32_t 350 wzero3ssp_read_ads7846(struct wzero3ssp_softc *sc, uint32_t cmd) 351 { 352 uint32_t rv; 353 354 mutex_enter(&sc->sc_mtx); 355 356 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 357 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 358 WS007SH_SSCR0_ADS7846); 359 360 pxa2x0_gpio_clear_bit(GPIO_WS007SH_ADS7846_CS); 361 362 /* send cmd */ 363 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 364 continue; /* poll */ 365 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 366 while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 367 continue; /* poll */ 368 369 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 370 continue; /* poll */ 371 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 372 373 pxa2x0_gpio_set_bit(GPIO_WS007SH_ADS7846_CS); 374 375 mutex_exit(&sc->sc_mtx); 376 377 return rv; 378 } 379 380 static uint32_t 381 wzero3ssp_read_max1233(struct wzero3ssp_softc *sc, uint32_t cmd, uint32_t data) 382 { 383 uint32_t rv; 384 385 mutex_enter(&sc->sc_mtx); 386 387 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 388 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 389 WS003SH_SSCR0_MAX1233); 390 391 pxa2x0_gpio_set_bit(39/*GPIO_WS003SH_XXX*/); 392 pxa2x0_gpio_clear_bit(GPIO_WS003SH_MAX1233_CS); 393 394 /* send cmd */ 395 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 396 continue; /* poll */ 397 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd); 398 while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 399 continue; /* poll */ 400 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 401 continue; /* poll */ 402 (void)bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 403 404 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 405 continue; /* poll */ 406 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, data); 407 while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 408 continue; /* poll */ 409 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 410 continue; /* poll */ 411 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 412 413 pxa2x0_gpio_set_bit(GPIO_WS003SH_MAX1233_CS); 414 415 mutex_exit(&sc->sc_mtx); 416 417 return rv; 418 } 419 420 static uint32_t 421 wzero3ssp_read_ak4184(struct wzero3ssp_softc *sc, uint32_t cmd) 422 { 423 uint32_t rv; 424 425 mutex_enter(&sc->sc_mtx); 426 427 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 0); 428 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSCR0, 429 WS011SH_SSCR0_AK4184_TP); 430 431 pxa2x0_gpio_clear_bit(GPIO_WS011SH_AK4184_CS); 432 433 (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 434 435 /* send cmd */ 436 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_TNF)) 437 continue; /* poll */ 438 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR, cmd << 16); 439 while (bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_BUSY) 440 continue; /* poll */ 441 442 while (!(bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSSR) & SSSR_RNE)) 443 continue; /* poll */ 444 rv = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SSP_SSDR); 445 446 pxa2x0_gpio_set_bit(GPIO_WS011SH_AK4184_CS); 447 448 mutex_exit(&sc->sc_mtx); 449 450 return rv; 451 } 452
Indexes created Tue Sep 23 14:10:03 GMT 2025