cpu.h revision 1.1
1 /* $NetBSD: cpu.h,v 1.1 2001/02/23 03:48:15 ichiro Exp $ */ 2 3 /* 4 * Copyright (c) 1994-1996 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpu.h 40 * 41 * CPU specific symbols 42 * 43 * Created : 18/09/94 44 * 45 * Based on kate/katelib/arm6.h 46 */ 47 48 #ifndef _ARM32_CPU_H_ 49 #define _ARM32_CPU_H_ 50 51 #if defined(_KERNEL) && !defined(_LKM) 52 #include "opt_cputypes.h" 53 #include "opt_lockdebug.h" 54 #endif 55 56 #ifndef _LOCORE 57 #include <machine/frame.h> 58 #endif /* !_LOCORE */ 59 #include <machine/psl.h> 60 61 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 62 63 /* 64 * ARM Process Status Register 65 * 66 * The picture in the ARM manuals looks like this: 67 * 3 3 2 2 2 68 * 1 0 9 8 7 8 7 6 5 4 0 69 * +-------+---------------------------------------+-+-+-+---------+ 70 * | flags | reserved |I|F| |M M M M M| 71 * |n z c v| | | | |4 3 2 1 0| 72 * +-------+---------------------------------------+-+-+-+---------+ 73 */ 74 75 #define PSR_FLAGS 0xf0000000 /* flags */ 76 #define PSR_N_bit (1 << 31) /* negative */ 77 #define PSR_Z_bit (1 << 30) /* zero */ 78 #define PSR_C_bit (1 << 29) /* carry */ 79 #define PSR_V_bit (1 << 28) /* overflow */ 80 81 #define I32_bit (1 << 7) /* IRQ disable */ 82 #define F32_bit (1 << 6) /* FIQ disable */ 83 84 #define PSR_MODE 0x0000001f /* mode mask */ 85 #define PSR_USR32_MODE 0x00000010 86 #define PSR_FIQ32_MODE 0x00000011 87 #define PSR_IRQ32_MODE 0x00000012 88 #define PSR_SVC32_MODE 0x00000013 89 #define PSR_ABT32_MODE 0x00000017 90 #define PSR_UND32_MODE 0x0000001b 91 #define PSR_32_MODE 0x00000010 92 93 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 94 #define PSR_IN_32_MODE(psr) ((psr) & PSR_32_MODE) 95 96 /* 97 * ARM Instructions 98 * 99 * 3 3 2 2 2 100 * 1 0 9 8 7 0 101 * +-------+-------------------------------------------------------+ 102 * | cond | instruction dependant | 103 * |c c c c| | 104 * +-------+-------------------------------------------------------+ 105 */ 106 107 #define INSN_SIZE 4 /* Always 4 bytes */ 108 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 109 #define INSN_COND_AL 0xe0000000 /* Always condition */ 110 111 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 112 113 #define CPU_ID_DESIGNER_MASK 0xff000000 114 #define CPU_ID_ARM_LTD 0x41000000 115 #define CPU_ID_DEC 0x44000000 116 #define CPU_ID_TYPE_MASK 0x00ff0000 117 #define CPU_ID_ARM 0x00560000 118 #define CPU_ID_CPU_MASK 0x0000fff0 119 #define ID_SA110 0x0000a100 120 #define ID_SA1100 0x0000a110 121 #define ID_SA1110 0x0000b110 122 #define CPU_ID_REVISION_MASK 0x0000000f 123 124 #define CPU_CONTROL_MMU_ENABLE 0x0001 125 #define CPU_CONTROL_AFLT_ENABLE 0x0002 126 #define CPU_CONTROL_DC_ENABLE 0x0004 127 #define CPU_CONTROL_WBUF_ENABLE 0x0008 128 #define CPU_CONTROL_32BP_ENABLE 0x0010 129 #define CPU_CONTROL_32BD_ENABLE 0x0020 130 #define CPU_CONTROL_LABT_ENABLE 0x0040 131 #define CPU_CONTROL_BEND_ENABLE 0x0080 132 #define CPU_CONTROL_SYST_ENABLE 0x0100 133 #define CPU_CONTROL_ROM_ENABLE 0x0200 134 #define CPU_CONTROL_CPCLK 0x0400 135 #define CPU_CONTROL_BPRD_ENABLE 0x0800 136 #define CPU_CONTROL_IC_ENABLE 0x1000 137 138 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 139 140 /* Fault status register definitions */ 141 142 #define FAULT_TYPE_MASK 0x0f 143 #define FAULT_USER 0x10 144 145 #define FAULT_WRTBUF_0 0x00 146 #define FAULT_WRTBUF_1 0x02 147 #define FAULT_BUSERR_0 0x04 148 #define FAULT_BUSERR_1 0x06 149 #define FAULT_BUSERR_2 0x08 150 #define FAULT_BUSERR_3 0x0a 151 #define FAULT_ALIGN_0 0x01 152 #define FAULT_ALIGN_1 0x03 153 #define FAULT_BUSTRNL1 0x0c 154 #define FAULT_BUSTRNL2 0x0e 155 #define FAULT_TRANS_S 0x05 156 #define FAULT_TRANS_P 0x07 157 #define FAULT_DOMAIN_S 0x09 158 #define FAULT_DOMAIN_P 0x0b 159 #define FAULT_PERM_S 0x0d 160 #define FAULT_PERM_P 0x0f 161 162 #ifdef _LOCORE 163 #define IRQdisable \ 164 stmfd sp!, {r0} ; \ 165 mrs r0, cpsr_all ; \ 166 orr r0, r0, #(I32_bit) ; \ 167 msr cpsr_all, r0 ; \ 168 ldmfd sp!, {r0} 169 170 #define IRQenable \ 171 stmfd sp!, {r0} ; \ 172 mrs r0, cpsr_all ; \ 173 bic r0, r0, #(I32_bit) ; \ 174 msr cpsr_all, r0 ; \ 175 ldmfd sp!, {r0} 176 177 #else 178 #define IRQdisable SetCPSR(I32_bit, I32_bit); 179 #define IRQenable SetCPSR(I32_bit, 0); 180 #endif /* _LOCORE */ 181 182 /* 183 * Return TRUE/FALSE (1/0) depending on whether the frame came from USR 184 * mode or not. 185 */ 186 187 #define CLKF_USERMODE(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) 188 189 /* 190 * This needs straighening, prob is the frame does not have info on the priority 191 * a guess that needs trying is (current_spl_level == SPL0) 192 */ 193 194 #define CLKF_BASEPRI(frame) ((frame->if_spsr & PSR_MODE) == PSR_USR32_MODE) 195 196 #define CLKF_PC(frame) (frame->if_pc) 197 198 /*#define CLKF_INTR(frame) (current_intr_depth > 1)*/ 199 200 /* Hack to treat FPE time as interrupt time so we can measure it */ 201 #define CLKF_INTR(frame) ((current_intr_depth > 1) || (frame->if_spsr & PSR_MODE) == PSR_UND32_MODE) 202 203 #define PROC_PC(p) ((p)->p_md.md_regs->tf_pc) 204 205 /* 206 * definitions of cpu-dependent requirements 207 * referenced in generic code 208 */ 209 210 #ifndef _LOCORE 211 #include <sys/sched.h> 212 struct cpu_info { 213 struct schedstate_percpu ci_schedstate; /* scheduler state */ 214 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 215 u_long ci_spin_locks; /* # of spin locks held */ 216 u_long ci_simple_locks; /* # of simple locks held */ 217 #endif 218 }; 219 #ifdef _KERNEL 220 extern struct cpu_info cpu_info_store; 221 #define curcpu() (&cpu_info_store) 222 #endif /* _KERNEL */ 223 #endif /* ! _LOCORE */ 224 225 #define cpu_wait(p) /* nothing */ 226 #define cpu_number() 0 227 228 /* 229 * Notify the current process (p) that it has a signal pending, 230 * process as soon as possible. 231 */ 232 233 #define signotify(p) setsoftast() 234 235 236 #if defined(_KERNEL) && !defined(_LOCORE) 237 extern int current_intr_depth; 238 239 /* 240 * Preempt the current process if in interrupt from user mode, 241 * or after the current trap/syscall if in system mode. 242 */ 243 int want_resched; /* resched() was called */ 244 #define need_resched(ci) (want_resched = 1, setsoftast()) 245 246 /* 247 * Give a profiling tick to the current process when the user profiling 248 * buffer pages are invalid. On the i386, request an ast to send us 249 * through trap(), marking the proc as needing a profiling tick. 250 */ 251 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) 252 253 /* locore.S */ 254 void atomic_set_bit __P((u_int *address, u_int setmask)); 255 void atomic_clear_bit __P((u_int *address, u_int clearmask)); 256 257 /* cpuswitch.S */ 258 struct pcb; 259 void savectx __P((struct pcb *pcb)); 260 261 /* ast.c */ 262 void userret __P((register struct proc *p)); 263 264 /* machdep.h */ 265 void bootsync __P((void)); 266 267 /* strstr.c */ 268 char *strstr __P((const char *s1, const char *s2)); 269 270 /* syscall.c */ 271 void child_return __P((void *)); 272 273 #endif /* _KERNEL && !_LOCORE */ 274 275 /* 276 * CTL_MACHDEP definitions. 277 */ 278 #define CPU_DEBUG 1 /* int: misc kernel debug control */ 279 #define CPU_BOOTED_DEVICE 2 /* string: device we booted from */ 280 #define CPU_BOOTED_KERNEL 3 /* string: kernel we booted */ 281 #define CPU_CONSDEV 4 /* struct: dev_t of our console */ 282 #define CPU_MAXID 5 /* number of valid machdep ids */ 283 284 #define CTL_MACHDEP_NAMES { \ 285 { 0, 0 }, \ 286 { "debug", CTLTYPE_INT }, \ 287 { "booted_device", CTLTYPE_STRING }, \ 288 { "booted_kernel", CTLTYPE_STRING }, \ 289 { "console_device", CTLTYPE_STRUCT }, \ 290 } 291 292 #endif /* !_ARM32_CPU_H_ */ 293 294 /* End of cpu.h */ 295
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