it8368.c revision 1.10.4.2
1 1.10.4.2 nathanw /* $NetBSD: it8368.c,v 1.10.4.2 2002/01/08 00:24:59 nathanw Exp $ */ 2 1.10.4.2 nathanw 3 1.10.4.2 nathanw /*- 4 1.10.4.2 nathanw * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 1.10.4.2 nathanw * All rights reserved. 6 1.10.4.2 nathanw * 7 1.10.4.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.10.4.2 nathanw * by UCHIYAMA Yasushi. 9 1.10.4.2 nathanw * 10 1.10.4.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.10.4.2 nathanw * modification, are permitted provided that the following conditions 12 1.10.4.2 nathanw * are met: 13 1.10.4.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.10.4.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.10.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.10.4.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.10.4.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.10.4.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.10.4.2 nathanw * must display the following acknowledgement: 20 1.10.4.2 nathanw * This product includes software developed by the NetBSD 21 1.10.4.2 nathanw * Foundation, Inc. and its contributors. 22 1.10.4.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.10.4.2 nathanw * contributors may be used to endorse or promote products derived 24 1.10.4.2 nathanw * from this software without specific prior written permission. 25 1.10.4.2 nathanw * 26 1.10.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.10.4.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.10.4.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.10.4.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.10.4.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.10.4.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.10.4.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.10.4.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.10.4.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.10.4.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.10.4.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.10.4.2 nathanw */ 38 1.10.4.2 nathanw 39 1.10.4.2 nathanw #undef WINCE_DEFAULT_SETTING /* for debug */ 40 1.10.4.2 nathanw #undef IT8368DEBUG 41 1.10.4.2 nathanw #include "opt_tx39_debug.h" 42 1.10.4.2 nathanw 43 1.10.4.2 nathanw #include <sys/param.h> 44 1.10.4.2 nathanw #include <sys/systm.h> 45 1.10.4.2 nathanw #include <sys/device.h> 46 1.10.4.2 nathanw 47 1.10.4.2 nathanw #include <machine/bus.h> 48 1.10.4.2 nathanw 49 1.10.4.2 nathanw #include <dev/pcmcia/pcmciareg.h> 50 1.10.4.2 nathanw #include <dev/pcmcia/pcmciavar.h> 51 1.10.4.2 nathanw #include <dev/pcmcia/pcmciachip.h> 52 1.10.4.2 nathanw 53 1.10.4.2 nathanw #include <hpcmips/tx/tx39var.h> 54 1.10.4.2 nathanw #include <hpcmips/tx/txcsbusvar.h> 55 1.10.4.2 nathanw #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 56 1.10.4.2 nathanw #include <hpcmips/dev/it8368var.h> 57 1.10.4.2 nathanw #include <hpcmips/dev/it8368reg.h> 58 1.10.4.2 nathanw 59 1.10.4.2 nathanw #ifdef IT8368DEBUG 60 1.10.4.2 nathanw int it8368debug = 1; 61 1.10.4.2 nathanw #define DPRINTF(arg) if (it8368debug) printf arg; 62 1.10.4.2 nathanw #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 63 1.10.4.2 nathanw #else 64 1.10.4.2 nathanw #define DPRINTF(arg) 65 1.10.4.2 nathanw #define DPRINTFN(n, arg) 66 1.10.4.2 nathanw #endif 67 1.10.4.2 nathanw 68 1.10.4.2 nathanw int it8368e_match(struct device *, struct cfdata *, void *); 69 1.10.4.2 nathanw void it8368e_attach(struct device *, struct device *, void *); 70 1.10.4.2 nathanw int it8368_print(void *, const char *); 71 1.10.4.2 nathanw int it8368_submatch(struct device *, struct cfdata *, void *); 72 1.10.4.2 nathanw 73 1.10.4.2 nathanw #define IT8368_LASTSTATE_PRESENT 0x0002 74 1.10.4.2 nathanw #define IT8368_LASTSTATE_HALF 0x0001 75 1.10.4.2 nathanw #define IT8368_LASTSTATE_EMPTY 0x0000 76 1.10.4.2 nathanw 77 1.10.4.2 nathanw struct it8368e_softc { 78 1.10.4.2 nathanw struct device sc_dev; 79 1.10.4.2 nathanw struct device *sc_pcmcia; 80 1.10.4.2 nathanw tx_chipset_tag_t sc_tc; 81 1.10.4.2 nathanw 82 1.10.4.2 nathanw /* Register space */ 83 1.10.4.2 nathanw bus_space_tag_t sc_csregt; 84 1.10.4.2 nathanw bus_space_handle_t sc_csregh; 85 1.10.4.2 nathanw /* I/O, attribute space */ 86 1.10.4.2 nathanw bus_space_tag_t sc_csiot; 87 1.10.4.2 nathanw bus_addr_t sc_csiobase; 88 1.10.4.2 nathanw bus_size_t sc_csiosize; 89 1.10.4.2 nathanw /* 90 1.10.4.2 nathanw * XXX theses means attribute memory. not memory space. 91 1.10.4.2 nathanw * memory space is 0x64000000. 92 1.10.4.2 nathanw */ 93 1.10.4.2 nathanw bus_space_tag_t sc_csmemt; 94 1.10.4.2 nathanw bus_addr_t sc_csmembase; 95 1.10.4.2 nathanw bus_size_t sc_csmemsize; 96 1.10.4.2 nathanw 97 1.10.4.2 nathanw /* Separate I/O and attribute space mode */ 98 1.10.4.2 nathanw int sc_fixattr; 99 1.10.4.2 nathanw 100 1.10.4.2 nathanw /* Card interrupt handler */ 101 1.10.4.2 nathanw int (*sc_card_fun)(void *); 102 1.10.4.2 nathanw void *sc_card_arg; 103 1.10.4.2 nathanw void *sc_card_ih; 104 1.10.4.2 nathanw int sc_card_irq; 105 1.10.4.2 nathanw 106 1.10.4.2 nathanw /* Card status change */ 107 1.10.4.2 nathanw int sc_irq; 108 1.10.4.2 nathanw void *sc_ih; 109 1.10.4.2 nathanw int sc_laststate; 110 1.10.4.2 nathanw }; 111 1.10.4.2 nathanw 112 1.10.4.2 nathanw void it8368_init_socket(struct it8368e_softc*); 113 1.10.4.2 nathanw void it8368_attach_socket(struct it8368e_softc *); 114 1.10.4.2 nathanw int it8368_intr(void *); 115 1.10.4.2 nathanw int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 116 1.10.4.2 nathanw struct pcmcia_mem_handle *); 117 1.10.4.2 nathanw void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 118 1.10.4.2 nathanw int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 119 1.10.4.2 nathanw struct pcmcia_mem_handle *, bus_addr_t *, int *); 120 1.10.4.2 nathanw void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 121 1.10.4.2 nathanw int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 122 1.10.4.2 nathanw bus_size_t, struct pcmcia_io_handle *); 123 1.10.4.2 nathanw void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 124 1.10.4.2 nathanw int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 125 1.10.4.2 nathanw struct pcmcia_io_handle *, int *); 126 1.10.4.2 nathanw void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 127 1.10.4.2 nathanw void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 128 1.10.4.2 nathanw void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 129 1.10.4.2 nathanw void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 130 1.10.4.2 nathanw struct pcmcia_function *, int, int (*) (void *), void *); 131 1.10.4.2 nathanw void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 132 1.10.4.2 nathanw 133 1.10.4.2 nathanw #ifdef IT8368DEBUG 134 1.10.4.2 nathanw void it8368_dump(struct it8368e_softc *); 135 1.10.4.2 nathanw #endif 136 1.10.4.2 nathanw 137 1.10.4.2 nathanw static struct pcmcia_chip_functions it8368_functions = { 138 1.10.4.2 nathanw it8368_chip_mem_alloc, 139 1.10.4.2 nathanw it8368_chip_mem_free, 140 1.10.4.2 nathanw it8368_chip_mem_map, 141 1.10.4.2 nathanw it8368_chip_mem_unmap, 142 1.10.4.2 nathanw it8368_chip_io_alloc, 143 1.10.4.2 nathanw it8368_chip_io_free, 144 1.10.4.2 nathanw it8368_chip_io_map, 145 1.10.4.2 nathanw it8368_chip_io_unmap, 146 1.10.4.2 nathanw it8368_chip_intr_establish, 147 1.10.4.2 nathanw it8368_chip_intr_disestablish, 148 1.10.4.2 nathanw it8368_chip_socket_enable, 149 1.10.4.2 nathanw it8368_chip_socket_disable 150 1.10.4.2 nathanw }; 151 1.10.4.2 nathanw 152 1.10.4.2 nathanw struct cfattach it8368e_ca = { 153 1.10.4.2 nathanw sizeof(struct it8368e_softc), it8368e_match, it8368e_attach 154 1.10.4.2 nathanw }; 155 1.10.4.2 nathanw 156 1.10.4.2 nathanw /* 157 1.10.4.2 nathanw * IT8368 configuration register is big-endian. 158 1.10.4.2 nathanw */ 159 1.10.4.2 nathanw static __inline__ u_int16_t it8368_reg_read(bus_space_tag_t, 160 1.10.4.2 nathanw bus_space_handle_t, int); 161 1.10.4.2 nathanw static __inline__ void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 162 1.10.4.2 nathanw int, u_int16_t); 163 1.10.4.2 nathanw 164 1.10.4.2 nathanw #ifdef IT8368E_DESTRUCTIVE_CHECK 165 1.10.4.2 nathanw int it8368e_id_check(void *); 166 1.10.4.2 nathanw 167 1.10.4.2 nathanw /* 168 1.10.4.2 nathanw * IT8368E don't have identification method. this is destructive check. 169 1.10.4.2 nathanw */ 170 1.10.4.2 nathanw int 171 1.10.4.2 nathanw it8368e_id_check(void *aux) 172 1.10.4.2 nathanw { 173 1.10.4.2 nathanw struct cs_attach_args *ca = aux; 174 1.10.4.2 nathanw tx_chipset_tag_t tc; 175 1.10.4.2 nathanw bus_space_tag_t csregt; 176 1.10.4.2 nathanw bus_space_handle_t csregh; 177 1.10.4.2 nathanw u_int16_t oreg, reg; 178 1.10.4.2 nathanw int match = 0; 179 1.10.4.2 nathanw 180 1.10.4.2 nathanw tc = ca->ca_tc; 181 1.10.4.2 nathanw csregt = ca->ca_csreg.cstag; 182 1.10.4.2 nathanw 183 1.10.4.2 nathanw bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 184 1.10.4.2 nathanw 0, &csregh); 185 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 186 1.10.4.2 nathanw oreg = reg; 187 1.10.4.2 nathanw bitdisp(reg); 188 1.10.4.2 nathanw 189 1.10.4.2 nathanw reg &= ~IT8368_CTRL_BYTESWAP; 190 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 191 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 192 1.10.4.2 nathanw if (reg & IT8368_CTRL_BYTESWAP) 193 1.10.4.2 nathanw goto nomatch; 194 1.10.4.2 nathanw 195 1.10.4.2 nathanw reg |= IT8368_CTRL_BYTESWAP; 196 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 197 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 198 1.10.4.2 nathanw if (!(reg & IT8368_CTRL_BYTESWAP)) 199 1.10.4.2 nathanw goto nomatch; 200 1.10.4.2 nathanw 201 1.10.4.2 nathanw match = 1; 202 1.10.4.2 nathanw nomatch: 203 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 204 1.10.4.2 nathanw bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 205 1.10.4.2 nathanw 206 1.10.4.2 nathanw return (match); 207 1.10.4.2 nathanw } 208 1.10.4.2 nathanw #endif /* IT8368E_DESTRUCTIVE_CHECK */ 209 1.10.4.2 nathanw 210 1.10.4.2 nathanw int 211 1.10.4.2 nathanw it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 212 1.10.4.2 nathanw { 213 1.10.4.2 nathanw #ifdef IT8368E_DESTRUCTIVE_CHECK 214 1.10.4.2 nathanw return (it8368e_id_check(aux)); 215 1.10.4.2 nathanw #else 216 1.10.4.2 nathanw return (1); 217 1.10.4.2 nathanw #endif 218 1.10.4.2 nathanw } 219 1.10.4.2 nathanw 220 1.10.4.2 nathanw void 221 1.10.4.2 nathanw it8368e_attach(struct device *parent, struct device *self, void *aux) 222 1.10.4.2 nathanw { 223 1.10.4.2 nathanw struct cs_attach_args *ca = aux; 224 1.10.4.2 nathanw struct it8368e_softc *sc = (void*)self; 225 1.10.4.2 nathanw tx_chipset_tag_t tc; 226 1.10.4.2 nathanw bus_space_tag_t csregt; 227 1.10.4.2 nathanw bus_space_handle_t csregh; 228 1.10.4.2 nathanw u_int16_t reg; 229 1.10.4.2 nathanw 230 1.10.4.2 nathanw sc->sc_tc = tc = ca->ca_tc; 231 1.10.4.2 nathanw sc->sc_csregt = csregt = ca->ca_csreg.cstag; 232 1.10.4.2 nathanw 233 1.10.4.2 nathanw bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 234 1.10.4.2 nathanw 0, &sc->sc_csregh); 235 1.10.4.2 nathanw csregh = sc->sc_csregh; 236 1.10.4.2 nathanw sc->sc_csiot = ca->ca_csio.cstag; 237 1.10.4.2 nathanw sc->sc_csiobase = ca->ca_csio.csbase; 238 1.10.4.2 nathanw sc->sc_csiosize = ca->ca_csio.cssize; 239 1.10.4.2 nathanw 240 1.10.4.2 nathanw #ifdef IT8368DEBUG 241 1.10.4.2 nathanw printf("\n\t[Windows CE setting]\n"); 242 1.10.4.2 nathanw it8368_dump(sc); /* print WindowsCE setting */ 243 1.10.4.2 nathanw #endif 244 1.10.4.2 nathanw /* LHA[14:13] <= HA[14:13] */ 245 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 246 1.10.4.2 nathanw reg &= ~IT8368_CTRL_ADDRSEL; 247 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 248 1.10.4.2 nathanw 249 1.10.4.2 nathanw /* Set all MFIO direction as LHA[23:13] output pins */ 250 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 251 1.10.4.2 nathanw reg |= IT8368_MFIODIR_MASK; 252 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 253 1.10.4.2 nathanw 254 1.10.4.2 nathanw /* Set all MFIO functions as LHA */ 255 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 256 1.10.4.2 nathanw reg &= ~IT8368_MFIOSEL_MASK; 257 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 258 1.10.4.2 nathanw 259 1.10.4.2 nathanw /* Disable MFIO interrupt */ 260 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 261 1.10.4.2 nathanw reg &= ~IT8368_MFIOPOSINTEN_MASK; 262 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 263 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 264 1.10.4.2 nathanw reg &= ~IT8368_MFIONEGINTEN_MASK; 265 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 266 1.10.4.2 nathanw 267 1.10.4.2 nathanw /* Port direction */ 268 1.10.4.2 nathanw reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 269 1.10.4.2 nathanw IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 270 1.10.4.2 nathanw IT8368_PIN_BCRDRST; 271 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 272 1.10.4.2 nathanw printf("\n"); 273 1.10.4.2 nathanw 274 1.10.4.2 nathanw /* 275 1.10.4.2 nathanw * Separate I/O and attribute memory region 276 1.10.4.2 nathanw */ 277 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 278 1.10.4.2 nathanw 279 1.10.4.2 nathanw reg |= IT8368_CTRL_FIXATTRIO; 280 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 281 1.10.4.2 nathanw 282 1.10.4.2 nathanw if (IT8368_CTRL_FIXATTRIO & 283 1.10.4.2 nathanw it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 284 1.10.4.2 nathanw sc->sc_fixattr = 1; 285 1.10.4.2 nathanw printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 286 1.10.4.2 nathanw } else { 287 1.10.4.2 nathanw sc->sc_fixattr = 0; 288 1.10.4.2 nathanw printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 289 1.10.4.2 nathanw } 290 1.10.4.2 nathanw 291 1.10.4.2 nathanw sc->sc_csmemt = sc->sc_csiot; 292 1.10.4.2 nathanw sc->sc_csiosize /= 2; 293 1.10.4.2 nathanw sc->sc_csmemsize = sc->sc_csiosize; 294 1.10.4.2 nathanw sc->sc_csmembase = sc->sc_csiosize; 295 1.10.4.2 nathanw 296 1.10.4.2 nathanw #ifdef IT8368DEBUG 297 1.10.4.2 nathanw it8368_dump(sc); 298 1.10.4.2 nathanw #endif 299 1.10.4.2 nathanw /* Enable card and interrupt driving. */ 300 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 301 1.10.4.2 nathanw reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 302 1.10.4.2 nathanw if (sc->sc_fixattr) 303 1.10.4.2 nathanw reg |= IT8368_CTRL_FIXATTRIO; 304 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 305 1.10.4.2 nathanw 306 1.10.4.2 nathanw sc->sc_irq = ca->ca_irq1; 307 1.10.4.2 nathanw sc->sc_card_irq = ca->ca_irq3; 308 1.10.4.2 nathanw 309 1.10.4.2 nathanw it8368_attach_socket(sc); 310 1.10.4.2 nathanw } 311 1.10.4.2 nathanw 312 1.10.4.2 nathanw __inline__ u_int16_t 313 1.10.4.2 nathanw it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 314 1.10.4.2 nathanw { 315 1.10.4.2 nathanw u_int16_t val; 316 1.10.4.2 nathanw 317 1.10.4.2 nathanw val = bus_space_read_2(t, h, ofs); 318 1.10.4.2 nathanw return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 319 1.10.4.2 nathanw } 320 1.10.4.2 nathanw 321 1.10.4.2 nathanw __inline__ void 322 1.10.4.2 nathanw it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 323 1.10.4.2 nathanw { 324 1.10.4.2 nathanw u_int16_t val; 325 1.10.4.2 nathanw 326 1.10.4.2 nathanw val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 327 1.10.4.2 nathanw bus_space_write_2(t, h, ofs, val); 328 1.10.4.2 nathanw } 329 1.10.4.2 nathanw 330 1.10.4.2 nathanw int 331 1.10.4.2 nathanw it8368_intr(void *arg) 332 1.10.4.2 nathanw { 333 1.10.4.2 nathanw struct it8368e_softc *sc = arg; 334 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 335 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 336 1.10.4.2 nathanw u_int16_t reg; 337 1.10.4.2 nathanw 338 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 339 1.10.4.2 nathanw 340 1.10.4.2 nathanw if (reg & IT8368_PIN_BCRDRDY) { 341 1.10.4.2 nathanw if (sc->sc_card_fun) { 342 1.10.4.2 nathanw /* clear interrupt */ 343 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, 344 1.10.4.2 nathanw IT8368_GPIONEGINTSTAT_REG, 345 1.10.4.2 nathanw IT8368_PIN_BCRDRDY); 346 1.10.4.2 nathanw 347 1.10.4.2 nathanw /* Dispatch card interrupt handler */ 348 1.10.4.2 nathanw (*sc->sc_card_fun)(sc->sc_card_arg); 349 1.10.4.2 nathanw } 350 1.10.4.2 nathanw } else if (reg & IT8368_PIN_CRDDET2) { 351 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 352 1.10.4.2 nathanw IT8368_PIN_CRDDET2); 353 1.10.4.2 nathanw printf("[CSC]\n"); 354 1.10.4.2 nathanw #ifdef IT8368DEBUG 355 1.10.4.2 nathanw it8368_dump(sc); 356 1.10.4.2 nathanw #endif 357 1.10.4.2 nathanw it8368_chip_socket_disable(sc); 358 1.10.4.2 nathanw } else { 359 1.10.4.2 nathanw #ifdef IT8368DEBUG 360 1.10.4.2 nathanw u_int16_t reg2; 361 1.10.4.2 nathanw reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 362 1.10.4.2 nathanw printf("unknown it8368 interrupt: "); 363 1.10.4.2 nathanw bitdisp(reg2); 364 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 365 1.10.4.2 nathanw reg); 366 1.10.4.2 nathanw #endif 367 1.10.4.2 nathanw } 368 1.10.4.2 nathanw 369 1.10.4.2 nathanw return (0); 370 1.10.4.2 nathanw } 371 1.10.4.2 nathanw 372 1.10.4.2 nathanw int 373 1.10.4.2 nathanw it8368_print(void *arg, const char *pnp) 374 1.10.4.2 nathanw { 375 1.10.4.2 nathanw if (pnp) 376 1.10.4.2 nathanw printf("pcmcia at %s", pnp); 377 1.10.4.2 nathanw 378 1.10.4.2 nathanw return (UNCONF); 379 1.10.4.2 nathanw } 380 1.10.4.2 nathanw 381 1.10.4.2 nathanw int 382 1.10.4.2 nathanw it8368_submatch(struct device *parent, struct cfdata *cf, void *aux) 383 1.10.4.2 nathanw { 384 1.10.4.2 nathanw 385 1.10.4.2 nathanw return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 386 1.10.4.2 nathanw } 387 1.10.4.2 nathanw 388 1.10.4.2 nathanw void 389 1.10.4.2 nathanw it8368_attach_socket(struct it8368e_softc *sc) 390 1.10.4.2 nathanw { 391 1.10.4.2 nathanw struct pcmciabus_attach_args paa; 392 1.10.4.2 nathanw 393 1.10.4.2 nathanw paa.paa_busname = "pcmcia"; 394 1.10.4.2 nathanw paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 395 1.10.4.2 nathanw paa.pch = (pcmcia_chipset_handle_t)sc; 396 1.10.4.2 nathanw paa.iobase = 0; 397 1.10.4.2 nathanw paa.iosize = sc->sc_csiosize; 398 1.10.4.2 nathanw 399 1.10.4.2 nathanw if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 400 1.10.4.2 nathanw it8368_submatch))) { 401 1.10.4.2 nathanw 402 1.10.4.2 nathanw it8368_init_socket(sc); 403 1.10.4.2 nathanw } 404 1.10.4.2 nathanw } 405 1.10.4.2 nathanw 406 1.10.4.2 nathanw void 407 1.10.4.2 nathanw it8368_init_socket(struct it8368e_softc *sc) 408 1.10.4.2 nathanw { 409 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 410 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 411 1.10.4.2 nathanw u_int16_t reg; 412 1.10.4.2 nathanw 413 1.10.4.2 nathanw /* 414 1.10.4.2 nathanw * set up the card to interrupt on card detect 415 1.10.4.2 nathanw */ 416 1.10.4.2 nathanw reg = IT8368_PIN_CRDDET2; /* CSC */ 417 1.10.4.2 nathanw /* enable negative edge */ 418 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 419 1.10.4.2 nathanw /* disable positive edge */ 420 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 421 1.10.4.2 nathanw 422 1.10.4.2 nathanw sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 423 1.10.4.2 nathanw IST_EDGE, IPL_BIO, it8368_intr, sc); 424 1.10.4.2 nathanw if (sc->sc_ih == NULL) { 425 1.10.4.2 nathanw printf("%s: can't establish interrupt\n", 426 1.10.4.2 nathanw sc->sc_dev.dv_xname); 427 1.10.4.2 nathanw return; 428 1.10.4.2 nathanw } 429 1.10.4.2 nathanw 430 1.10.4.2 nathanw /* 431 1.10.4.2 nathanw * if there's a card there, then attach it. 432 1.10.4.2 nathanw */ 433 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 434 1.10.4.2 nathanw 435 1.10.4.2 nathanw if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 436 1.10.4.2 nathanw sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 437 1.10.4.2 nathanw } else { 438 1.10.4.2 nathanw pcmcia_card_attach(sc->sc_pcmcia); 439 1.10.4.2 nathanw sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 440 1.10.4.2 nathanw } 441 1.10.4.2 nathanw } 442 1.10.4.2 nathanw 443 1.10.4.2 nathanw void * 444 1.10.4.2 nathanw it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 445 1.10.4.2 nathanw struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 446 1.10.4.2 nathanw { 447 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 448 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 449 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 450 1.10.4.2 nathanw u_int16_t reg; 451 1.10.4.2 nathanw 452 1.10.4.2 nathanw if (sc->sc_card_fun) 453 1.10.4.2 nathanw panic("it8368_chip_intr_establish: " 454 1.10.4.2 nathanw "duplicate card interrupt handler."); 455 1.10.4.2 nathanw 456 1.10.4.2 nathanw sc->sc_card_fun = ih_fun; 457 1.10.4.2 nathanw sc->sc_card_arg = ih_arg; 458 1.10.4.2 nathanw 459 1.10.4.2 nathanw sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 460 1.10.4.2 nathanw IST_EDGE, IPL_BIO, it8368_intr, 461 1.10.4.2 nathanw sc); 462 1.10.4.2 nathanw 463 1.10.4.2 nathanw /* enable card interrupt */ 464 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 465 1.10.4.2 nathanw reg |= IT8368_PIN_BCRDRDY; 466 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 467 1.10.4.2 nathanw 468 1.10.4.2 nathanw return (sc->sc_card_ih); 469 1.10.4.2 nathanw } 470 1.10.4.2 nathanw 471 1.10.4.2 nathanw void 472 1.10.4.2 nathanw it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 473 1.10.4.2 nathanw { 474 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 475 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 476 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 477 1.10.4.2 nathanw u_int16_t reg; 478 1.10.4.2 nathanw 479 1.10.4.2 nathanw if (!sc->sc_card_fun) 480 1.10.4.2 nathanw panic("it8368_chip_intr_disestablish:" 481 1.10.4.2 nathanw "no handler established."); 482 1.10.4.2 nathanw assert(ih == sc->sc_card_ih); 483 1.10.4.2 nathanw 484 1.10.4.2 nathanw sc->sc_card_fun = 0; 485 1.10.4.2 nathanw sc->sc_card_arg = 0; 486 1.10.4.2 nathanw 487 1.10.4.2 nathanw /* disable card interrupt */ 488 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 489 1.10.4.2 nathanw reg &= ~IT8368_PIN_BCRDRDY; 490 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 491 1.10.4.2 nathanw 492 1.10.4.2 nathanw tx_intr_disestablish(sc->sc_tc, ih); 493 1.10.4.2 nathanw } 494 1.10.4.2 nathanw 495 1.10.4.2 nathanw int 496 1.10.4.2 nathanw it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 497 1.10.4.2 nathanw struct pcmcia_mem_handle *pcmhp) 498 1.10.4.2 nathanw { 499 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 500 1.10.4.2 nathanw 501 1.10.4.2 nathanw if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 502 1.10.4.2 nathanw sc->sc_csmembase + sc->sc_csmemsize, size, 503 1.10.4.2 nathanw size, 0, 0, 0, &pcmhp->memh)) { 504 1.10.4.2 nathanw DPRINTF(("it8368_chip_mem_alloc: failed\n")); 505 1.10.4.2 nathanw return (1); 506 1.10.4.2 nathanw } 507 1.10.4.2 nathanw 508 1.10.4.2 nathanw if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 509 1.10.4.2 nathanw pcmhp->memh -= sc->sc_csmembase; 510 1.10.4.2 nathanw 511 1.10.4.2 nathanw pcmhp->memt = sc->sc_csmemt; 512 1.10.4.2 nathanw pcmhp->addr = pcmhp->memh; 513 1.10.4.2 nathanw pcmhp->size = size; 514 1.10.4.2 nathanw pcmhp->realsize = size; 515 1.10.4.2 nathanw 516 1.10.4.2 nathanw DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 517 1.10.4.2 nathanw (unsigned)pcmhp->memh, (unsigned)size)); 518 1.10.4.2 nathanw 519 1.10.4.2 nathanw return (0); 520 1.10.4.2 nathanw } 521 1.10.4.2 nathanw 522 1.10.4.2 nathanw void 523 1.10.4.2 nathanw it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 524 1.10.4.2 nathanw struct pcmcia_mem_handle *pcmhp) 525 1.10.4.2 nathanw { 526 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 527 1.10.4.2 nathanw 528 1.10.4.2 nathanw DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 529 1.10.4.2 nathanw (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 530 1.10.4.2 nathanw 531 1.10.4.2 nathanw if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 532 1.10.4.2 nathanw pcmhp->memh += sc->sc_csmembase; 533 1.10.4.2 nathanw 534 1.10.4.2 nathanw bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 535 1.10.4.2 nathanw } 536 1.10.4.2 nathanw 537 1.10.4.2 nathanw int 538 1.10.4.2 nathanw it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 539 1.10.4.2 nathanw bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 540 1.10.4.2 nathanw bus_size_t *offsetp, int *windowp) 541 1.10.4.2 nathanw { 542 1.10.4.2 nathanw /* attribute mode */ 543 1.10.4.2 nathanw it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 544 1.10.4.2 nathanw 545 1.10.4.2 nathanw *offsetp = card_addr; 546 1.10.4.2 nathanw DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 547 1.10.4.2 nathanw (unsigned)pcmhp->memh, (unsigned)size)); 548 1.10.4.2 nathanw 549 1.10.4.2 nathanw return (0); 550 1.10.4.2 nathanw } 551 1.10.4.2 nathanw 552 1.10.4.2 nathanw void 553 1.10.4.2 nathanw it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 554 1.10.4.2 nathanw { 555 1.10.4.2 nathanw /* return to I/O mode */ 556 1.10.4.2 nathanw it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 557 1.10.4.2 nathanw } 558 1.10.4.2 nathanw 559 1.10.4.2 nathanw void 560 1.10.4.2 nathanw it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 561 1.10.4.2 nathanw { 562 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 563 1.10.4.2 nathanw txreg_t reg32; 564 1.10.4.2 nathanw 565 1.10.4.2 nathanw DPRINTF(("it8368_mode: change access space to ")); 566 1.10.4.2 nathanw DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 567 1.10.4.2 nathanw width == IT8368_WIDTH_8 ? 8 : 16)); 568 1.10.4.2 nathanw 569 1.10.4.2 nathanw reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 570 1.10.4.2 nathanw 571 1.10.4.2 nathanw if (io) { 572 1.10.4.2 nathanw if (width == IT8368_WIDTH_8) 573 1.10.4.2 nathanw reg32 |= TX39_MEMCONFIG3_PORT8SEL; 574 1.10.4.2 nathanw else 575 1.10.4.2 nathanw reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 576 1.10.4.2 nathanw } 577 1.10.4.2 nathanw 578 1.10.4.2 nathanw if (!sc->sc_fixattr) { 579 1.10.4.2 nathanw if (io) 580 1.10.4.2 nathanw reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 581 1.10.4.2 nathanw else 582 1.10.4.2 nathanw reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 583 1.10.4.2 nathanw } 584 1.10.4.2 nathanw tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 585 1.10.4.2 nathanw 586 1.10.4.2 nathanw #ifdef IT8368DEBUG 587 1.10.4.2 nathanw if (sc->sc_fixattr) 588 1.10.4.2 nathanw return; /* No need to report BIU status */ 589 1.10.4.2 nathanw 590 1.10.4.2 nathanw /* check BIU status */ 591 1.10.4.2 nathanw reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 592 1.10.4.2 nathanw if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 593 1.10.4.2 nathanw DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 594 1.10.4.2 nathanw reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 595 1.10.4.2 nathanw } else { 596 1.10.4.2 nathanw DPRINTF(("it8368_mode: atttribute space enabled\n")); 597 1.10.4.2 nathanw } 598 1.10.4.2 nathanw #endif /* IT8368DEBUG */ 599 1.10.4.2 nathanw } 600 1.10.4.2 nathanw 601 1.10.4.2 nathanw int 602 1.10.4.2 nathanw it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 603 1.10.4.2 nathanw bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 604 1.10.4.2 nathanw { 605 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 606 1.10.4.2 nathanw 607 1.10.4.2 nathanw if (start) { 608 1.10.4.2 nathanw if (bus_space_map(sc->sc_csiot, start, size, 0, 609 1.10.4.2 nathanw &pcihp->ioh)) { 610 1.10.4.2 nathanw return (1); 611 1.10.4.2 nathanw } 612 1.10.4.2 nathanw DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 613 1.10.4.2 nathanw (unsigned)start, (unsigned)size)); 614 1.10.4.2 nathanw } else { 615 1.10.4.2 nathanw if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 616 1.10.4.2 nathanw sc->sc_csiobase + sc->sc_csiosize, 617 1.10.4.2 nathanw size, align, 0, 0, &pcihp->addr, 618 1.10.4.2 nathanw &pcihp->ioh)) { 619 1.10.4.2 nathanw 620 1.10.4.2 nathanw return (1); 621 1.10.4.2 nathanw } 622 1.10.4.2 nathanw pcihp->flags = PCMCIA_IO_ALLOCATED; 623 1.10.4.2 nathanw DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 624 1.10.4.2 nathanw (unsigned)size, (unsigned)pcihp->addr)); 625 1.10.4.2 nathanw } 626 1.10.4.2 nathanw 627 1.10.4.2 nathanw pcihp->iot = sc->sc_csiot; 628 1.10.4.2 nathanw pcihp->size = size; 629 1.10.4.2 nathanw 630 1.10.4.2 nathanw return (0); 631 1.10.4.2 nathanw } 632 1.10.4.2 nathanw 633 1.10.4.2 nathanw int 634 1.10.4.2 nathanw it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 635 1.10.4.2 nathanw bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 636 1.10.4.2 nathanw { 637 1.10.4.2 nathanw /* I/O mode */ 638 1.10.4.2 nathanw it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 639 1.10.4.2 nathanw 640 1.10.4.2 nathanw DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 641 1.10.4.2 nathanw (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 642 1.10.4.2 nathanw 643 1.10.4.2 nathanw return (0); 644 1.10.4.2 nathanw } 645 1.10.4.2 nathanw 646 1.10.4.2 nathanw void 647 1.10.4.2 nathanw it8368_chip_io_free(pcmcia_chipset_handle_t pch, 648 1.10.4.2 nathanw struct pcmcia_io_handle *pcihp) 649 1.10.4.2 nathanw { 650 1.10.4.2 nathanw if (pcihp->flags & PCMCIA_IO_ALLOCATED) 651 1.10.4.2 nathanw bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 652 1.10.4.2 nathanw else 653 1.10.4.2 nathanw bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 654 1.10.4.2 nathanw 655 1.10.4.2 nathanw DPRINTF(("it8368_chip_io_free %#x+%#x\n", 656 1.10.4.2 nathanw (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 657 1.10.4.2 nathanw } 658 1.10.4.2 nathanw 659 1.10.4.2 nathanw void 660 1.10.4.2 nathanw it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 661 1.10.4.2 nathanw { 662 1.10.4.2 nathanw 663 1.10.4.2 nathanw } 664 1.10.4.2 nathanw 665 1.10.4.2 nathanw void 666 1.10.4.2 nathanw it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 667 1.10.4.2 nathanw { 668 1.10.4.2 nathanw #ifndef WINCE_DEFAULT_SETTING 669 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*)pch; 670 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 671 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 672 1.10.4.2 nathanw volatile u_int16_t reg; 673 1.10.4.2 nathanw 674 1.10.4.2 nathanw /* Power off */ 675 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 676 1.10.4.2 nathanw reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 677 1.10.4.2 nathanw reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 678 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 679 1.10.4.2 nathanw delay(20000); 680 1.10.4.2 nathanw 681 1.10.4.2 nathanw /* 682 1.10.4.2 nathanw * wait 300ms until power fails (Tpf). Then, wait 100ms since 683 1.10.4.2 nathanw * we are changing Vcc (Toff). 684 1.10.4.2 nathanw */ 685 1.10.4.2 nathanw delay((300 + 100) * 1000); 686 1.10.4.2 nathanw 687 1.10.4.2 nathanw /* Supply Vcc */ 688 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 689 1.10.4.2 nathanw reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 690 1.10.4.2 nathanw reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 691 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 692 1.10.4.2 nathanw 693 1.10.4.2 nathanw /* 694 1.10.4.2 nathanw * wait 100ms until power raise (Tpr) and 20ms to become 695 1.10.4.2 nathanw * stable (Tsu(Vcc)). 696 1.10.4.2 nathanw * 697 1.10.4.2 nathanw * some machines require some more time to be settled 698 1.10.4.2 nathanw * (300ms is added here). 699 1.10.4.2 nathanw */ 700 1.10.4.2 nathanw delay((100 + 20 + 300) * 1000); 701 1.10.4.2 nathanw 702 1.10.4.2 nathanw /* Assert reset signal */ 703 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 704 1.10.4.2 nathanw reg |= IT8368_PIN_BCRDRST; 705 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 706 1.10.4.2 nathanw 707 1.10.4.2 nathanw /* 708 1.10.4.2 nathanw * hold RESET at least 10us. 709 1.10.4.2 nathanw */ 710 1.10.4.2 nathanw delay(10); 711 1.10.4.2 nathanw 712 1.10.4.2 nathanw /* deassert reset signal */ 713 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 714 1.10.4.2 nathanw reg &= ~IT8368_PIN_BCRDRST; 715 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 716 1.10.4.2 nathanw delay(20000); 717 1.10.4.2 nathanw 718 1.10.4.2 nathanw DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 719 1.10.4.2 nathanw #endif /* !WINCE_DEFAULT_SETTING */ 720 1.10.4.2 nathanw } 721 1.10.4.2 nathanw 722 1.10.4.2 nathanw void 723 1.10.4.2 nathanw it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 724 1.10.4.2 nathanw { 725 1.10.4.2 nathanw #ifndef WINCE_DEFAULT_SETTING 726 1.10.4.2 nathanw struct it8368e_softc *sc = (struct it8368e_softc*) pch; 727 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 728 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 729 1.10.4.2 nathanw u_int16_t reg; 730 1.10.4.2 nathanw 731 1.10.4.2 nathanw /* Power down */ 732 1.10.4.2 nathanw reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 733 1.10.4.2 nathanw reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 734 1.10.4.2 nathanw reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 735 1.10.4.2 nathanw it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 736 1.10.4.2 nathanw delay(20000); 737 1.10.4.2 nathanw 738 1.10.4.2 nathanw /* 739 1.10.4.2 nathanw * wait 300ms until power fails (Tpf). 740 1.10.4.2 nathanw */ 741 1.10.4.2 nathanw delay(300 * 1000); 742 1.10.4.2 nathanw 743 1.10.4.2 nathanw DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 744 1.10.4.2 nathanw #endif /* !WINCE_DEFAULT_SETTING */ 745 1.10.4.2 nathanw } 746 1.10.4.2 nathanw 747 1.10.4.2 nathanw #ifdef IT8368DEBUG 748 1.10.4.2 nathanw #define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 749 1.10.4.2 nathanw IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, 1) 750 1.10.4.2 nathanw #define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 751 1.10.4.2 nathanw IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, 1) 752 1.10.4.2 nathanw void 753 1.10.4.2 nathanw it8368_dump(struct it8368e_softc *sc) 754 1.10.4.2 nathanw { 755 1.10.4.2 nathanw bus_space_tag_t csregt = sc->sc_csregt; 756 1.10.4.2 nathanw bus_space_handle_t csregh = sc->sc_csregh; 757 1.10.4.2 nathanw 758 1.10.4.2 nathanw printf("[GPIO]\n"); 759 1.10.4.2 nathanw PRINTGPIO(DIR); 760 1.10.4.2 nathanw PRINTGPIO(DATAIN); 761 1.10.4.2 nathanw PRINTGPIO(DATAOUT); 762 1.10.4.2 nathanw PRINTGPIO(POSINTEN); 763 1.10.4.2 nathanw PRINTGPIO(NEGINTEN); 764 1.10.4.2 nathanw PRINTGPIO(POSINTSTAT); 765 1.10.4.2 nathanw PRINTGPIO(NEGINTSTAT); 766 1.10.4.2 nathanw printf("[MFIO]\n"); 767 1.10.4.2 nathanw PRINTMFIO(SEL); 768 1.10.4.2 nathanw PRINTMFIO(DIR); 769 1.10.4.2 nathanw PRINTMFIO(DATAIN); 770 1.10.4.2 nathanw PRINTMFIO(DATAOUT); 771 1.10.4.2 nathanw PRINTMFIO(POSINTEN); 772 1.10.4.2 nathanw PRINTMFIO(NEGINTEN); 773 1.10.4.2 nathanw PRINTMFIO(POSINTSTAT); 774 1.10.4.2 nathanw PRINTMFIO(NEGINTSTAT); 775 1.10.4.2 nathanw __bitdisp(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 776 1.10.4.2 nathanw "CTRL", 1); 777 1.10.4.2 nathanw __bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 778 1.10.4.2 nathanw 8, 11, "]CRDDET/SENSE[", 1); 779 1.10.4.2 nathanw } 780 1.10.4.2 nathanw #endif /* IT8368DEBUG */ 781
Indexes created Fri Oct 17 09:09:57 GMT 2025