it8368.c revision 1.10
1 /* $NetBSD: it8368.c,v 1.10 2001/09/15 12:47:04 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #undef WINCE_DEFAULT_SETTING /* for debug */ 40 #undef IT8368DEBUG 41 #include "opt_tx39_debug.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 #include <dev/pcmcia/pcmciachip.h> 52 53 #include <hpcmips/tx/tx39var.h> 54 #include <hpcmips/tx/txcsbusvar.h> 55 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 56 #include <hpcmips/dev/it8368var.h> 57 #include <hpcmips/dev/it8368reg.h> 58 59 #ifdef IT8368DEBUG 60 int it8368debug = 1; 61 #define DPRINTF(arg) if (it8368debug) printf arg; 62 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 63 #else 64 #define DPRINTF(arg) 65 #define DPRINTFN(n, arg) 66 #endif 67 68 int it8368e_match(struct device *, struct cfdata *, void *); 69 void it8368e_attach(struct device *, struct device *, void *); 70 int it8368_print(void *, const char *); 71 int it8368_submatch(struct device *, struct cfdata *, void *); 72 73 #define IT8368_LASTSTATE_PRESENT 0x0002 74 #define IT8368_LASTSTATE_HALF 0x0001 75 #define IT8368_LASTSTATE_EMPTY 0x0000 76 77 struct it8368e_softc { 78 struct device sc_dev; 79 struct device *sc_pcmcia; 80 tx_chipset_tag_t sc_tc; 81 82 /* Register space */ 83 bus_space_tag_t sc_csregt; 84 bus_space_handle_t sc_csregh; 85 /* I/O, attribute space */ 86 bus_space_tag_t sc_csiot; 87 bus_addr_t sc_csiobase; 88 bus_size_t sc_csiosize; 89 /* 90 * XXX theses means attribute memory. not memory space. 91 * memory space is 0x64000000. 92 */ 93 bus_space_tag_t sc_csmemt; 94 bus_addr_t sc_csmembase; 95 bus_size_t sc_csmemsize; 96 97 /* Separate I/O and attribute space mode */ 98 int sc_fixattr; 99 100 /* Card interrupt handler */ 101 int (*sc_card_fun)(void *); 102 void *sc_card_arg; 103 void *sc_card_ih; 104 int sc_card_irq; 105 106 /* Card status change */ 107 int sc_irq; 108 void *sc_ih; 109 int sc_laststate; 110 }; 111 112 void it8368_init_socket(struct it8368e_softc*); 113 void it8368_attach_socket(struct it8368e_softc *); 114 int it8368_intr(void *); 115 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 116 struct pcmcia_mem_handle *); 117 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 118 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 119 struct pcmcia_mem_handle *, bus_addr_t *, int *); 120 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 121 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 122 bus_size_t, struct pcmcia_io_handle *); 123 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 124 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 125 struct pcmcia_io_handle *, int *); 126 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 127 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 128 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 129 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 130 struct pcmcia_function *, int, int (*) (void *), void *); 131 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 132 133 #ifdef IT8368DEBUG 134 void it8368_dump(struct it8368e_softc *); 135 #endif 136 137 static struct pcmcia_chip_functions it8368_functions = { 138 it8368_chip_mem_alloc, 139 it8368_chip_mem_free, 140 it8368_chip_mem_map, 141 it8368_chip_mem_unmap, 142 it8368_chip_io_alloc, 143 it8368_chip_io_free, 144 it8368_chip_io_map, 145 it8368_chip_io_unmap, 146 it8368_chip_intr_establish, 147 it8368_chip_intr_disestablish, 148 it8368_chip_socket_enable, 149 it8368_chip_socket_disable 150 }; 151 152 struct cfattach it8368e_ca = { 153 sizeof(struct it8368e_softc), it8368e_match, it8368e_attach 154 }; 155 156 /* 157 * IT8368 configuration register is big-endian. 158 */ 159 static __inline__ u_int16_t it8368_reg_read(bus_space_tag_t, 160 bus_space_handle_t, int); 161 static __inline__ void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 162 int, u_int16_t); 163 164 #ifdef IT8368E_DESTRUCTIVE_CHECK 165 int it8368e_id_check(void *); 166 167 /* 168 * IT8368E don't have identification method. this is destructive check. 169 */ 170 int 171 it8368e_id_check(void *aux) 172 { 173 struct cs_attach_args *ca = aux; 174 tx_chipset_tag_t tc; 175 bus_space_tag_t csregt; 176 bus_space_handle_t csregh; 177 u_int16_t oreg, reg; 178 int match = 0; 179 180 tc = ca->ca_tc; 181 csregt = ca->ca_csreg.cstag; 182 183 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 184 0, &csregh); 185 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 186 oreg = reg; 187 bitdisp(reg); 188 189 reg &= ~IT8368_CTRL_BYTESWAP; 190 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 191 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 192 if (reg & IT8368_CTRL_BYTESWAP) 193 goto nomatch; 194 195 reg |= IT8368_CTRL_BYTESWAP; 196 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 197 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 198 if (!(reg & IT8368_CTRL_BYTESWAP)) 199 goto nomatch; 200 201 match = 1; 202 nomatch: 203 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 204 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 205 206 return (match); 207 } 208 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 209 210 int 211 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 #ifdef IT8368E_DESTRUCTIVE_CHECK 214 return (it8368e_id_check(aux)); 215 #else 216 return (1); 217 #endif 218 } 219 220 void 221 it8368e_attach(struct device *parent, struct device *self, void *aux) 222 { 223 struct cs_attach_args *ca = aux; 224 struct it8368e_softc *sc = (void*)self; 225 tx_chipset_tag_t tc; 226 bus_space_tag_t csregt; 227 bus_space_handle_t csregh; 228 u_int16_t reg; 229 230 sc->sc_tc = tc = ca->ca_tc; 231 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 232 233 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 234 0, &sc->sc_csregh); 235 csregh = sc->sc_csregh; 236 sc->sc_csiot = ca->ca_csio.cstag; 237 sc->sc_csiobase = ca->ca_csio.csbase; 238 sc->sc_csiosize = ca->ca_csio.cssize; 239 240 #ifdef IT8368DEBUG 241 printf("\n\t[Windows CE setting]\n"); 242 it8368_dump(sc); /* print WindowsCE setting */ 243 #endif 244 /* LHA[14:13] <= HA[14:13] */ 245 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 246 reg &= ~IT8368_CTRL_ADDRSEL; 247 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 248 249 /* Set all MFIO direction as LHA[23:13] output pins */ 250 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 251 reg |= IT8368_MFIODIR_MASK; 252 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 253 254 /* Set all MFIO functions as LHA */ 255 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 256 reg &= ~IT8368_MFIOSEL_MASK; 257 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 258 259 /* Disable MFIO interrupt */ 260 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 261 reg &= ~IT8368_MFIOPOSINTEN_MASK; 262 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 263 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 264 reg &= ~IT8368_MFIONEGINTEN_MASK; 265 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 266 267 /* Port direction */ 268 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 269 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 270 IT8368_PIN_BCRDRST; 271 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 272 printf("\n"); 273 274 /* 275 * Separate I/O and attribute memory region 276 */ 277 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 278 279 reg |= IT8368_CTRL_FIXATTRIO; 280 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 281 282 if (IT8368_CTRL_FIXATTRIO & 283 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 284 sc->sc_fixattr = 1; 285 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 286 } else { 287 sc->sc_fixattr = 0; 288 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 289 } 290 291 sc->sc_csmemt = sc->sc_csiot; 292 sc->sc_csiosize /= 2; 293 sc->sc_csmemsize = sc->sc_csiosize; 294 sc->sc_csmembase = sc->sc_csiosize; 295 296 #ifdef IT8368DEBUG 297 it8368_dump(sc); 298 #endif 299 /* Enable card and interrupt driving. */ 300 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 301 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 302 if (sc->sc_fixattr) 303 reg |= IT8368_CTRL_FIXATTRIO; 304 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 305 306 sc->sc_irq = ca->ca_irq1; 307 sc->sc_card_irq = ca->ca_irq3; 308 309 it8368_attach_socket(sc); 310 } 311 312 __inline__ u_int16_t 313 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 314 { 315 u_int16_t val; 316 317 val = bus_space_read_2(t, h, ofs); 318 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 319 } 320 321 __inline__ void 322 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 323 { 324 u_int16_t val; 325 326 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 327 bus_space_write_2(t, h, ofs, val); 328 } 329 330 int 331 it8368_intr(void *arg) 332 { 333 struct it8368e_softc *sc = arg; 334 bus_space_tag_t csregt = sc->sc_csregt; 335 bus_space_handle_t csregh = sc->sc_csregh; 336 u_int16_t reg; 337 338 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 339 340 if (reg & IT8368_PIN_BCRDRDY) { 341 if (sc->sc_card_fun) { 342 /* clear interrupt */ 343 it8368_reg_write(csregt, csregh, 344 IT8368_GPIONEGINTSTAT_REG, 345 IT8368_PIN_BCRDRDY); 346 347 /* Dispatch card interrupt handler */ 348 (*sc->sc_card_fun)(sc->sc_card_arg); 349 } 350 } else if (reg & IT8368_PIN_CRDDET2) { 351 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 352 IT8368_PIN_CRDDET2); 353 printf("[CSC]\n"); 354 #ifdef IT8368DEBUG 355 it8368_dump(sc); 356 #endif 357 it8368_chip_socket_disable(sc); 358 } else { 359 #ifdef IT8368DEBUG 360 u_int16_t reg2; 361 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 362 printf("unknown it8368 interrupt: "); 363 bitdisp(reg2); 364 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 365 reg); 366 #endif 367 } 368 369 return (0); 370 } 371 372 int 373 it8368_print(void *arg, const char *pnp) 374 { 375 if (pnp) 376 printf("pcmcia at %s", pnp); 377 378 return (UNCONF); 379 } 380 381 int 382 it8368_submatch(struct device *parent, struct cfdata *cf, void *aux) 383 { 384 385 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 386 } 387 388 void 389 it8368_attach_socket(struct it8368e_softc *sc) 390 { 391 struct pcmciabus_attach_args paa; 392 393 paa.paa_busname = "pcmcia"; 394 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 395 paa.pch = (pcmcia_chipset_handle_t)sc; 396 paa.iobase = 0; 397 paa.iosize = sc->sc_csiosize; 398 399 if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 400 it8368_submatch))) { 401 402 it8368_init_socket(sc); 403 } 404 } 405 406 void 407 it8368_init_socket(struct it8368e_softc *sc) 408 { 409 bus_space_tag_t csregt = sc->sc_csregt; 410 bus_space_handle_t csregh = sc->sc_csregh; 411 u_int16_t reg; 412 413 /* 414 * set up the card to interrupt on card detect 415 */ 416 reg = IT8368_PIN_CRDDET2; /* CSC */ 417 /* enable negative edge */ 418 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 419 /* disable positive edge */ 420 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 421 422 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 423 IST_EDGE, IPL_BIO, it8368_intr, sc); 424 if (sc->sc_ih == NULL) { 425 printf("%s: can't establish interrupt\n", 426 sc->sc_dev.dv_xname); 427 return; 428 } 429 430 /* 431 * if there's a card there, then attach it. 432 */ 433 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 434 435 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 436 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 437 } else { 438 pcmcia_card_attach(sc->sc_pcmcia); 439 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 440 } 441 } 442 443 void * 444 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 445 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 446 { 447 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 448 bus_space_tag_t csregt = sc->sc_csregt; 449 bus_space_handle_t csregh = sc->sc_csregh; 450 u_int16_t reg; 451 452 if (sc->sc_card_fun) 453 panic("it8368_chip_intr_establish: " 454 "duplicate card interrupt handler."); 455 456 sc->sc_card_fun = ih_fun; 457 sc->sc_card_arg = ih_arg; 458 459 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 460 IST_EDGE, IPL_BIO, it8368_intr, 461 sc); 462 463 /* enable card interrupt */ 464 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 465 reg |= IT8368_PIN_BCRDRDY; 466 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 467 468 return (sc->sc_card_ih); 469 } 470 471 void 472 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 473 { 474 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 475 bus_space_tag_t csregt = sc->sc_csregt; 476 bus_space_handle_t csregh = sc->sc_csregh; 477 u_int16_t reg; 478 479 if (!sc->sc_card_fun) 480 panic("it8368_chip_intr_disestablish:" 481 "no handler established."); 482 assert(ih == sc->sc_card_ih); 483 484 sc->sc_card_fun = 0; 485 sc->sc_card_arg = 0; 486 487 /* disable card interrupt */ 488 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 489 reg &= ~IT8368_PIN_BCRDRDY; 490 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 491 492 tx_intr_disestablish(sc->sc_tc, ih); 493 } 494 495 int 496 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 497 struct pcmcia_mem_handle *pcmhp) 498 { 499 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 500 501 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 502 sc->sc_csmembase + sc->sc_csmemsize, size, 503 size, 0, 0, 0, &pcmhp->memh)) { 504 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 505 return (1); 506 } 507 508 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 509 pcmhp->memh -= sc->sc_csmembase; 510 511 pcmhp->memt = sc->sc_csmemt; 512 pcmhp->addr = pcmhp->memh; 513 pcmhp->size = size; 514 pcmhp->realsize = size; 515 516 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 517 (unsigned)pcmhp->memh, (unsigned)size)); 518 519 return (0); 520 } 521 522 void 523 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 524 struct pcmcia_mem_handle *pcmhp) 525 { 526 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 527 528 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 529 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 530 531 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 532 pcmhp->memh += sc->sc_csmembase; 533 534 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 535 } 536 537 int 538 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 539 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 540 bus_addr_t *offsetp, int *windowp) 541 { 542 /* attribute mode */ 543 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 544 545 *offsetp = card_addr; 546 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 547 (unsigned)pcmhp->memh, (unsigned)size)); 548 549 return (0); 550 } 551 552 void 553 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 554 { 555 /* return to I/O mode */ 556 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 557 } 558 559 void 560 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 561 { 562 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 563 txreg_t reg32; 564 565 DPRINTF(("it8368_mode: change access space to ")); 566 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 567 width == IT8368_WIDTH_8 ? 8 : 16)); 568 569 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 570 571 if (io) { 572 if (width == IT8368_WIDTH_8) 573 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 574 else 575 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 576 } 577 578 if (!sc->sc_fixattr) { 579 if (io) 580 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 581 else 582 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 583 } 584 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 585 586 #ifdef IT8368DEBUG 587 if (sc->sc_fixattr) 588 return; /* No need to report BIU status */ 589 590 /* check BIU status */ 591 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 592 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 593 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 594 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 595 } else { 596 DPRINTF(("it8368_mode: atttribute space enabled\n")); 597 } 598 #endif /* IT8368DEBUG */ 599 } 600 601 int 602 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 603 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 604 { 605 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 606 607 if (start) { 608 if (bus_space_map(sc->sc_csiot, start, size, 0, 609 &pcihp->ioh)) { 610 return (1); 611 } 612 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 613 (unsigned)start, (unsigned)size)); 614 } else { 615 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 616 sc->sc_csiobase + sc->sc_csiosize, 617 size, align, 0, 0, &pcihp->addr, 618 &pcihp->ioh)) { 619 620 return (1); 621 } 622 pcihp->flags = PCMCIA_IO_ALLOCATED; 623 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 624 (unsigned)size, (unsigned)pcihp->addr)); 625 } 626 627 pcihp->iot = sc->sc_csiot; 628 pcihp->size = size; 629 630 return (0); 631 } 632 633 int 634 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 635 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 636 { 637 /* I/O mode */ 638 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 639 640 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 641 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 642 643 return (0); 644 } 645 646 void 647 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 648 struct pcmcia_io_handle *pcihp) 649 { 650 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 651 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 652 else 653 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 654 655 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 656 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 657 } 658 659 void 660 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 661 { 662 663 } 664 665 void 666 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 667 { 668 #ifndef WINCE_DEFAULT_SETTING 669 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 670 bus_space_tag_t csregt = sc->sc_csregt; 671 bus_space_handle_t csregh = sc->sc_csregh; 672 volatile u_int16_t reg; 673 674 /* Power off */ 675 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 676 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 677 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 678 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 679 delay(20000); 680 681 /* 682 * wait 300ms until power fails (Tpf). Then, wait 100ms since 683 * we are changing Vcc (Toff). 684 */ 685 delay((300 + 100) * 1000); 686 687 /* Supply Vcc */ 688 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 689 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 690 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 691 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 692 693 /* 694 * wait 100ms until power raise (Tpr) and 20ms to become 695 * stable (Tsu(Vcc)). 696 * 697 * some machines require some more time to be settled 698 * (300ms is added here). 699 */ 700 delay((100 + 20 + 300) * 1000); 701 702 /* Assert reset signal */ 703 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 704 reg |= IT8368_PIN_BCRDRST; 705 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 706 707 /* 708 * hold RESET at least 10us. 709 */ 710 delay(10); 711 712 /* deassert reset signal */ 713 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 714 reg &= ~IT8368_PIN_BCRDRST; 715 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 716 delay(20000); 717 718 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 719 #endif /* !WINCE_DEFAULT_SETTING */ 720 } 721 722 void 723 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 724 { 725 #ifndef WINCE_DEFAULT_SETTING 726 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 727 bus_space_tag_t csregt = sc->sc_csregt; 728 bus_space_handle_t csregh = sc->sc_csregh; 729 u_int16_t reg; 730 731 /* Power down */ 732 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 733 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 734 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 735 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 736 delay(20000); 737 738 /* 739 * wait 300ms until power fails (Tpf). 740 */ 741 delay(300 * 1000); 742 743 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 744 #endif /* !WINCE_DEFAULT_SETTING */ 745 } 746 747 #ifdef IT8368DEBUG 748 #define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 749 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, 1) 750 #define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 751 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, 1) 752 void 753 it8368_dump(struct it8368e_softc *sc) 754 { 755 bus_space_tag_t csregt = sc->sc_csregt; 756 bus_space_handle_t csregh = sc->sc_csregh; 757 758 printf("[GPIO]\n"); 759 PRINTGPIO(DIR); 760 PRINTGPIO(DATAIN); 761 PRINTGPIO(DATAOUT); 762 PRINTGPIO(POSINTEN); 763 PRINTGPIO(NEGINTEN); 764 PRINTGPIO(POSINTSTAT); 765 PRINTGPIO(NEGINTSTAT); 766 printf("[MFIO]\n"); 767 PRINTMFIO(SEL); 768 PRINTMFIO(DIR); 769 PRINTMFIO(DATAIN); 770 PRINTMFIO(DATAOUT); 771 PRINTMFIO(POSINTEN); 772 PRINTMFIO(NEGINTEN); 773 PRINTMFIO(POSINTSTAT); 774 PRINTMFIO(NEGINTSTAT); 775 __bitdisp(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 776 "CTRL", 1); 777 __bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 778 8, 11, "]CRDDET/SENSE[", 1); 779 } 780 #endif /* IT8368DEBUG */ 781
Indexes created Tue Sep 30 11:09:46 GMT 2025