it8368.c revision 1.13
1 /* $NetBSD: it8368.c,v 1.13 2002/05/03 07:31:24 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #undef WINCE_DEFAULT_SETTING /* for debug */ 40 #undef IT8368DEBUG 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 #include <dev/pcmcia/pcmciachip.h> 51 52 #include <hpcmips/tx/tx39var.h> 53 #include <hpcmips/tx/txcsbusvar.h> 54 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 55 #include <hpcmips/dev/it8368var.h> 56 #include <hpcmips/dev/it8368reg.h> 57 58 #ifdef IT8368DEBUG 59 int it8368debug = 1; 60 #define DPRINTF(arg) if (it8368debug) printf arg; 61 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 62 #else 63 #define DPRINTF(arg) 64 #define DPRINTFN(n, arg) 65 #endif 66 67 int it8368e_match(struct device *, struct cfdata *, void *); 68 void it8368e_attach(struct device *, struct device *, void *); 69 int it8368_print(void *, const char *); 70 int it8368_submatch(struct device *, struct cfdata *, void *); 71 72 #define IT8368_LASTSTATE_PRESENT 0x0002 73 #define IT8368_LASTSTATE_HALF 0x0001 74 #define IT8368_LASTSTATE_EMPTY 0x0000 75 76 struct it8368e_softc { 77 struct device sc_dev; 78 struct device *sc_pcmcia; 79 tx_chipset_tag_t sc_tc; 80 81 /* Register space */ 82 bus_space_tag_t sc_csregt; 83 bus_space_handle_t sc_csregh; 84 /* I/O, attribute space */ 85 bus_space_tag_t sc_csiot; 86 bus_addr_t sc_csiobase; 87 bus_size_t sc_csiosize; 88 /* 89 * XXX theses means attribute memory. not memory space. 90 * memory space is 0x64000000. 91 */ 92 bus_space_tag_t sc_csmemt; 93 bus_addr_t sc_csmembase; 94 bus_size_t sc_csmemsize; 95 96 /* Separate I/O and attribute space mode */ 97 int sc_fixattr; 98 99 /* Card interrupt handler */ 100 int (*sc_card_fun)(void *); 101 void *sc_card_arg; 102 void *sc_card_ih; 103 int sc_card_irq; 104 105 /* Card status change */ 106 int sc_irq; 107 void *sc_ih; 108 int sc_laststate; 109 }; 110 111 void it8368_init_socket(struct it8368e_softc*); 112 void it8368_attach_socket(struct it8368e_softc *); 113 int it8368_intr(void *); 114 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 115 struct pcmcia_mem_handle *); 116 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 117 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 118 struct pcmcia_mem_handle *, bus_addr_t *, int *); 119 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 120 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 121 bus_size_t, struct pcmcia_io_handle *); 122 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 123 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 124 struct pcmcia_io_handle *, int *); 125 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 126 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 127 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 128 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 129 struct pcmcia_function *, int, int (*) (void *), void *); 130 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 131 132 #ifdef IT8368DEBUG 133 void it8368_dump(struct it8368e_softc *); 134 #endif 135 136 static struct pcmcia_chip_functions it8368_functions = { 137 it8368_chip_mem_alloc, 138 it8368_chip_mem_free, 139 it8368_chip_mem_map, 140 it8368_chip_mem_unmap, 141 it8368_chip_io_alloc, 142 it8368_chip_io_free, 143 it8368_chip_io_map, 144 it8368_chip_io_unmap, 145 it8368_chip_intr_establish, 146 it8368_chip_intr_disestablish, 147 it8368_chip_socket_enable, 148 it8368_chip_socket_disable 149 }; 150 151 struct cfattach it8368e_ca = { 152 sizeof(struct it8368e_softc), it8368e_match, it8368e_attach 153 }; 154 155 /* 156 * IT8368 configuration register is big-endian. 157 */ 158 static __inline__ u_int16_t it8368_reg_read(bus_space_tag_t, 159 bus_space_handle_t, int); 160 static __inline__ void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 161 int, u_int16_t); 162 163 #ifdef IT8368E_DESTRUCTIVE_CHECK 164 int it8368e_id_check(void *); 165 166 /* 167 * IT8368E don't have identification method. this is destructive check. 168 */ 169 int 170 it8368e_id_check(void *aux) 171 { 172 struct cs_attach_args *ca = aux; 173 tx_chipset_tag_t tc; 174 bus_space_tag_t csregt; 175 bus_space_handle_t csregh; 176 u_int16_t oreg, reg; 177 int match = 0; 178 179 tc = ca->ca_tc; 180 csregt = ca->ca_csreg.cstag; 181 182 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 183 0, &csregh); 184 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 185 oreg = reg; 186 dbg_bit_print(reg); 187 188 reg &= ~IT8368_CTRL_BYTESWAP; 189 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 190 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 191 if (reg & IT8368_CTRL_BYTESWAP) 192 goto nomatch; 193 194 reg |= IT8368_CTRL_BYTESWAP; 195 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 196 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 197 if (!(reg & IT8368_CTRL_BYTESWAP)) 198 goto nomatch; 199 200 match = 1; 201 nomatch: 202 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 203 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 204 205 return (match); 206 } 207 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 208 209 int 210 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 211 { 212 #ifdef IT8368E_DESTRUCTIVE_CHECK 213 return (it8368e_id_check(aux)); 214 #else 215 return (1); 216 #endif 217 } 218 219 void 220 it8368e_attach(struct device *parent, struct device *self, void *aux) 221 { 222 struct cs_attach_args *ca = aux; 223 struct it8368e_softc *sc = (void*)self; 224 tx_chipset_tag_t tc; 225 bus_space_tag_t csregt; 226 bus_space_handle_t csregh; 227 u_int16_t reg; 228 229 sc->sc_tc = tc = ca->ca_tc; 230 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 231 232 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 233 0, &sc->sc_csregh); 234 csregh = sc->sc_csregh; 235 sc->sc_csiot = ca->ca_csio.cstag; 236 sc->sc_csiobase = ca->ca_csio.csbase; 237 sc->sc_csiosize = ca->ca_csio.cssize; 238 239 #ifdef IT8368DEBUG 240 printf("\n\t[Windows CE setting]\n"); 241 it8368_dump(sc); /* print WindowsCE setting */ 242 #endif 243 /* LHA[14:13] <= HA[14:13] */ 244 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 245 reg &= ~IT8368_CTRL_ADDRSEL; 246 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 247 248 /* Set all MFIO direction as LHA[23:13] output pins */ 249 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 250 reg |= IT8368_MFIODIR_MASK; 251 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 252 253 /* Set all MFIO functions as LHA */ 254 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 255 reg &= ~IT8368_MFIOSEL_MASK; 256 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 257 258 /* Disable MFIO interrupt */ 259 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 260 reg &= ~IT8368_MFIOPOSINTEN_MASK; 261 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 262 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 263 reg &= ~IT8368_MFIONEGINTEN_MASK; 264 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 265 266 /* Port direction */ 267 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 268 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 269 IT8368_PIN_BCRDRST; 270 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 271 printf("\n"); 272 273 /* 274 * Separate I/O and attribute memory region 275 */ 276 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 277 278 reg |= IT8368_CTRL_FIXATTRIO; 279 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 280 281 if (IT8368_CTRL_FIXATTRIO & 282 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 283 sc->sc_fixattr = 1; 284 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 285 } else { 286 sc->sc_fixattr = 0; 287 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 288 } 289 290 sc->sc_csmemt = sc->sc_csiot; 291 sc->sc_csiosize /= 2; 292 sc->sc_csmemsize = sc->sc_csiosize; 293 sc->sc_csmembase = sc->sc_csiosize; 294 295 #ifdef IT8368DEBUG 296 it8368_dump(sc); 297 #endif 298 /* Enable card and interrupt driving. */ 299 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 300 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 301 if (sc->sc_fixattr) 302 reg |= IT8368_CTRL_FIXATTRIO; 303 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 304 305 sc->sc_irq = ca->ca_irq1; 306 sc->sc_card_irq = ca->ca_irq3; 307 308 it8368_attach_socket(sc); 309 } 310 311 __inline__ u_int16_t 312 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 313 { 314 u_int16_t val; 315 316 val = bus_space_read_2(t, h, ofs); 317 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 318 } 319 320 __inline__ void 321 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 322 { 323 u_int16_t val; 324 325 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 326 bus_space_write_2(t, h, ofs, val); 327 } 328 329 int 330 it8368_intr(void *arg) 331 { 332 struct it8368e_softc *sc = arg; 333 bus_space_tag_t csregt = sc->sc_csregt; 334 bus_space_handle_t csregh = sc->sc_csregh; 335 u_int16_t reg; 336 337 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 338 339 if (reg & IT8368_PIN_BCRDRDY) { 340 if (sc->sc_card_fun) { 341 /* clear interrupt */ 342 it8368_reg_write(csregt, csregh, 343 IT8368_GPIONEGINTSTAT_REG, 344 IT8368_PIN_BCRDRDY); 345 346 /* Dispatch card interrupt handler */ 347 (*sc->sc_card_fun)(sc->sc_card_arg); 348 } 349 } else if (reg & IT8368_PIN_CRDDET2) { 350 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 351 IT8368_PIN_CRDDET2); 352 printf("[CSC]\n"); 353 #ifdef IT8368DEBUG 354 it8368_dump(sc); 355 #endif 356 it8368_chip_socket_disable(sc); 357 } else { 358 #ifdef IT8368DEBUG 359 u_int16_t reg2; 360 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 361 printf("unknown it8368 interrupt: "); 362 dbg_bit_print(reg2); 363 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 364 reg); 365 #endif 366 } 367 368 return (0); 369 } 370 371 int 372 it8368_print(void *arg, const char *pnp) 373 { 374 if (pnp) 375 printf("pcmcia at %s", pnp); 376 377 return (UNCONF); 378 } 379 380 int 381 it8368_submatch(struct device *parent, struct cfdata *cf, void *aux) 382 { 383 384 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 385 } 386 387 void 388 it8368_attach_socket(struct it8368e_softc *sc) 389 { 390 struct pcmciabus_attach_args paa; 391 392 paa.paa_busname = "pcmcia"; 393 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 394 paa.pch = (pcmcia_chipset_handle_t)sc; 395 paa.iobase = 0; 396 paa.iosize = sc->sc_csiosize; 397 398 if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 399 it8368_submatch))) { 400 401 it8368_init_socket(sc); 402 } 403 } 404 405 void 406 it8368_init_socket(struct it8368e_softc *sc) 407 { 408 bus_space_tag_t csregt = sc->sc_csregt; 409 bus_space_handle_t csregh = sc->sc_csregh; 410 u_int16_t reg; 411 412 /* 413 * set up the card to interrupt on card detect 414 */ 415 reg = IT8368_PIN_CRDDET2; /* CSC */ 416 /* enable negative edge */ 417 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 418 /* disable positive edge */ 419 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 420 421 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 422 IST_EDGE, IPL_BIO, it8368_intr, sc); 423 if (sc->sc_ih == NULL) { 424 printf("%s: can't establish interrupt\n", 425 sc->sc_dev.dv_xname); 426 return; 427 } 428 429 /* 430 * if there's a card there, then attach it. 431 */ 432 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 433 434 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 435 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 436 } else { 437 pcmcia_card_attach(sc->sc_pcmcia); 438 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 439 } 440 } 441 442 void * 443 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 444 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 445 { 446 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 447 bus_space_tag_t csregt = sc->sc_csregt; 448 bus_space_handle_t csregh = sc->sc_csregh; 449 u_int16_t reg; 450 451 if (sc->sc_card_fun) 452 panic("it8368_chip_intr_establish: " 453 "duplicate card interrupt handler."); 454 455 sc->sc_card_fun = ih_fun; 456 sc->sc_card_arg = ih_arg; 457 458 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 459 IST_EDGE, IPL_BIO, it8368_intr, 460 sc); 461 462 /* enable card interrupt */ 463 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 464 reg |= IT8368_PIN_BCRDRDY; 465 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 466 467 return (sc->sc_card_ih); 468 } 469 470 void 471 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 472 { 473 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 474 bus_space_tag_t csregt = sc->sc_csregt; 475 bus_space_handle_t csregh = sc->sc_csregh; 476 u_int16_t reg; 477 478 if (!sc->sc_card_fun) 479 panic("it8368_chip_intr_disestablish:" 480 "no handler established."); 481 assert(ih == sc->sc_card_ih); 482 483 sc->sc_card_fun = 0; 484 sc->sc_card_arg = 0; 485 486 /* disable card interrupt */ 487 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 488 reg &= ~IT8368_PIN_BCRDRDY; 489 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 490 491 tx_intr_disestablish(sc->sc_tc, ih); 492 } 493 494 int 495 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 496 struct pcmcia_mem_handle *pcmhp) 497 { 498 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 499 500 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 501 sc->sc_csmembase + sc->sc_csmemsize, size, 502 size, 0, 0, 0, &pcmhp->memh)) { 503 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 504 return (1); 505 } 506 507 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 508 pcmhp->memh -= sc->sc_csmembase; 509 510 pcmhp->memt = sc->sc_csmemt; 511 pcmhp->addr = pcmhp->memh; 512 pcmhp->size = size; 513 pcmhp->realsize = size; 514 515 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 516 (unsigned)pcmhp->memh, (unsigned)size)); 517 518 return (0); 519 } 520 521 void 522 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 523 struct pcmcia_mem_handle *pcmhp) 524 { 525 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 526 527 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 528 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 529 530 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 531 pcmhp->memh += sc->sc_csmembase; 532 533 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 534 } 535 536 int 537 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 538 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 539 bus_size_t *offsetp, int *windowp) 540 { 541 /* attribute mode */ 542 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 543 544 *offsetp = card_addr; 545 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 546 (unsigned)pcmhp->memh, (unsigned)size)); 547 548 return (0); 549 } 550 551 void 552 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 553 { 554 /* return to I/O mode */ 555 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 556 } 557 558 void 559 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 560 { 561 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 562 txreg_t reg32; 563 564 DPRINTF(("it8368_mode: change access space to ")); 565 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 566 width == IT8368_WIDTH_8 ? 8 : 16)); 567 568 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 569 570 if (io) { 571 if (width == IT8368_WIDTH_8) 572 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 573 else 574 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 575 } 576 577 if (!sc->sc_fixattr) { 578 if (io) 579 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 580 else 581 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 582 } 583 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 584 585 #ifdef IT8368DEBUG 586 if (sc->sc_fixattr) 587 return; /* No need to report BIU status */ 588 589 /* check BIU status */ 590 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 591 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 592 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 593 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 594 } else { 595 DPRINTF(("it8368_mode: atttribute space enabled\n")); 596 } 597 #endif /* IT8368DEBUG */ 598 } 599 600 int 601 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 602 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 603 { 604 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 605 606 if (start) { 607 if (bus_space_map(sc->sc_csiot, start, size, 0, 608 &pcihp->ioh)) { 609 return (1); 610 } 611 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 612 (unsigned)start, (unsigned)size)); 613 } else { 614 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 615 sc->sc_csiobase + sc->sc_csiosize, 616 size, align, 0, 0, &pcihp->addr, 617 &pcihp->ioh)) { 618 619 return (1); 620 } 621 pcihp->flags = PCMCIA_IO_ALLOCATED; 622 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 623 (unsigned)size, (unsigned)pcihp->addr)); 624 } 625 626 pcihp->iot = sc->sc_csiot; 627 pcihp->size = size; 628 629 return (0); 630 } 631 632 int 633 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 634 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 635 { 636 /* I/O mode */ 637 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 638 639 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 640 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 641 642 return (0); 643 } 644 645 void 646 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 647 struct pcmcia_io_handle *pcihp) 648 { 649 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 650 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 651 else 652 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 653 654 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 655 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 656 } 657 658 void 659 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 660 { 661 662 } 663 664 void 665 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 666 { 667 #ifndef WINCE_DEFAULT_SETTING 668 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 669 bus_space_tag_t csregt = sc->sc_csregt; 670 bus_space_handle_t csregh = sc->sc_csregh; 671 volatile u_int16_t reg; 672 673 /* Power off */ 674 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 675 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 676 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 677 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 678 delay(20000); 679 680 /* 681 * wait 300ms until power fails (Tpf). Then, wait 100ms since 682 * we are changing Vcc (Toff). 683 */ 684 delay((300 + 100) * 1000); 685 686 /* Supply Vcc */ 687 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 688 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 689 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 690 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 691 692 /* 693 * wait 100ms until power raise (Tpr) and 20ms to become 694 * stable (Tsu(Vcc)). 695 * 696 * some machines require some more time to be settled 697 * (300ms is added here). 698 */ 699 delay((100 + 20 + 300) * 1000); 700 701 /* Assert reset signal */ 702 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 703 reg |= IT8368_PIN_BCRDRST; 704 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 705 706 /* 707 * hold RESET at least 10us. 708 */ 709 delay(10); 710 711 /* deassert reset signal */ 712 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 713 reg &= ~IT8368_PIN_BCRDRST; 714 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 715 delay(20000); 716 717 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 718 #endif /* !WINCE_DEFAULT_SETTING */ 719 } 720 721 void 722 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 723 { 724 #ifndef WINCE_DEFAULT_SETTING 725 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 726 bus_space_tag_t csregt = sc->sc_csregt; 727 bus_space_handle_t csregh = sc->sc_csregh; 728 u_int16_t reg; 729 730 /* Power down */ 731 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 732 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 733 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 734 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 735 delay(20000); 736 737 /* 738 * wait 300ms until power fails (Tpf). 739 */ 740 delay(300 * 1000); 741 742 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 743 #endif /* !WINCE_DEFAULT_SETTING */ 744 } 745 746 #ifdef IT8368DEBUG 747 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 748 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 749 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 750 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 751 void 752 it8368_dump(struct it8368e_softc *sc) 753 { 754 bus_space_tag_t csregt = sc->sc_csregt; 755 bus_space_handle_t csregh = sc->sc_csregh; 756 757 printf("[GPIO]\n"); 758 PRINTGPIO(DIR); 759 PRINTGPIO(DATAIN); 760 PRINTGPIO(DATAOUT); 761 PRINTGPIO(POSINTEN); 762 PRINTGPIO(NEGINTEN); 763 PRINTGPIO(POSINTSTAT); 764 PRINTGPIO(NEGINTSTAT); 765 printf("[MFIO]\n"); 766 PRINTMFIO(SEL); 767 PRINTMFIO(DIR); 768 PRINTMFIO(DATAIN); 769 PRINTMFIO(DATAOUT); 770 PRINTMFIO(POSINTEN); 771 PRINTMFIO(NEGINTEN); 772 PRINTMFIO(POSINTSTAT); 773 PRINTMFIO(NEGINTSTAT); 774 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 775 "CTRL", DBG_BIT_PRINT_COUNT); 776 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 777 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 778 } 779 #endif /* IT8368DEBUG */ 780
Indexes created Tue Sep 30 20:09:53 GMT 2025