it8368.c revision 1.17
1 /* $NetBSD: it8368.c,v 1.17 2003/01/01 01:40:26 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #undef WINCE_DEFAULT_SETTING /* for debug */ 40 #undef IT8368DEBUG 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <machine/bus.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 #include <dev/pcmcia/pcmciachip.h> 51 52 #include <hpcmips/tx/tx39var.h> 53 #include <hpcmips/tx/txcsbusvar.h> 54 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 55 #include <hpcmips/dev/it8368var.h> 56 #include <hpcmips/dev/it8368reg.h> 57 58 #ifdef IT8368DEBUG 59 int it8368debug = 1; 60 #define DPRINTF(arg) if (it8368debug) printf arg; 61 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 62 #else 63 #define DPRINTF(arg) 64 #define DPRINTFN(n, arg) 65 #endif 66 67 int it8368e_match(struct device *, struct cfdata *, void *); 68 void it8368e_attach(struct device *, struct device *, void *); 69 int it8368_print(void *, const char *); 70 int it8368_submatch(struct device *, struct cfdata *, void *); 71 72 #define IT8368_LASTSTATE_PRESENT 0x0002 73 #define IT8368_LASTSTATE_HALF 0x0001 74 #define IT8368_LASTSTATE_EMPTY 0x0000 75 76 struct it8368e_softc { 77 struct device sc_dev; 78 struct device *sc_pcmcia; 79 tx_chipset_tag_t sc_tc; 80 81 /* Register space */ 82 bus_space_tag_t sc_csregt; 83 bus_space_handle_t sc_csregh; 84 /* I/O, attribute space */ 85 bus_space_tag_t sc_csiot; 86 bus_addr_t sc_csiobase; 87 bus_size_t sc_csiosize; 88 /* 89 * XXX theses means attribute memory. not memory space. 90 * memory space is 0x64000000. 91 */ 92 bus_space_tag_t sc_csmemt; 93 bus_addr_t sc_csmembase; 94 bus_size_t sc_csmemsize; 95 96 /* Separate I/O and attribute space mode */ 97 int sc_fixattr; 98 99 /* Card interrupt handler */ 100 int (*sc_card_fun)(void *); 101 void *sc_card_arg; 102 void *sc_card_ih; 103 int sc_card_irq; 104 105 /* Card status change */ 106 int sc_irq; 107 void *sc_ih; 108 int sc_laststate; 109 }; 110 111 void it8368_init_socket(struct it8368e_softc*); 112 void it8368_attach_socket(struct it8368e_softc *); 113 int it8368_intr(void *); 114 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 115 struct pcmcia_mem_handle *); 116 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 117 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 118 struct pcmcia_mem_handle *, bus_addr_t *, int *); 119 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 120 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 121 bus_size_t, struct pcmcia_io_handle *); 122 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 123 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 124 struct pcmcia_io_handle *, int *); 125 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 126 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 127 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 128 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 129 struct pcmcia_function *, int, int (*) (void *), void *); 130 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 131 132 #ifdef IT8368DEBUG 133 void it8368_dump(struct it8368e_softc *); 134 #endif 135 136 static struct pcmcia_chip_functions it8368_functions = { 137 it8368_chip_mem_alloc, 138 it8368_chip_mem_free, 139 it8368_chip_mem_map, 140 it8368_chip_mem_unmap, 141 it8368_chip_io_alloc, 142 it8368_chip_io_free, 143 it8368_chip_io_map, 144 it8368_chip_io_unmap, 145 it8368_chip_intr_establish, 146 it8368_chip_intr_disestablish, 147 it8368_chip_socket_enable, 148 it8368_chip_socket_disable 149 }; 150 151 CFATTACH_DECL(it8368e, sizeof(struct it8368e_softc), 152 it8368e_match, it8368e_attach, NULL, NULL); 153 154 /* 155 * IT8368 configuration register is big-endian. 156 */ 157 static __inline__ u_int16_t it8368_reg_read(bus_space_tag_t, 158 bus_space_handle_t, int); 159 static __inline__ void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 160 int, u_int16_t); 161 162 #ifdef IT8368E_DESTRUCTIVE_CHECK 163 int it8368e_id_check(void *); 164 165 /* 166 * IT8368E don't have identification method. this is destructive check. 167 */ 168 int 169 it8368e_id_check(void *aux) 170 { 171 struct cs_attach_args *ca = aux; 172 tx_chipset_tag_t tc; 173 bus_space_tag_t csregt; 174 bus_space_handle_t csregh; 175 u_int16_t oreg, reg; 176 int match = 0; 177 178 tc = ca->ca_tc; 179 csregt = ca->ca_csreg.cstag; 180 181 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 182 0, &csregh); 183 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 184 oreg = reg; 185 dbg_bit_print(reg); 186 187 reg &= ~IT8368_CTRL_BYTESWAP; 188 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 189 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 190 if (reg & IT8368_CTRL_BYTESWAP) 191 goto nomatch; 192 193 reg |= IT8368_CTRL_BYTESWAP; 194 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 195 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 196 if (!(reg & IT8368_CTRL_BYTESWAP)) 197 goto nomatch; 198 199 match = 1; 200 nomatch: 201 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 202 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 203 204 return (match); 205 } 206 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 207 208 int 209 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 210 { 211 #ifdef IT8368E_DESTRUCTIVE_CHECK 212 return (it8368e_id_check(aux)); 213 #else 214 return (1); 215 #endif 216 } 217 218 void 219 it8368e_attach(struct device *parent, struct device *self, void *aux) 220 { 221 struct cs_attach_args *ca = aux; 222 struct it8368e_softc *sc = (void*)self; 223 tx_chipset_tag_t tc; 224 bus_space_tag_t csregt; 225 bus_space_handle_t csregh; 226 u_int16_t reg; 227 228 sc->sc_tc = tc = ca->ca_tc; 229 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 230 231 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 232 0, &sc->sc_csregh); 233 csregh = sc->sc_csregh; 234 sc->sc_csiot = ca->ca_csio.cstag; 235 sc->sc_csiobase = ca->ca_csio.csbase; 236 sc->sc_csiosize = ca->ca_csio.cssize; 237 238 #ifdef IT8368DEBUG 239 printf("\n\t[Windows CE setting]\n"); 240 it8368_dump(sc); /* print WindowsCE setting */ 241 #endif 242 /* LHA[14:13] <= HA[14:13] */ 243 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 244 reg &= ~IT8368_CTRL_ADDRSEL; 245 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 246 247 /* Set all MFIO direction as LHA[23:13] output pins */ 248 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 249 reg |= IT8368_MFIODIR_MASK; 250 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 251 252 /* Set all MFIO functions as LHA */ 253 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 254 reg &= ~IT8368_MFIOSEL_MASK; 255 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 256 257 /* Disable MFIO interrupt */ 258 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 259 reg &= ~IT8368_MFIOPOSINTEN_MASK; 260 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 261 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 262 reg &= ~IT8368_MFIONEGINTEN_MASK; 263 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 264 265 /* Port direction */ 266 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 267 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 268 IT8368_PIN_BCRDRST; 269 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 270 printf("\n"); 271 272 /* 273 * Separate I/O and attribute memory region 274 */ 275 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 276 277 reg |= IT8368_CTRL_FIXATTRIO; 278 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 279 280 if (IT8368_CTRL_FIXATTRIO & 281 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 282 sc->sc_fixattr = 1; 283 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 284 } else { 285 sc->sc_fixattr = 0; 286 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 287 } 288 289 sc->sc_csmemt = sc->sc_csiot; 290 sc->sc_csiosize /= 2; 291 sc->sc_csmemsize = sc->sc_csiosize; 292 sc->sc_csmembase = sc->sc_csiosize; 293 294 #ifdef IT8368DEBUG 295 it8368_dump(sc); 296 #endif 297 /* Enable card and interrupt driving. */ 298 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 299 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 300 if (sc->sc_fixattr) 301 reg |= IT8368_CTRL_FIXATTRIO; 302 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 303 304 sc->sc_irq = ca->ca_irq1; 305 sc->sc_card_irq = ca->ca_irq3; 306 307 it8368_attach_socket(sc); 308 } 309 310 __inline__ u_int16_t 311 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 312 { 313 u_int16_t val; 314 315 val = bus_space_read_2(t, h, ofs); 316 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 317 } 318 319 __inline__ void 320 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 321 { 322 u_int16_t val; 323 324 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 325 bus_space_write_2(t, h, ofs, val); 326 } 327 328 int 329 it8368_intr(void *arg) 330 { 331 struct it8368e_softc *sc = arg; 332 bus_space_tag_t csregt = sc->sc_csregt; 333 bus_space_handle_t csregh = sc->sc_csregh; 334 u_int16_t reg; 335 336 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 337 338 if (reg & IT8368_PIN_BCRDRDY) { 339 if (sc->sc_card_fun) { 340 /* clear interrupt */ 341 it8368_reg_write(csregt, csregh, 342 IT8368_GPIONEGINTSTAT_REG, 343 IT8368_PIN_BCRDRDY); 344 345 /* Dispatch card interrupt handler */ 346 (*sc->sc_card_fun)(sc->sc_card_arg); 347 } 348 } else if (reg & IT8368_PIN_CRDDET2) { 349 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 350 IT8368_PIN_CRDDET2); 351 printf("[CSC]\n"); 352 #ifdef IT8368DEBUG 353 it8368_dump(sc); 354 #endif 355 it8368_chip_socket_disable(sc); 356 } else { 357 #ifdef IT8368DEBUG 358 u_int16_t reg2; 359 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 360 printf("unknown it8368 interrupt: "); 361 dbg_bit_print(reg2); 362 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 363 reg); 364 #endif 365 } 366 367 return (0); 368 } 369 370 int 371 it8368_print(void *arg, const char *pnp) 372 { 373 if (pnp) 374 aprint_normal("pcmcia at %s", pnp); 375 376 return (UNCONF); 377 } 378 379 int 380 it8368_submatch(struct device *parent, struct cfdata *cf, void *aux) 381 { 382 383 return (config_match(parent, cf, aux)); 384 } 385 386 void 387 it8368_attach_socket(struct it8368e_softc *sc) 388 { 389 struct pcmciabus_attach_args paa; 390 391 paa.paa_busname = "pcmcia"; 392 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 393 paa.pch = (pcmcia_chipset_handle_t)sc; 394 paa.iobase = 0; 395 paa.iosize = sc->sc_csiosize; 396 397 if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 398 it8368_submatch))) { 399 400 it8368_init_socket(sc); 401 } 402 } 403 404 void 405 it8368_init_socket(struct it8368e_softc *sc) 406 { 407 bus_space_tag_t csregt = sc->sc_csregt; 408 bus_space_handle_t csregh = sc->sc_csregh; 409 u_int16_t reg; 410 411 /* 412 * set up the card to interrupt on card detect 413 */ 414 reg = IT8368_PIN_CRDDET2; /* CSC */ 415 /* enable negative edge */ 416 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 417 /* disable positive edge */ 418 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 419 420 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 421 IST_EDGE, IPL_BIO, it8368_intr, sc); 422 if (sc->sc_ih == NULL) { 423 printf("%s: can't establish interrupt\n", 424 sc->sc_dev.dv_xname); 425 return; 426 } 427 428 /* 429 * if there's a card there, then attach it. 430 */ 431 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 432 433 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 434 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 435 } else { 436 pcmcia_card_attach(sc->sc_pcmcia); 437 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 438 } 439 } 440 441 void * 442 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 443 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 444 { 445 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 446 bus_space_tag_t csregt = sc->sc_csregt; 447 bus_space_handle_t csregh = sc->sc_csregh; 448 u_int16_t reg; 449 450 if (sc->sc_card_fun) 451 panic("it8368_chip_intr_establish: " 452 "duplicate card interrupt handler."); 453 454 sc->sc_card_fun = ih_fun; 455 sc->sc_card_arg = ih_arg; 456 457 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 458 IST_EDGE, IPL_BIO, it8368_intr, 459 sc); 460 461 /* enable card interrupt */ 462 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 463 reg |= IT8368_PIN_BCRDRDY; 464 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 465 466 return (sc->sc_card_ih); 467 } 468 469 void 470 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 471 { 472 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 473 bus_space_tag_t csregt = sc->sc_csregt; 474 bus_space_handle_t csregh = sc->sc_csregh; 475 u_int16_t reg; 476 477 if (!sc->sc_card_fun) 478 panic("it8368_chip_intr_disestablish:" 479 "no handler established."); 480 assert(ih == sc->sc_card_ih); 481 482 sc->sc_card_fun = 0; 483 sc->sc_card_arg = 0; 484 485 /* disable card interrupt */ 486 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 487 reg &= ~IT8368_PIN_BCRDRDY; 488 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 489 490 tx_intr_disestablish(sc->sc_tc, ih); 491 } 492 493 int 494 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 495 struct pcmcia_mem_handle *pcmhp) 496 { 497 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 498 499 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 500 sc->sc_csmembase + sc->sc_csmemsize, size, 501 size, 0, 0, 0, &pcmhp->memh)) { 502 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 503 return (1); 504 } 505 506 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 507 pcmhp->memh -= sc->sc_csmembase; 508 509 pcmhp->memt = sc->sc_csmemt; 510 pcmhp->addr = pcmhp->memh; 511 pcmhp->size = size; 512 pcmhp->realsize = size; 513 514 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 515 (unsigned)pcmhp->memh, (unsigned)size)); 516 517 return (0); 518 } 519 520 void 521 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 522 struct pcmcia_mem_handle *pcmhp) 523 { 524 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 525 526 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 527 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 528 529 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 530 pcmhp->memh += sc->sc_csmembase; 531 532 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 533 } 534 535 int 536 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 537 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 538 bus_size_t *offsetp, int *windowp) 539 { 540 /* attribute mode */ 541 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 542 543 *offsetp = card_addr; 544 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 545 (unsigned)pcmhp->memh, (unsigned)size)); 546 547 return (0); 548 } 549 550 void 551 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 552 { 553 /* return to I/O mode */ 554 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 555 } 556 557 void 558 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 559 { 560 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 561 txreg_t reg32; 562 563 DPRINTF(("it8368_mode: change access space to ")); 564 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 565 width == IT8368_WIDTH_8 ? 8 : 16)); 566 567 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 568 569 if (io) { 570 if (width == IT8368_WIDTH_8) 571 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 572 else 573 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 574 } 575 576 if (!sc->sc_fixattr) { 577 if (io) 578 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 579 else 580 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 581 } 582 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 583 584 #ifdef IT8368DEBUG 585 if (sc->sc_fixattr) 586 return; /* No need to report BIU status */ 587 588 /* check BIU status */ 589 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 590 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 591 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 592 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 593 } else { 594 DPRINTF(("it8368_mode: atttribute space enabled\n")); 595 } 596 #endif /* IT8368DEBUG */ 597 } 598 599 int 600 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 601 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 602 { 603 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 604 605 if (start) { 606 if (bus_space_map(sc->sc_csiot, start, size, 0, 607 &pcihp->ioh)) { 608 return (1); 609 } 610 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 611 (unsigned)start, (unsigned)size)); 612 } else { 613 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 614 sc->sc_csiobase + sc->sc_csiosize, 615 size, align, 0, 0, &pcihp->addr, 616 &pcihp->ioh)) { 617 618 return (1); 619 } 620 pcihp->flags = PCMCIA_IO_ALLOCATED; 621 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 622 (unsigned)size, (unsigned)pcihp->addr)); 623 } 624 625 pcihp->iot = sc->sc_csiot; 626 pcihp->size = size; 627 628 return (0); 629 } 630 631 int 632 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 633 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 634 { 635 /* I/O mode */ 636 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 637 638 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 639 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 640 641 return (0); 642 } 643 644 void 645 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 646 struct pcmcia_io_handle *pcihp) 647 { 648 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 649 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 650 else 651 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 652 653 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 654 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 655 } 656 657 void 658 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 659 { 660 661 } 662 663 void 664 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 665 { 666 #ifndef WINCE_DEFAULT_SETTING 667 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 668 bus_space_tag_t csregt = sc->sc_csregt; 669 bus_space_handle_t csregh = sc->sc_csregh; 670 volatile u_int16_t reg; 671 672 /* Power off */ 673 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 674 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 675 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 676 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 677 delay(20000); 678 679 /* 680 * wait 300ms until power fails (Tpf). Then, wait 100ms since 681 * we are changing Vcc (Toff). 682 */ 683 delay((300 + 100) * 1000); 684 685 /* Supply Vcc */ 686 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 687 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 688 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 689 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 690 691 /* 692 * wait 100ms until power raise (Tpr) and 20ms to become 693 * stable (Tsu(Vcc)). 694 * 695 * some machines require some more time to be settled 696 * (300ms is added here). 697 */ 698 delay((100 + 20 + 300) * 1000); 699 700 /* Assert reset signal */ 701 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 702 reg |= IT8368_PIN_BCRDRST; 703 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 704 705 /* 706 * hold RESET at least 10us. 707 */ 708 delay(10); 709 710 /* deassert reset signal */ 711 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 712 reg &= ~IT8368_PIN_BCRDRST; 713 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 714 delay(20000); 715 716 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 717 #endif /* !WINCE_DEFAULT_SETTING */ 718 } 719 720 void 721 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 722 { 723 #ifndef WINCE_DEFAULT_SETTING 724 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 725 bus_space_tag_t csregt = sc->sc_csregt; 726 bus_space_handle_t csregh = sc->sc_csregh; 727 u_int16_t reg; 728 729 /* Power down */ 730 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 731 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 732 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 733 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 734 delay(20000); 735 736 /* 737 * wait 300ms until power fails (Tpf). 738 */ 739 delay(300 * 1000); 740 741 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 742 #endif /* !WINCE_DEFAULT_SETTING */ 743 } 744 745 #ifdef IT8368DEBUG 746 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 747 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 748 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 749 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 750 void 751 it8368_dump(struct it8368e_softc *sc) 752 { 753 bus_space_tag_t csregt = sc->sc_csregt; 754 bus_space_handle_t csregh = sc->sc_csregh; 755 756 printf("[GPIO]\n"); 757 PRINTGPIO(DIR); 758 PRINTGPIO(DATAIN); 759 PRINTGPIO(DATAOUT); 760 PRINTGPIO(POSINTEN); 761 PRINTGPIO(NEGINTEN); 762 PRINTGPIO(POSINTSTAT); 763 PRINTGPIO(NEGINTSTAT); 764 printf("[MFIO]\n"); 765 PRINTMFIO(SEL); 766 PRINTMFIO(DIR); 767 PRINTMFIO(DATAIN); 768 PRINTMFIO(DATAOUT); 769 PRINTMFIO(POSINTEN); 770 PRINTMFIO(NEGINTEN); 771 PRINTMFIO(POSINTSTAT); 772 PRINTMFIO(NEGINTSTAT); 773 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 774 "CTRL", DBG_BIT_PRINT_COUNT); 775 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 776 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 777 } 778 #endif /* IT8368DEBUG */ 779
Indexes created Tue Sep 30 11:09:46 GMT 2025