it8368.c revision 1.18
1 /* $NetBSD: it8368.c,v 1.18 2003/07/15 02:29:29 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: it8368.c,v 1.18 2003/07/15 02:29:29 lukem Exp $"); 41 42 #undef WINCE_DEFAULT_SETTING /* for debug */ 43 #undef IT8368DEBUG 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 49 #include <machine/bus.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <hpcmips/tx/tx39var.h> 56 #include <hpcmips/tx/txcsbusvar.h> 57 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 58 #include <hpcmips/dev/it8368var.h> 59 #include <hpcmips/dev/it8368reg.h> 60 61 #ifdef IT8368DEBUG 62 int it8368debug = 1; 63 #define DPRINTF(arg) if (it8368debug) printf arg; 64 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 65 #else 66 #define DPRINTF(arg) 67 #define DPRINTFN(n, arg) 68 #endif 69 70 int it8368e_match(struct device *, struct cfdata *, void *); 71 void it8368e_attach(struct device *, struct device *, void *); 72 int it8368_print(void *, const char *); 73 int it8368_submatch(struct device *, struct cfdata *, void *); 74 75 #define IT8368_LASTSTATE_PRESENT 0x0002 76 #define IT8368_LASTSTATE_HALF 0x0001 77 #define IT8368_LASTSTATE_EMPTY 0x0000 78 79 struct it8368e_softc { 80 struct device sc_dev; 81 struct device *sc_pcmcia; 82 tx_chipset_tag_t sc_tc; 83 84 /* Register space */ 85 bus_space_tag_t sc_csregt; 86 bus_space_handle_t sc_csregh; 87 /* I/O, attribute space */ 88 bus_space_tag_t sc_csiot; 89 bus_addr_t sc_csiobase; 90 bus_size_t sc_csiosize; 91 /* 92 * XXX theses means attribute memory. not memory space. 93 * memory space is 0x64000000. 94 */ 95 bus_space_tag_t sc_csmemt; 96 bus_addr_t sc_csmembase; 97 bus_size_t sc_csmemsize; 98 99 /* Separate I/O and attribute space mode */ 100 int sc_fixattr; 101 102 /* Card interrupt handler */ 103 int (*sc_card_fun)(void *); 104 void *sc_card_arg; 105 void *sc_card_ih; 106 int sc_card_irq; 107 108 /* Card status change */ 109 int sc_irq; 110 void *sc_ih; 111 int sc_laststate; 112 }; 113 114 void it8368_init_socket(struct it8368e_softc*); 115 void it8368_attach_socket(struct it8368e_softc *); 116 int it8368_intr(void *); 117 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 118 struct pcmcia_mem_handle *); 119 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 120 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 121 struct pcmcia_mem_handle *, bus_addr_t *, int *); 122 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 123 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 124 bus_size_t, struct pcmcia_io_handle *); 125 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 126 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 127 struct pcmcia_io_handle *, int *); 128 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 129 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 130 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 131 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 132 struct pcmcia_function *, int, int (*) (void *), void *); 133 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 134 135 #ifdef IT8368DEBUG 136 void it8368_dump(struct it8368e_softc *); 137 #endif 138 139 static struct pcmcia_chip_functions it8368_functions = { 140 it8368_chip_mem_alloc, 141 it8368_chip_mem_free, 142 it8368_chip_mem_map, 143 it8368_chip_mem_unmap, 144 it8368_chip_io_alloc, 145 it8368_chip_io_free, 146 it8368_chip_io_map, 147 it8368_chip_io_unmap, 148 it8368_chip_intr_establish, 149 it8368_chip_intr_disestablish, 150 it8368_chip_socket_enable, 151 it8368_chip_socket_disable 152 }; 153 154 CFATTACH_DECL(it8368e, sizeof(struct it8368e_softc), 155 it8368e_match, it8368e_attach, NULL, NULL); 156 157 /* 158 * IT8368 configuration register is big-endian. 159 */ 160 static __inline__ u_int16_t it8368_reg_read(bus_space_tag_t, 161 bus_space_handle_t, int); 162 static __inline__ void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 163 int, u_int16_t); 164 165 #ifdef IT8368E_DESTRUCTIVE_CHECK 166 int it8368e_id_check(void *); 167 168 /* 169 * IT8368E don't have identification method. this is destructive check. 170 */ 171 int 172 it8368e_id_check(void *aux) 173 { 174 struct cs_attach_args *ca = aux; 175 tx_chipset_tag_t tc; 176 bus_space_tag_t csregt; 177 bus_space_handle_t csregh; 178 u_int16_t oreg, reg; 179 int match = 0; 180 181 tc = ca->ca_tc; 182 csregt = ca->ca_csreg.cstag; 183 184 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 185 0, &csregh); 186 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 187 oreg = reg; 188 dbg_bit_print(reg); 189 190 reg &= ~IT8368_CTRL_BYTESWAP; 191 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 192 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 193 if (reg & IT8368_CTRL_BYTESWAP) 194 goto nomatch; 195 196 reg |= IT8368_CTRL_BYTESWAP; 197 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 198 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 199 if (!(reg & IT8368_CTRL_BYTESWAP)) 200 goto nomatch; 201 202 match = 1; 203 nomatch: 204 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 205 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 206 207 return (match); 208 } 209 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 210 211 int 212 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 213 { 214 #ifdef IT8368E_DESTRUCTIVE_CHECK 215 return (it8368e_id_check(aux)); 216 #else 217 return (1); 218 #endif 219 } 220 221 void 222 it8368e_attach(struct device *parent, struct device *self, void *aux) 223 { 224 struct cs_attach_args *ca = aux; 225 struct it8368e_softc *sc = (void*)self; 226 tx_chipset_tag_t tc; 227 bus_space_tag_t csregt; 228 bus_space_handle_t csregh; 229 u_int16_t reg; 230 231 sc->sc_tc = tc = ca->ca_tc; 232 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 233 234 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 235 0, &sc->sc_csregh); 236 csregh = sc->sc_csregh; 237 sc->sc_csiot = ca->ca_csio.cstag; 238 sc->sc_csiobase = ca->ca_csio.csbase; 239 sc->sc_csiosize = ca->ca_csio.cssize; 240 241 #ifdef IT8368DEBUG 242 printf("\n\t[Windows CE setting]\n"); 243 it8368_dump(sc); /* print WindowsCE setting */ 244 #endif 245 /* LHA[14:13] <= HA[14:13] */ 246 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 247 reg &= ~IT8368_CTRL_ADDRSEL; 248 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 249 250 /* Set all MFIO direction as LHA[23:13] output pins */ 251 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 252 reg |= IT8368_MFIODIR_MASK; 253 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 254 255 /* Set all MFIO functions as LHA */ 256 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 257 reg &= ~IT8368_MFIOSEL_MASK; 258 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 259 260 /* Disable MFIO interrupt */ 261 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 262 reg &= ~IT8368_MFIOPOSINTEN_MASK; 263 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 264 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 265 reg &= ~IT8368_MFIONEGINTEN_MASK; 266 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 267 268 /* Port direction */ 269 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 270 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 271 IT8368_PIN_BCRDRST; 272 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 273 printf("\n"); 274 275 /* 276 * Separate I/O and attribute memory region 277 */ 278 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 279 280 reg |= IT8368_CTRL_FIXATTRIO; 281 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 282 283 if (IT8368_CTRL_FIXATTRIO & 284 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 285 sc->sc_fixattr = 1; 286 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 287 } else { 288 sc->sc_fixattr = 0; 289 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 290 } 291 292 sc->sc_csmemt = sc->sc_csiot; 293 sc->sc_csiosize /= 2; 294 sc->sc_csmemsize = sc->sc_csiosize; 295 sc->sc_csmembase = sc->sc_csiosize; 296 297 #ifdef IT8368DEBUG 298 it8368_dump(sc); 299 #endif 300 /* Enable card and interrupt driving. */ 301 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 302 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 303 if (sc->sc_fixattr) 304 reg |= IT8368_CTRL_FIXATTRIO; 305 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 306 307 sc->sc_irq = ca->ca_irq1; 308 sc->sc_card_irq = ca->ca_irq3; 309 310 it8368_attach_socket(sc); 311 } 312 313 __inline__ u_int16_t 314 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 315 { 316 u_int16_t val; 317 318 val = bus_space_read_2(t, h, ofs); 319 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 320 } 321 322 __inline__ void 323 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 324 { 325 u_int16_t val; 326 327 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 328 bus_space_write_2(t, h, ofs, val); 329 } 330 331 int 332 it8368_intr(void *arg) 333 { 334 struct it8368e_softc *sc = arg; 335 bus_space_tag_t csregt = sc->sc_csregt; 336 bus_space_handle_t csregh = sc->sc_csregh; 337 u_int16_t reg; 338 339 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 340 341 if (reg & IT8368_PIN_BCRDRDY) { 342 if (sc->sc_card_fun) { 343 /* clear interrupt */ 344 it8368_reg_write(csregt, csregh, 345 IT8368_GPIONEGINTSTAT_REG, 346 IT8368_PIN_BCRDRDY); 347 348 /* Dispatch card interrupt handler */ 349 (*sc->sc_card_fun)(sc->sc_card_arg); 350 } 351 } else if (reg & IT8368_PIN_CRDDET2) { 352 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 353 IT8368_PIN_CRDDET2); 354 printf("[CSC]\n"); 355 #ifdef IT8368DEBUG 356 it8368_dump(sc); 357 #endif 358 it8368_chip_socket_disable(sc); 359 } else { 360 #ifdef IT8368DEBUG 361 u_int16_t reg2; 362 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 363 printf("unknown it8368 interrupt: "); 364 dbg_bit_print(reg2); 365 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 366 reg); 367 #endif 368 } 369 370 return (0); 371 } 372 373 int 374 it8368_print(void *arg, const char *pnp) 375 { 376 if (pnp) 377 aprint_normal("pcmcia at %s", pnp); 378 379 return (UNCONF); 380 } 381 382 int 383 it8368_submatch(struct device *parent, struct cfdata *cf, void *aux) 384 { 385 386 return (config_match(parent, cf, aux)); 387 } 388 389 void 390 it8368_attach_socket(struct it8368e_softc *sc) 391 { 392 struct pcmciabus_attach_args paa; 393 394 paa.paa_busname = "pcmcia"; 395 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 396 paa.pch = (pcmcia_chipset_handle_t)sc; 397 paa.iobase = 0; 398 paa.iosize = sc->sc_csiosize; 399 400 if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 401 it8368_submatch))) { 402 403 it8368_init_socket(sc); 404 } 405 } 406 407 void 408 it8368_init_socket(struct it8368e_softc *sc) 409 { 410 bus_space_tag_t csregt = sc->sc_csregt; 411 bus_space_handle_t csregh = sc->sc_csregh; 412 u_int16_t reg; 413 414 /* 415 * set up the card to interrupt on card detect 416 */ 417 reg = IT8368_PIN_CRDDET2; /* CSC */ 418 /* enable negative edge */ 419 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 420 /* disable positive edge */ 421 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 422 423 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 424 IST_EDGE, IPL_BIO, it8368_intr, sc); 425 if (sc->sc_ih == NULL) { 426 printf("%s: can't establish interrupt\n", 427 sc->sc_dev.dv_xname); 428 return; 429 } 430 431 /* 432 * if there's a card there, then attach it. 433 */ 434 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 435 436 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 437 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 438 } else { 439 pcmcia_card_attach(sc->sc_pcmcia); 440 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 441 } 442 } 443 444 void * 445 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 446 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 447 { 448 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 449 bus_space_tag_t csregt = sc->sc_csregt; 450 bus_space_handle_t csregh = sc->sc_csregh; 451 u_int16_t reg; 452 453 if (sc->sc_card_fun) 454 panic("it8368_chip_intr_establish: " 455 "duplicate card interrupt handler."); 456 457 sc->sc_card_fun = ih_fun; 458 sc->sc_card_arg = ih_arg; 459 460 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 461 IST_EDGE, IPL_BIO, it8368_intr, 462 sc); 463 464 /* enable card interrupt */ 465 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 466 reg |= IT8368_PIN_BCRDRDY; 467 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 468 469 return (sc->sc_card_ih); 470 } 471 472 void 473 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 474 { 475 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 476 bus_space_tag_t csregt = sc->sc_csregt; 477 bus_space_handle_t csregh = sc->sc_csregh; 478 u_int16_t reg; 479 480 if (!sc->sc_card_fun) 481 panic("it8368_chip_intr_disestablish:" 482 "no handler established."); 483 assert(ih == sc->sc_card_ih); 484 485 sc->sc_card_fun = 0; 486 sc->sc_card_arg = 0; 487 488 /* disable card interrupt */ 489 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 490 reg &= ~IT8368_PIN_BCRDRDY; 491 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 492 493 tx_intr_disestablish(sc->sc_tc, ih); 494 } 495 496 int 497 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 498 struct pcmcia_mem_handle *pcmhp) 499 { 500 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 501 502 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 503 sc->sc_csmembase + sc->sc_csmemsize, size, 504 size, 0, 0, 0, &pcmhp->memh)) { 505 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 506 return (1); 507 } 508 509 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 510 pcmhp->memh -= sc->sc_csmembase; 511 512 pcmhp->memt = sc->sc_csmemt; 513 pcmhp->addr = pcmhp->memh; 514 pcmhp->size = size; 515 pcmhp->realsize = size; 516 517 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 518 (unsigned)pcmhp->memh, (unsigned)size)); 519 520 return (0); 521 } 522 523 void 524 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 525 struct pcmcia_mem_handle *pcmhp) 526 { 527 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 528 529 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 530 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 531 532 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 533 pcmhp->memh += sc->sc_csmembase; 534 535 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 536 } 537 538 int 539 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 540 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 541 bus_size_t *offsetp, int *windowp) 542 { 543 /* attribute mode */ 544 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 545 546 *offsetp = card_addr; 547 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 548 (unsigned)pcmhp->memh, (unsigned)size)); 549 550 return (0); 551 } 552 553 void 554 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 555 { 556 /* return to I/O mode */ 557 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 558 } 559 560 void 561 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 562 { 563 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 564 txreg_t reg32; 565 566 DPRINTF(("it8368_mode: change access space to ")); 567 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 568 width == IT8368_WIDTH_8 ? 8 : 16)); 569 570 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 571 572 if (io) { 573 if (width == IT8368_WIDTH_8) 574 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 575 else 576 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 577 } 578 579 if (!sc->sc_fixattr) { 580 if (io) 581 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 582 else 583 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 584 } 585 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 586 587 #ifdef IT8368DEBUG 588 if (sc->sc_fixattr) 589 return; /* No need to report BIU status */ 590 591 /* check BIU status */ 592 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 593 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 594 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 595 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 596 } else { 597 DPRINTF(("it8368_mode: atttribute space enabled\n")); 598 } 599 #endif /* IT8368DEBUG */ 600 } 601 602 int 603 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 604 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 605 { 606 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 607 608 if (start) { 609 if (bus_space_map(sc->sc_csiot, start, size, 0, 610 &pcihp->ioh)) { 611 return (1); 612 } 613 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 614 (unsigned)start, (unsigned)size)); 615 } else { 616 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 617 sc->sc_csiobase + sc->sc_csiosize, 618 size, align, 0, 0, &pcihp->addr, 619 &pcihp->ioh)) { 620 621 return (1); 622 } 623 pcihp->flags = PCMCIA_IO_ALLOCATED; 624 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 625 (unsigned)size, (unsigned)pcihp->addr)); 626 } 627 628 pcihp->iot = sc->sc_csiot; 629 pcihp->size = size; 630 631 return (0); 632 } 633 634 int 635 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 636 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 637 { 638 /* I/O mode */ 639 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 640 641 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 642 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 643 644 return (0); 645 } 646 647 void 648 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 649 struct pcmcia_io_handle *pcihp) 650 { 651 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 652 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 653 else 654 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 655 656 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 657 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 658 } 659 660 void 661 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 662 { 663 664 } 665 666 void 667 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 668 { 669 #ifndef WINCE_DEFAULT_SETTING 670 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 671 bus_space_tag_t csregt = sc->sc_csregt; 672 bus_space_handle_t csregh = sc->sc_csregh; 673 volatile u_int16_t reg; 674 675 /* Power off */ 676 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 677 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 678 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 679 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 680 delay(20000); 681 682 /* 683 * wait 300ms until power fails (Tpf). Then, wait 100ms since 684 * we are changing Vcc (Toff). 685 */ 686 delay((300 + 100) * 1000); 687 688 /* Supply Vcc */ 689 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 690 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 691 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 692 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 693 694 /* 695 * wait 100ms until power raise (Tpr) and 20ms to become 696 * stable (Tsu(Vcc)). 697 * 698 * some machines require some more time to be settled 699 * (300ms is added here). 700 */ 701 delay((100 + 20 + 300) * 1000); 702 703 /* Assert reset signal */ 704 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 705 reg |= IT8368_PIN_BCRDRST; 706 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 707 708 /* 709 * hold RESET at least 10us. 710 */ 711 delay(10); 712 713 /* deassert reset signal */ 714 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 715 reg &= ~IT8368_PIN_BCRDRST; 716 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 717 delay(20000); 718 719 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 720 #endif /* !WINCE_DEFAULT_SETTING */ 721 } 722 723 void 724 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 725 { 726 #ifndef WINCE_DEFAULT_SETTING 727 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 728 bus_space_tag_t csregt = sc->sc_csregt; 729 bus_space_handle_t csregh = sc->sc_csregh; 730 u_int16_t reg; 731 732 /* Power down */ 733 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 734 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 735 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 736 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 737 delay(20000); 738 739 /* 740 * wait 300ms until power fails (Tpf). 741 */ 742 delay(300 * 1000); 743 744 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 745 #endif /* !WINCE_DEFAULT_SETTING */ 746 } 747 748 #ifdef IT8368DEBUG 749 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 750 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 751 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 752 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 753 void 754 it8368_dump(struct it8368e_softc *sc) 755 { 756 bus_space_tag_t csregt = sc->sc_csregt; 757 bus_space_handle_t csregh = sc->sc_csregh; 758 759 printf("[GPIO]\n"); 760 PRINTGPIO(DIR); 761 PRINTGPIO(DATAIN); 762 PRINTGPIO(DATAOUT); 763 PRINTGPIO(POSINTEN); 764 PRINTGPIO(NEGINTEN); 765 PRINTGPIO(POSINTSTAT); 766 PRINTGPIO(NEGINTSTAT); 767 printf("[MFIO]\n"); 768 PRINTMFIO(SEL); 769 PRINTMFIO(DIR); 770 PRINTMFIO(DATAIN); 771 PRINTMFIO(DATAOUT); 772 PRINTMFIO(POSINTEN); 773 PRINTMFIO(NEGINTEN); 774 PRINTMFIO(POSINTSTAT); 775 PRINTMFIO(NEGINTSTAT); 776 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 777 "CTRL", DBG_BIT_PRINT_COUNT); 778 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 779 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 780 } 781 #endif /* IT8368DEBUG */ 782
Indexes created Tue Sep 30 11:09:46 GMT 2025