it8368.c revision 1.22
1 /* $NetBSD: it8368.c,v 1.22 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: it8368.c,v 1.22 2008/04/28 20:23:21 martin Exp $"); 34 35 #undef WINCE_DEFAULT_SETTING /* for debug */ 36 #undef IT8368DEBUG 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/pcmcia/pcmciareg.h> 45 #include <dev/pcmcia/pcmciavar.h> 46 #include <dev/pcmcia/pcmciachip.h> 47 48 #include <hpcmips/tx/tx39var.h> 49 #include <hpcmips/tx/txcsbusvar.h> 50 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 51 #include <hpcmips/dev/it8368var.h> 52 #include <hpcmips/dev/it8368reg.h> 53 54 #ifdef IT8368DEBUG 55 int it8368debug = 1; 56 #define DPRINTF(arg) if (it8368debug) printf arg; 57 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #define DPRINTFN(n, arg) 61 #endif 62 63 int it8368e_match(struct device *, struct cfdata *, void *); 64 void it8368e_attach(struct device *, struct device *, void *); 65 int it8368_print(void *, const char *); 66 67 #define IT8368_LASTSTATE_PRESENT 0x0002 68 #define IT8368_LASTSTATE_HALF 0x0001 69 #define IT8368_LASTSTATE_EMPTY 0x0000 70 71 struct it8368e_softc { 72 struct device sc_dev; 73 struct device *sc_pcmcia; 74 tx_chipset_tag_t sc_tc; 75 76 /* Register space */ 77 bus_space_tag_t sc_csregt; 78 bus_space_handle_t sc_csregh; 79 /* I/O, attribute space */ 80 bus_space_tag_t sc_csiot; 81 bus_addr_t sc_csiobase; 82 bus_size_t sc_csiosize; 83 /* 84 * XXX theses means attribute memory. not memory space. 85 * memory space is 0x64000000. 86 */ 87 bus_space_tag_t sc_csmemt; 88 bus_addr_t sc_csmembase; 89 bus_size_t sc_csmemsize; 90 91 /* Separate I/O and attribute space mode */ 92 int sc_fixattr; 93 94 /* Card interrupt handler */ 95 int (*sc_card_fun)(void *); 96 void *sc_card_arg; 97 void *sc_card_ih; 98 int sc_card_irq; 99 100 /* Card status change */ 101 int sc_irq; 102 void *sc_ih; 103 int sc_laststate; 104 }; 105 106 void it8368_init_socket(struct it8368e_softc*); 107 void it8368_attach_socket(struct it8368e_softc *); 108 int it8368_intr(void *); 109 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 110 struct pcmcia_mem_handle *); 111 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 112 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 113 struct pcmcia_mem_handle *, bus_addr_t *, int *); 114 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 115 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 116 bus_size_t, struct pcmcia_io_handle *); 117 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 118 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 119 struct pcmcia_io_handle *, int *); 120 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 121 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 122 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 123 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 124 struct pcmcia_function *, int, int (*) (void *), void *); 125 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 126 127 #ifdef IT8368DEBUG 128 void it8368_dump(struct it8368e_softc *); 129 #endif 130 131 static struct pcmcia_chip_functions it8368_functions = { 132 it8368_chip_mem_alloc, 133 it8368_chip_mem_free, 134 it8368_chip_mem_map, 135 it8368_chip_mem_unmap, 136 it8368_chip_io_alloc, 137 it8368_chip_io_free, 138 it8368_chip_io_map, 139 it8368_chip_io_unmap, 140 it8368_chip_intr_establish, 141 it8368_chip_intr_disestablish, 142 it8368_chip_socket_enable, 143 it8368_chip_socket_disable 144 }; 145 146 CFATTACH_DECL(it8368e, sizeof(struct it8368e_softc), 147 it8368e_match, it8368e_attach, NULL, NULL); 148 149 /* 150 * IT8368 configuration register is big-endian. 151 */ 152 static inline u_int16_t it8368_reg_read(bus_space_tag_t, 153 bus_space_handle_t, int); 154 static inline void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 155 int, u_int16_t); 156 157 #ifdef IT8368E_DESTRUCTIVE_CHECK 158 int it8368e_id_check(void *); 159 160 /* 161 * IT8368E don't have identification method. this is destructive check. 162 */ 163 int 164 it8368e_id_check(void *aux) 165 { 166 struct cs_attach_args *ca = aux; 167 tx_chipset_tag_t tc; 168 bus_space_tag_t csregt; 169 bus_space_handle_t csregh; 170 u_int16_t oreg, reg; 171 int match = 0; 172 173 tc = ca->ca_tc; 174 csregt = ca->ca_csreg.cstag; 175 176 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 177 0, &csregh); 178 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 179 oreg = reg; 180 dbg_bit_print(reg); 181 182 reg &= ~IT8368_CTRL_BYTESWAP; 183 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 184 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 185 if (reg & IT8368_CTRL_BYTESWAP) 186 goto nomatch; 187 188 reg |= IT8368_CTRL_BYTESWAP; 189 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 190 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 191 if (!(reg & IT8368_CTRL_BYTESWAP)) 192 goto nomatch; 193 194 match = 1; 195 nomatch: 196 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 197 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 198 199 return (match); 200 } 201 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 202 203 int 204 it8368e_match(struct device *parent, struct cfdata *cf, void *aux) 205 { 206 #ifdef IT8368E_DESTRUCTIVE_CHECK 207 return (it8368e_id_check(aux)); 208 #else 209 return (1); 210 #endif 211 } 212 213 void 214 it8368e_attach(struct device *parent, struct device *self, void *aux) 215 { 216 struct cs_attach_args *ca = aux; 217 struct it8368e_softc *sc = (void*)self; 218 tx_chipset_tag_t tc; 219 bus_space_tag_t csregt; 220 bus_space_handle_t csregh; 221 u_int16_t reg; 222 223 sc->sc_tc = tc = ca->ca_tc; 224 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 225 226 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 227 0, &sc->sc_csregh); 228 csregh = sc->sc_csregh; 229 sc->sc_csiot = ca->ca_csio.cstag; 230 sc->sc_csiobase = ca->ca_csio.csbase; 231 sc->sc_csiosize = ca->ca_csio.cssize; 232 233 #ifdef IT8368DEBUG 234 printf("\n\t[Windows CE setting]\n"); 235 it8368_dump(sc); /* print WindowsCE setting */ 236 #endif 237 /* LHA[14:13] <= HA[14:13] */ 238 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 239 reg &= ~IT8368_CTRL_ADDRSEL; 240 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 241 242 /* Set all MFIO direction as LHA[23:13] output pins */ 243 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 244 reg |= IT8368_MFIODIR_MASK; 245 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 246 247 /* Set all MFIO functions as LHA */ 248 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 249 reg &= ~IT8368_MFIOSEL_MASK; 250 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 251 252 /* Disable MFIO interrupt */ 253 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 254 reg &= ~IT8368_MFIOPOSINTEN_MASK; 255 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 256 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 257 reg &= ~IT8368_MFIONEGINTEN_MASK; 258 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 259 260 /* Port direction */ 261 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 262 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 263 IT8368_PIN_BCRDRST; 264 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 265 printf("\n"); 266 267 /* 268 * Separate I/O and attribute memory region 269 */ 270 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 271 272 reg |= IT8368_CTRL_FIXATTRIO; 273 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 274 275 if (IT8368_CTRL_FIXATTRIO & 276 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 277 sc->sc_fixattr = 1; 278 printf("%s: fix attr mode\n", sc->sc_dev.dv_xname); 279 } else { 280 sc->sc_fixattr = 0; 281 printf("%s: legacy attr mode\n", sc->sc_dev.dv_xname); 282 } 283 284 sc->sc_csmemt = sc->sc_csiot; 285 sc->sc_csiosize /= 2; 286 sc->sc_csmemsize = sc->sc_csiosize; 287 sc->sc_csmembase = sc->sc_csiosize; 288 289 #ifdef IT8368DEBUG 290 it8368_dump(sc); 291 #endif 292 /* Enable card and interrupt driving. */ 293 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 294 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 295 if (sc->sc_fixattr) 296 reg |= IT8368_CTRL_FIXATTRIO; 297 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 298 299 sc->sc_irq = ca->ca_irq1; 300 sc->sc_card_irq = ca->ca_irq3; 301 302 it8368_attach_socket(sc); 303 } 304 305 inline u_int16_t 306 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 307 { 308 u_int16_t val; 309 310 val = bus_space_read_2(t, h, ofs); 311 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 312 } 313 314 inline void 315 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 316 { 317 u_int16_t val; 318 319 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 320 bus_space_write_2(t, h, ofs, val); 321 } 322 323 int 324 it8368_intr(void *arg) 325 { 326 struct it8368e_softc *sc = arg; 327 bus_space_tag_t csregt = sc->sc_csregt; 328 bus_space_handle_t csregh = sc->sc_csregh; 329 u_int16_t reg; 330 331 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 332 333 if (reg & IT8368_PIN_BCRDRDY) { 334 if (sc->sc_card_fun) { 335 /* clear interrupt */ 336 it8368_reg_write(csregt, csregh, 337 IT8368_GPIONEGINTSTAT_REG, 338 IT8368_PIN_BCRDRDY); 339 340 /* Dispatch card interrupt handler */ 341 (*sc->sc_card_fun)(sc->sc_card_arg); 342 } 343 } else if (reg & IT8368_PIN_CRDDET2) { 344 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 345 IT8368_PIN_CRDDET2); 346 printf("[CSC]\n"); 347 #ifdef IT8368DEBUG 348 it8368_dump(sc); 349 #endif 350 it8368_chip_socket_disable(sc); 351 } else { 352 #ifdef IT8368DEBUG 353 u_int16_t reg2; 354 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 355 printf("unknown it8368 interrupt: "); 356 dbg_bit_print(reg2); 357 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 358 reg); 359 #endif 360 } 361 362 return (0); 363 } 364 365 int 366 it8368_print(void *arg, const char *pnp) 367 { 368 if (pnp) 369 aprint_normal("pcmcia at %s", pnp); 370 371 return (UNCONF); 372 } 373 374 void 375 it8368_attach_socket(struct it8368e_softc *sc) 376 { 377 struct pcmciabus_attach_args paa; 378 379 paa.paa_busname = "pcmcia"; 380 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 381 paa.pch = (pcmcia_chipset_handle_t)sc; 382 paa.iobase = 0; 383 paa.iosize = sc->sc_csiosize; 384 385 if ((sc->sc_pcmcia = config_found_ia((void*)sc, "pcmciabus", &paa, 386 it8368_print))) { 387 it8368_init_socket(sc); 388 } 389 } 390 391 void 392 it8368_init_socket(struct it8368e_softc *sc) 393 { 394 bus_space_tag_t csregt = sc->sc_csregt; 395 bus_space_handle_t csregh = sc->sc_csregh; 396 u_int16_t reg; 397 398 /* 399 * set up the card to interrupt on card detect 400 */ 401 reg = IT8368_PIN_CRDDET2; /* CSC */ 402 /* enable negative edge */ 403 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 404 /* disable positive edge */ 405 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 406 407 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 408 IST_EDGE, IPL_BIO, it8368_intr, sc); 409 if (sc->sc_ih == NULL) { 410 printf("%s: can't establish interrupt\n", 411 sc->sc_dev.dv_xname); 412 return; 413 } 414 415 /* 416 * if there's a card there, then attach it. 417 */ 418 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 419 420 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 421 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 422 } else { 423 pcmcia_card_attach(sc->sc_pcmcia); 424 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 425 } 426 } 427 428 void * 429 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 430 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 431 { 432 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 433 bus_space_tag_t csregt = sc->sc_csregt; 434 bus_space_handle_t csregh = sc->sc_csregh; 435 u_int16_t reg; 436 437 if (sc->sc_card_fun) 438 panic("it8368_chip_intr_establish: " 439 "duplicate card interrupt handler."); 440 441 sc->sc_card_fun = ih_fun; 442 sc->sc_card_arg = ih_arg; 443 444 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 445 IST_EDGE, IPL_BIO, it8368_intr, 446 sc); 447 448 /* enable card interrupt */ 449 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 450 reg |= IT8368_PIN_BCRDRDY; 451 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 452 453 return (sc->sc_card_ih); 454 } 455 456 void 457 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 458 { 459 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 460 bus_space_tag_t csregt = sc->sc_csregt; 461 bus_space_handle_t csregh = sc->sc_csregh; 462 u_int16_t reg; 463 464 if (!sc->sc_card_fun) 465 panic("it8368_chip_intr_disestablish:" 466 "no handler established."); 467 assert(ih == sc->sc_card_ih); 468 469 sc->sc_card_fun = 0; 470 sc->sc_card_arg = 0; 471 472 /* disable card interrupt */ 473 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 474 reg &= ~IT8368_PIN_BCRDRDY; 475 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 476 477 tx_intr_disestablish(sc->sc_tc, ih); 478 } 479 480 int 481 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 482 struct pcmcia_mem_handle *pcmhp) 483 { 484 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 485 486 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 487 sc->sc_csmembase + sc->sc_csmemsize, size, 488 size, 0, 0, 0, &pcmhp->memh)) { 489 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 490 return (1); 491 } 492 493 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 494 pcmhp->memh -= sc->sc_csmembase; 495 496 pcmhp->memt = sc->sc_csmemt; 497 pcmhp->addr = pcmhp->memh; 498 pcmhp->size = size; 499 pcmhp->realsize = size; 500 501 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 502 (unsigned)pcmhp->memh, (unsigned)size)); 503 504 return (0); 505 } 506 507 void 508 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 509 struct pcmcia_mem_handle *pcmhp) 510 { 511 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 512 513 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 514 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 515 516 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 517 pcmhp->memh += sc->sc_csmembase; 518 519 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 520 } 521 522 int 523 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 524 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 525 bus_size_t *offsetp, int *windowp) 526 { 527 /* attribute mode */ 528 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 529 530 *offsetp = card_addr; 531 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 532 (unsigned)pcmhp->memh, (unsigned)size)); 533 534 return (0); 535 } 536 537 void 538 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 539 { 540 /* return to I/O mode */ 541 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 542 } 543 544 void 545 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 546 { 547 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 548 txreg_t reg32; 549 550 DPRINTF(("it8368_mode: change access space to ")); 551 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 552 width == IT8368_WIDTH_8 ? 8 : 16)); 553 554 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 555 556 if (io) { 557 if (width == IT8368_WIDTH_8) 558 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 559 else 560 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 561 } 562 563 if (!sc->sc_fixattr) { 564 if (io) 565 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 566 else 567 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 568 } 569 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 570 571 #ifdef IT8368DEBUG 572 if (sc->sc_fixattr) 573 return; /* No need to report BIU status */ 574 575 /* check BIU status */ 576 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 577 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 578 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 579 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 580 } else { 581 DPRINTF(("it8368_mode: atttribute space enabled\n")); 582 } 583 #endif /* IT8368DEBUG */ 584 } 585 586 int 587 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 588 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 589 { 590 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 591 592 if (start) { 593 if (bus_space_map(sc->sc_csiot, start, size, 0, 594 &pcihp->ioh)) { 595 return (1); 596 } 597 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 598 (unsigned)start, (unsigned)size)); 599 } else { 600 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 601 sc->sc_csiobase + sc->sc_csiosize, 602 size, align, 0, 0, &pcihp->addr, 603 &pcihp->ioh)) { 604 605 return (1); 606 } 607 pcihp->flags = PCMCIA_IO_ALLOCATED; 608 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 609 (unsigned)size, (unsigned)pcihp->addr)); 610 } 611 612 pcihp->iot = sc->sc_csiot; 613 pcihp->size = size; 614 615 return (0); 616 } 617 618 int 619 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 620 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 621 { 622 /* I/O mode */ 623 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 624 625 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 626 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 627 628 return (0); 629 } 630 631 void 632 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 633 struct pcmcia_io_handle *pcihp) 634 { 635 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 636 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 637 else 638 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 639 640 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 641 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 642 } 643 644 void 645 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 646 { 647 648 } 649 650 void 651 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 652 { 653 #ifndef WINCE_DEFAULT_SETTING 654 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 655 bus_space_tag_t csregt = sc->sc_csregt; 656 bus_space_handle_t csregh = sc->sc_csregh; 657 volatile u_int16_t reg; 658 659 /* Power off */ 660 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 661 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 662 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 663 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 664 delay(20000); 665 666 /* 667 * wait 300ms until power fails (Tpf). Then, wait 100ms since 668 * we are changing Vcc (Toff). 669 */ 670 delay((300 + 100) * 1000); 671 672 /* Supply Vcc */ 673 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 674 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 675 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 676 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 677 678 /* 679 * wait 100ms until power raise (Tpr) and 20ms to become 680 * stable (Tsu(Vcc)). 681 * 682 * some machines require some more time to be settled 683 * (300ms is added here). 684 */ 685 delay((100 + 20 + 300) * 1000); 686 687 /* Assert reset signal */ 688 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 689 reg |= IT8368_PIN_BCRDRST; 690 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 691 692 /* 693 * hold RESET at least 10us. 694 */ 695 delay(10); 696 697 /* deassert reset signal */ 698 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 699 reg &= ~IT8368_PIN_BCRDRST; 700 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 701 delay(20000); 702 703 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 704 #endif /* !WINCE_DEFAULT_SETTING */ 705 } 706 707 void 708 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 709 { 710 #ifndef WINCE_DEFAULT_SETTING 711 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 712 bus_space_tag_t csregt = sc->sc_csregt; 713 bus_space_handle_t csregh = sc->sc_csregh; 714 u_int16_t reg; 715 716 /* Power down */ 717 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 718 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 719 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 720 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 721 delay(20000); 722 723 /* 724 * wait 300ms until power fails (Tpf). 725 */ 726 delay(300 * 1000); 727 728 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 729 #endif /* !WINCE_DEFAULT_SETTING */ 730 } 731 732 #ifdef IT8368DEBUG 733 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 734 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 735 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 736 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 737 void 738 it8368_dump(struct it8368e_softc *sc) 739 { 740 bus_space_tag_t csregt = sc->sc_csregt; 741 bus_space_handle_t csregh = sc->sc_csregh; 742 743 printf("[GPIO]\n"); 744 PRINTGPIO(DIR); 745 PRINTGPIO(DATAIN); 746 PRINTGPIO(DATAOUT); 747 PRINTGPIO(POSINTEN); 748 PRINTGPIO(NEGINTEN); 749 PRINTGPIO(POSINTSTAT); 750 PRINTGPIO(NEGINTSTAT); 751 printf("[MFIO]\n"); 752 PRINTMFIO(SEL); 753 PRINTMFIO(DIR); 754 PRINTMFIO(DATAIN); 755 PRINTMFIO(DATAOUT); 756 PRINTMFIO(POSINTEN); 757 PRINTMFIO(NEGINTEN); 758 PRINTMFIO(POSINTSTAT); 759 PRINTMFIO(NEGINTSTAT); 760 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 761 "CTRL", DBG_BIT_PRINT_COUNT); 762 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 763 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 764 } 765 #endif /* IT8368DEBUG */ 766
Indexes created Sat Oct 11 08:10:02 GMT 2025