it8368.c revision 1.24.52.1
1 /* $NetBSD: it8368.c,v 1.24.52.1 2021/03/23 07:14:48 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: it8368.c,v 1.24.52.1 2021/03/23 07:14:48 thorpej Exp $"); 34 35 #undef WINCE_DEFAULT_SETTING /* for debug */ 36 #undef IT8368DEBUG 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 42 #include <machine/bus.h> 43 44 #include <dev/pcmcia/pcmciareg.h> 45 #include <dev/pcmcia/pcmciavar.h> 46 #include <dev/pcmcia/pcmciachip.h> 47 48 #include <hpcmips/tx/tx39var.h> 49 #include <hpcmips/tx/txcsbusvar.h> 50 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */ 51 #include <hpcmips/dev/it8368var.h> 52 #include <hpcmips/dev/it8368reg.h> 53 54 #ifdef IT8368DEBUG 55 int it8368debug = 1; 56 #define DPRINTF(arg) if (it8368debug) printf arg; 57 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #define DPRINTFN(n, arg) 61 #endif 62 63 int it8368e_match(device_t, cfdata_t, void *); 64 void it8368e_attach(device_t, device_t, void *); 65 int it8368_print(void *, const char *); 66 67 #define IT8368_LASTSTATE_PRESENT 0x0002 68 #define IT8368_LASTSTATE_HALF 0x0001 69 #define IT8368_LASTSTATE_EMPTY 0x0000 70 71 struct it8368e_softc { 72 device_t sc_dev; 73 device_t sc_pcmcia; 74 tx_chipset_tag_t sc_tc; 75 76 /* Register space */ 77 bus_space_tag_t sc_csregt; 78 bus_space_handle_t sc_csregh; 79 /* I/O, attribute space */ 80 bus_space_tag_t sc_csiot; 81 bus_addr_t sc_csiobase; 82 bus_size_t sc_csiosize; 83 /* 84 * XXX theses means attribute memory. not memory space. 85 * memory space is 0x64000000. 86 */ 87 bus_space_tag_t sc_csmemt; 88 bus_addr_t sc_csmembase; 89 bus_size_t sc_csmemsize; 90 91 /* Separate I/O and attribute space mode */ 92 int sc_fixattr; 93 94 /* Card interrupt handler */ 95 int (*sc_card_fun)(void *); 96 void *sc_card_arg; 97 void *sc_card_ih; 98 int sc_card_irq; 99 100 /* Card status change */ 101 int sc_irq; 102 void *sc_ih; 103 int sc_laststate; 104 }; 105 106 void it8368_init_socket(struct it8368e_softc*); 107 void it8368_attach_socket(struct it8368e_softc *); 108 int it8368_intr(void *); 109 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 110 struct pcmcia_mem_handle *); 111 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *); 112 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t, 113 struct pcmcia_mem_handle *, bus_addr_t *, int *); 114 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int); 115 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 116 bus_size_t, struct pcmcia_io_handle *); 117 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 118 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t, 119 struct pcmcia_io_handle *, int *); 120 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int); 121 void it8368_chip_socket_enable(pcmcia_chipset_handle_t); 122 void it8368_chip_socket_disable(pcmcia_chipset_handle_t); 123 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t, 124 struct pcmcia_function *, int, int (*) (void *), void *); 125 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *); 126 127 #ifdef IT8368DEBUG 128 void it8368_dump(struct it8368e_softc *); 129 #endif 130 131 static struct pcmcia_chip_functions it8368_functions = { 132 it8368_chip_mem_alloc, 133 it8368_chip_mem_free, 134 it8368_chip_mem_map, 135 it8368_chip_mem_unmap, 136 it8368_chip_io_alloc, 137 it8368_chip_io_free, 138 it8368_chip_io_map, 139 it8368_chip_io_unmap, 140 it8368_chip_intr_establish, 141 it8368_chip_intr_disestablish, 142 it8368_chip_socket_enable, 143 it8368_chip_socket_disable 144 }; 145 146 CFATTACH_DECL_NEW(it8368e, sizeof(struct it8368e_softc), 147 it8368e_match, it8368e_attach, NULL, NULL); 148 149 /* 150 * IT8368 configuration register is big-endian. 151 */ 152 static inline u_int16_t it8368_reg_read(bus_space_tag_t, 153 bus_space_handle_t, int); 154 static inline void it8368_reg_write(bus_space_tag_t, bus_space_handle_t, 155 int, u_int16_t); 156 157 #ifdef IT8368E_DESTRUCTIVE_CHECK 158 int it8368e_id_check(void *); 159 160 /* 161 * IT8368E don't have identification method. this is destructive check. 162 */ 163 int 164 it8368e_id_check(void *aux) 165 { 166 struct cs_attach_args *ca = aux; 167 tx_chipset_tag_t tc; 168 bus_space_tag_t csregt; 169 bus_space_handle_t csregh; 170 u_int16_t oreg, reg; 171 int match = 0; 172 173 tc = ca->ca_tc; 174 csregt = ca->ca_csreg.cstag; 175 176 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 177 0, &csregh); 178 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 179 oreg = reg; 180 dbg_bit_print(reg); 181 182 reg &= ~IT8368_CTRL_BYTESWAP; 183 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 184 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 185 if (reg & IT8368_CTRL_BYTESWAP) 186 goto nomatch; 187 188 reg |= IT8368_CTRL_BYTESWAP; 189 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 190 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 191 if (!(reg & IT8368_CTRL_BYTESWAP)) 192 goto nomatch; 193 194 match = 1; 195 nomatch: 196 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg); 197 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize); 198 199 return (match); 200 } 201 #endif /* IT8368E_DESTRUCTIVE_CHECK */ 202 203 int 204 it8368e_match(device_t parent, cfdata_t cf, void *aux) 205 { 206 #ifdef IT8368E_DESTRUCTIVE_CHECK 207 return (it8368e_id_check(aux)); 208 #else 209 return (1); 210 #endif 211 } 212 213 void 214 it8368e_attach(device_t parent, device_t self, void *aux) 215 { 216 struct cs_attach_args *ca = aux; 217 struct it8368e_softc *sc = device_private(self); 218 tx_chipset_tag_t tc; 219 bus_space_tag_t csregt; 220 bus_space_handle_t csregh; 221 u_int16_t reg; 222 223 sc->sc_dev = self; 224 sc->sc_tc = tc = ca->ca_tc; 225 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 226 227 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 228 0, &sc->sc_csregh); 229 csregh = sc->sc_csregh; 230 sc->sc_csiot = ca->ca_csio.cstag; 231 sc->sc_csiobase = ca->ca_csio.csbase; 232 sc->sc_csiosize = ca->ca_csio.cssize; 233 234 #ifdef IT8368DEBUG 235 printf("\n\t[Windows CE setting]\n"); 236 it8368_dump(sc); /* print WindowsCE setting */ 237 #endif 238 /* LHA[14:13] <= HA[14:13] */ 239 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 240 reg &= ~IT8368_CTRL_ADDRSEL; 241 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 242 243 /* Set all MFIO direction as LHA[23:13] output pins */ 244 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 245 reg |= IT8368_MFIODIR_MASK; 246 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 247 248 /* Set all MFIO functions as LHA */ 249 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 250 reg &= ~IT8368_MFIOSEL_MASK; 251 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 252 253 /* Disable MFIO interrupt */ 254 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 255 reg &= ~IT8368_MFIOPOSINTEN_MASK; 256 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 257 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 258 reg &= ~IT8368_MFIONEGINTEN_MASK; 259 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 260 261 /* Port direction */ 262 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 263 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 264 IT8368_PIN_BCRDRST; 265 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 266 printf("\n"); 267 268 /* 269 * Separate I/O and attribute memory region 270 */ 271 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 272 273 reg |= IT8368_CTRL_FIXATTRIO; 274 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 275 276 if (IT8368_CTRL_FIXATTRIO & 277 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) { 278 sc->sc_fixattr = 1; 279 printf("%s: fix attr mode\n", device_xname(sc->sc_dev)); 280 } else { 281 sc->sc_fixattr = 0; 282 printf("%s: legacy attr mode\n", device_xname(sc->sc_dev)); 283 } 284 285 sc->sc_csmemt = sc->sc_csiot; 286 sc->sc_csiosize /= 2; 287 sc->sc_csmemsize = sc->sc_csiosize; 288 sc->sc_csmembase = sc->sc_csiosize; 289 290 #ifdef IT8368DEBUG 291 it8368_dump(sc); 292 #endif 293 /* Enable card and interrupt driving. */ 294 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 295 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 296 if (sc->sc_fixattr) 297 reg |= IT8368_CTRL_FIXATTRIO; 298 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 299 300 sc->sc_irq = ca->ca_irq1; 301 sc->sc_card_irq = ca->ca_irq3; 302 303 it8368_attach_socket(sc); 304 } 305 306 inline u_int16_t 307 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs) 308 { 309 u_int16_t val; 310 311 val = bus_space_read_2(t, h, ofs); 312 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00))); 313 } 314 315 inline void 316 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v) 317 { 318 u_int16_t val; 319 320 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 321 bus_space_write_2(t, h, ofs, val); 322 } 323 324 int 325 it8368_intr(void *arg) 326 { 327 struct it8368e_softc *sc = arg; 328 bus_space_tag_t csregt = sc->sc_csregt; 329 bus_space_handle_t csregh = sc->sc_csregh; 330 u_int16_t reg; 331 332 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 333 334 if (reg & IT8368_PIN_BCRDRDY) { 335 if (sc->sc_card_fun) { 336 /* clear interrupt */ 337 it8368_reg_write(csregt, csregh, 338 IT8368_GPIONEGINTSTAT_REG, 339 IT8368_PIN_BCRDRDY); 340 341 /* Dispatch card interrupt handler */ 342 (*sc->sc_card_fun)(sc->sc_card_arg); 343 } 344 } else if (reg & IT8368_PIN_CRDDET2) { 345 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 346 IT8368_PIN_CRDDET2); 347 printf("[CSC]\n"); 348 #ifdef IT8368DEBUG 349 it8368_dump(sc); 350 #endif 351 it8368_chip_socket_disable(sc); 352 } else { 353 #ifdef IT8368DEBUG 354 u_int16_t reg2; 355 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2); 356 printf("unknown it8368 interrupt: "); 357 dbg_bit_print(reg2); 358 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 359 reg); 360 #endif 361 } 362 363 return (0); 364 } 365 366 int 367 it8368_print(void *arg, const char *pnp) 368 { 369 if (pnp) 370 aprint_normal("pcmcia at %s", pnp); 371 372 return (UNCONF); 373 } 374 375 void 376 it8368_attach_socket(struct it8368e_softc *sc) 377 { 378 struct pcmciabus_attach_args paa; 379 380 paa.paa_busname = "pcmcia"; 381 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 382 paa.pch = (pcmcia_chipset_handle_t)sc; 383 384 if ((sc->sc_pcmcia = config_found(sc, &paa, it8368_print, CFARG_EOL))) { 385 it8368_init_socket(sc); 386 } 387 } 388 389 void 390 it8368_init_socket(struct it8368e_softc *sc) 391 { 392 bus_space_tag_t csregt = sc->sc_csregt; 393 bus_space_handle_t csregh = sc->sc_csregh; 394 u_int16_t reg; 395 396 /* 397 * set up the card to interrupt on card detect 398 */ 399 reg = IT8368_PIN_CRDDET2; /* CSC */ 400 /* enable negative edge */ 401 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 402 /* disable positive edge */ 403 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 404 405 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 406 IST_EDGE, IPL_BIO, it8368_intr, sc); 407 if (sc->sc_ih == NULL) { 408 printf("%s: can't establish interrupt\n", 409 device_xname(sc->sc_dev)); 410 return; 411 } 412 413 /* 414 * if there's a card there, then attach it. 415 */ 416 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 417 418 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 419 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 420 } else { 421 pcmcia_card_attach(sc->sc_pcmcia); 422 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 423 } 424 } 425 426 void * 427 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch, 428 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg) 429 { 430 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 431 bus_space_tag_t csregt = sc->sc_csregt; 432 bus_space_handle_t csregh = sc->sc_csregh; 433 u_int16_t reg; 434 435 if (sc->sc_card_fun) 436 panic("it8368_chip_intr_establish: " 437 "duplicate card interrupt handler."); 438 439 sc->sc_card_fun = ih_fun; 440 sc->sc_card_arg = ih_arg; 441 442 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 443 IST_EDGE, IPL_BIO, it8368_intr, 444 sc); 445 446 /* enable card interrupt */ 447 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 448 reg |= IT8368_PIN_BCRDRDY; 449 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 450 451 return (sc->sc_card_ih); 452 } 453 454 void 455 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 456 { 457 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 458 bus_space_tag_t csregt = sc->sc_csregt; 459 bus_space_handle_t csregh = sc->sc_csregh; 460 u_int16_t reg; 461 462 if (!sc->sc_card_fun) 463 panic("it8368_chip_intr_disestablish:" 464 "no handler established."); 465 assert(ih == sc->sc_card_ih); 466 467 sc->sc_card_fun = 0; 468 sc->sc_card_arg = 0; 469 470 /* disable card interrupt */ 471 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 472 reg &= ~IT8368_PIN_BCRDRDY; 473 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 474 475 tx_intr_disestablish(sc->sc_tc, ih); 476 } 477 478 int 479 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 480 struct pcmcia_mem_handle *pcmhp) 481 { 482 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 483 484 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase, 485 sc->sc_csmembase + sc->sc_csmemsize, size, 486 size, 0, 0, 0, &pcmhp->memh)) { 487 DPRINTF(("it8368_chip_mem_alloc: failed\n")); 488 return (1); 489 } 490 491 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 492 pcmhp->memh -= sc->sc_csmembase; 493 494 pcmhp->memt = sc->sc_csmemt; 495 pcmhp->addr = pcmhp->memh; 496 pcmhp->size = size; 497 pcmhp->realsize = size; 498 499 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n", 500 (unsigned)pcmhp->memh, (unsigned)size)); 501 502 return (0); 503 } 504 505 void 506 it8368_chip_mem_free(pcmcia_chipset_handle_t pch, 507 struct pcmcia_mem_handle *pcmhp) 508 { 509 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 510 511 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n", 512 (unsigned)pcmhp->memh, (unsigned)pcmhp->size)); 513 514 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */ 515 pcmhp->memh += sc->sc_csmembase; 516 517 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 518 } 519 520 int 521 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 522 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 523 bus_size_t *offsetp, int *windowp) 524 { 525 /* attribute mode */ 526 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16); 527 528 *offsetp = card_addr; 529 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", 530 (unsigned)pcmhp->memh, (unsigned)size)); 531 532 return (0); 533 } 534 535 void 536 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 537 { 538 /* return to I/O mode */ 539 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 540 } 541 542 void 543 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width) 544 { 545 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 546 txreg_t reg32; 547 548 DPRINTF(("it8368_mode: change access space to ")); 549 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n", 550 width == IT8368_WIDTH_8 ? 8 : 16)); 551 552 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 553 554 if (io) { 555 if (width == IT8368_WIDTH_8) 556 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 557 else 558 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 559 } 560 561 if (!sc->sc_fixattr) { 562 if (io) 563 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 564 else 565 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 566 } 567 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 568 569 #ifdef IT8368DEBUG 570 if (sc->sc_fixattr) 571 return; /* No need to report BIU status */ 572 573 /* check BIU status */ 574 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 575 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) { 576 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n", 577 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16)); 578 } else { 579 DPRINTF(("it8368_mode: atttribute space enabled\n")); 580 } 581 #endif /* IT8368DEBUG */ 582 } 583 584 int 585 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 586 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 587 { 588 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 589 590 if (start) { 591 if (bus_space_map(sc->sc_csiot, start, size, 0, 592 &pcihp->ioh)) { 593 return (1); 594 } 595 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 596 (unsigned)start, (unsigned)size)); 597 } else { 598 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 599 sc->sc_csiobase + sc->sc_csiosize, 600 size, align, 0, 0, &pcihp->addr, 601 &pcihp->ioh)) { 602 603 return (1); 604 } 605 pcihp->flags = PCMCIA_IO_ALLOCATED; 606 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 607 (unsigned)size, (unsigned)pcihp->addr)); 608 } 609 610 pcihp->iot = sc->sc_csiot; 611 pcihp->size = size; 612 613 return (0); 614 } 615 616 int 617 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 618 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 619 { 620 /* I/O mode */ 621 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16); 622 623 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", 624 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size)); 625 626 return (0); 627 } 628 629 void 630 it8368_chip_io_free(pcmcia_chipset_handle_t pch, 631 struct pcmcia_io_handle *pcihp) 632 { 633 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 634 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 635 else 636 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 637 638 DPRINTF(("it8368_chip_io_free %#x+%#x\n", 639 (unsigned)pcihp->ioh, (unsigned)pcihp->size)); 640 } 641 642 void 643 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 644 { 645 646 } 647 648 void 649 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch) 650 { 651 #ifndef WINCE_DEFAULT_SETTING 652 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 653 bus_space_tag_t csregt = sc->sc_csregt; 654 bus_space_handle_t csregh = sc->sc_csregh; 655 volatile u_int16_t reg; 656 657 /* Power off */ 658 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 659 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 660 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 661 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 662 delay(20000); 663 664 /* 665 * wait 300ms until power fails (Tpf). Then, wait 100ms since 666 * we are changing Vcc (Toff). 667 */ 668 delay((300 + 100) * 1000); 669 670 /* Supply Vcc */ 671 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 672 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 673 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 674 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 675 676 /* 677 * wait 100ms until power raise (Tpr) and 20ms to become 678 * stable (Tsu(Vcc)). 679 * 680 * some machines require some more time to be settled 681 * (300ms is added here). 682 */ 683 delay((100 + 20 + 300) * 1000); 684 685 /* Assert reset signal */ 686 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 687 reg |= IT8368_PIN_BCRDRST; 688 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 689 690 /* 691 * hold RESET at least 10us. 692 */ 693 delay(10); 694 695 /* deassert reset signal */ 696 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 697 reg &= ~IT8368_PIN_BCRDRST; 698 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 699 delay(20000); 700 701 DPRINTF(("it8368_chip_socket_enable: socket enabled\n")); 702 #endif /* !WINCE_DEFAULT_SETTING */ 703 } 704 705 void 706 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch) 707 { 708 #ifndef WINCE_DEFAULT_SETTING 709 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 710 bus_space_tag_t csregt = sc->sc_csregt; 711 bus_space_handle_t csregh = sc->sc_csregh; 712 u_int16_t reg; 713 714 /* Power down */ 715 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 716 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 717 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 718 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 719 delay(20000); 720 721 /* 722 * wait 300ms until power fails (Tpf). 723 */ 724 delay(300 * 1000); 725 726 DPRINTF(("it8368_chip_socket_disable: socket disabled\n")); 727 #endif /* !WINCE_DEFAULT_SETTING */ 728 } 729 730 #ifdef IT8368DEBUG 731 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 732 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT) 733 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \ 734 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT) 735 void 736 it8368_dump(struct it8368e_softc *sc) 737 { 738 bus_space_tag_t csregt = sc->sc_csregt; 739 bus_space_handle_t csregh = sc->sc_csregh; 740 741 printf("[GPIO]\n"); 742 PRINTGPIO(DIR); 743 PRINTGPIO(DATAIN); 744 PRINTGPIO(DATAOUT); 745 PRINTGPIO(POSINTEN); 746 PRINTGPIO(NEGINTEN); 747 PRINTGPIO(POSINTSTAT); 748 PRINTGPIO(NEGINTSTAT); 749 printf("[MFIO]\n"); 750 PRINTMFIO(SEL); 751 PRINTMFIO(DIR); 752 PRINTMFIO(DATAIN); 753 PRINTMFIO(DATAOUT); 754 PRINTMFIO(POSINTEN); 755 PRINTMFIO(NEGINTEN); 756 PRINTMFIO(POSINTSTAT); 757 PRINTMFIO(NEGINTSTAT); 758 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 759 "CTRL", DBG_BIT_PRINT_COUNT); 760 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 761 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT); 762 } 763 #endif /* IT8368DEBUG */ 764
Indexes created Sat Oct 11 08:10:02 GMT 2025