it8368.c revision 1.4
1 /* $NetBSD: it8368.c,v 1.4 1999/12/30 16:50:43 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include "opt_tx39_debug.h" 29 #include "opt_it8368debug.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 37 #include <dev/pcmcia/pcmciareg.h> 38 #include <dev/pcmcia/pcmciavar.h> 39 #include <dev/pcmcia/pcmciachip.h> 40 41 #include <hpcmips/tx/tx39var.h> 42 #include <hpcmips/tx/txcsbusvar.h> 43 #include <hpcmips/dev/it8368reg.h> 44 45 #ifdef IT8368DEBUG 46 #define DPRINTF(arg) printf arg 47 #else 48 #define DPRINTF(arg) 49 #endif 50 51 int it8368e_match __P((struct device*, struct cfdata*, void*)); 52 void it8368e_attach __P((struct device*, struct device*, void*)); 53 int it8368_print __P((void*, const char*)); 54 int it8368_submatch __P((struct device*, struct cfdata*, void*)); 55 56 #define IT8368_LASTSTATE_PRESENT 0x0002 57 #define IT8368_LASTSTATE_HALF 0x0001 58 #define IT8368_LASTSTATE_EMPTY 0x0000 59 60 struct it8368e_softc { 61 struct device sc_dev; 62 struct device *sc_pcmcia; 63 tx_chipset_tag_t sc_tc; 64 65 /* Register space */ 66 bus_space_tag_t sc_csregt; 67 bus_space_handle_t sc_csregh; 68 /* I/O, attribute space */ 69 bus_space_tag_t sc_csiot; 70 bus_space_handle_t sc_csioh; 71 bus_addr_t sc_csiobase; 72 bus_size_t sc_csiosize; 73 /* 74 * XXX theses means attribute memory. not memory space. 75 * memory space is 0x64000000. 76 */ 77 bus_space_tag_t sc_csmemt; 78 bus_space_handle_t sc_csmemh; 79 bus_addr_t sc_csmembase; 80 bus_size_t sc_csmemsize; 81 82 /* Separate I/O and attribute space mode */ 83 int sc_fixattr; 84 85 /* Card interrupt handler */ 86 int (*sc_card_fun) __P((void*)); 87 void *sc_card_arg; 88 void *sc_card_ih; 89 int sc_card_irq; 90 91 /* Card status change */ 92 int sc_irq; 93 void *sc_ih; 94 int sc_laststate; 95 }; 96 97 void it8368_init_socket __P((struct it8368e_softc*)); 98 void it8368_attach_socket __P((struct it8368e_softc*)); 99 void it8368_access __P((struct it8368e_softc*, int, int)); 100 int it8368_intr __P((void*)); 101 102 void it8368_dump __P((struct it8368e_softc*)); 103 104 int it8368_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t, 105 struct pcmcia_mem_handle*)); 106 void it8368_chip_mem_free __P((pcmcia_chipset_handle_t, 107 struct pcmcia_mem_handle*)); 108 int it8368_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 109 bus_size_t, struct pcmcia_mem_handle*, 110 bus_addr_t*, int*)); 111 void it8368_chip_mem_unmap __P((pcmcia_chipset_handle_t, int)); 112 int it8368_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t, 113 bus_size_t, bus_size_t, 114 struct pcmcia_io_handle*)); 115 void it8368_chip_io_free __P((pcmcia_chipset_handle_t, 116 struct pcmcia_io_handle*)); 117 int it8368_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t, 118 bus_size_t, struct pcmcia_io_handle*, 119 int*)); 120 void it8368_chip_io_unmap __P((pcmcia_chipset_handle_t, int)); 121 void it8368_chip_socket_enable __P((pcmcia_chipset_handle_t)); 122 void it8368_chip_socket_disable __P((pcmcia_chipset_handle_t)); 123 void *it8368_chip_intr_establish __P((pcmcia_chipset_handle_t, 124 struct pcmcia_function*, int, 125 int (*) (void*), void*)); 126 void it8368_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void*)); 127 128 static struct pcmcia_chip_functions it8368_functions = { 129 it8368_chip_mem_alloc, 130 it8368_chip_mem_free, 131 it8368_chip_mem_map, 132 it8368_chip_mem_unmap, 133 it8368_chip_io_alloc, 134 it8368_chip_io_free, 135 it8368_chip_io_map, 136 it8368_chip_io_unmap, 137 it8368_chip_intr_establish, 138 it8368_chip_intr_disestablish, 139 it8368_chip_socket_enable, 140 it8368_chip_socket_disable 141 }; 142 143 struct cfattach it8368e_ca = { 144 sizeof(struct it8368e_softc), it8368e_match, it8368e_attach 145 }; 146 147 /* 148 * IT8368 configuration register is big-endian. 149 */ 150 __inline u_int16_t it8368_reg_read __P((bus_space_tag_t, 151 bus_space_handle_t, int)); 152 __inline void it8368_reg_write __P((bus_space_tag_t, 153 bus_space_handle_t, int, 154 u_int16_t)); 155 156 #define PRINTGPIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 157 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, 1) 158 #define PRINTMFIO(m) __bitdisp(it8368_reg_read(csregt, csregh, \ 159 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, 1) 160 161 int 162 it8368e_match(parent, cf, aux) 163 struct device *parent; 164 struct cfdata *cf; 165 void *aux; 166 { 167 return 1; 168 } 169 170 void 171 it8368e_attach(parent, self, aux) 172 struct device *parent; 173 struct device *self; 174 void *aux; 175 { 176 struct cs_attach_args *ca = aux; 177 struct it8368e_softc *sc = (void*)self; 178 tx_chipset_tag_t tc; 179 bus_space_tag_t csregt; 180 bus_space_handle_t csregh; 181 u_int16_t reg; 182 183 sc->sc_tc = tc = ca->ca_tc; 184 sc->sc_csregt = csregt = ca->ca_csreg.cstag; 185 186 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize, 187 0, &sc->sc_csregh); 188 csregh = sc->sc_csregh; 189 sc->sc_csiot = ca->ca_csio.cstag; 190 sc->sc_csiobase = ca->ca_csio.csbase; 191 sc->sc_csiosize = ca->ca_csio.cssize; 192 193 #ifdef IT8368DEBUG 194 printf("\n\t[Windows CE setting]\n"); 195 it8368_dump(sc); /* print WindowsCE setting */ 196 #endif 197 /* LHA[14:13] <= HA[14:13] */ 198 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 199 reg &= ~IT8368_CTRL_ADDRSEL; 200 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 201 202 /* Set all MFIO direction as LHA[23:13] output pins */ 203 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG); 204 reg |= IT8368_MFIODIR_MASK; 205 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg); 206 207 /* Set all MFIO functions as LHA */ 208 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG); 209 reg &= ~IT8368_MFIOSEL_MASK; 210 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg); 211 212 /* Disable MFIO interrupt */ 213 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG); 214 reg &= ~IT8368_MFIOPOSINTEN_MASK; 215 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg); 216 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG); 217 reg &= ~IT8368_MFIONEGINTEN_MASK; 218 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg); 219 220 /* Port direction */ 221 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 | 222 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 | 223 IT8368_PIN_BCRDRST; 224 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg); 225 226 /* 227 * Separate I/O and attribute memory region 228 */ 229 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 230 reg |= IT8368_CTRL_FIXATTRIO; 231 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 232 233 if (IT8368_CTRL_FIXATTRIO & it8368_reg_read(csregt, csregh, 234 IT8368_CTRL_REG)) { 235 sc->sc_fixattr = 1; 236 printf(":fix attr mode"); 237 sc->sc_csmemt = sc->sc_csiot; 238 sc->sc_csiosize /= 2; 239 sc->sc_csmemsize = sc->sc_csiosize; 240 sc->sc_csmembase = sc->sc_csiosize; 241 } else { 242 printf(":legacy attr mode"); 243 sc->sc_fixattr = 0; 244 sc->sc_csmemt = sc->sc_csiot; 245 sc->sc_csmemh = sc->sc_csmemh; 246 sc->sc_csmembase = sc->sc_csiobase; 247 sc->sc_csmemsize = sc->sc_csiosize; 248 } 249 it8368_dump(sc); 250 251 /* Enable card and interrupt driving. */ 252 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG); 253 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN); 254 if (sc->sc_fixattr) 255 reg |= IT8368_CTRL_FIXATTRIO; 256 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg); 257 258 sc->sc_irq = ca->ca_irq1; 259 sc->sc_card_irq = ca->ca_irq3; 260 261 printf("\n"); 262 263 it8368_attach_socket(sc); 264 } 265 266 __inline u_int16_t 267 it8368_reg_read(t, h, ofs) 268 bus_space_tag_t t; 269 bus_space_handle_t h; 270 int ofs; 271 { 272 u_int16_t val; 273 274 val = bus_space_read_2(t, h, ofs); 275 return 0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00)); 276 } 277 278 __inline void 279 it8368_reg_write(t, h, ofs, v) 280 bus_space_tag_t t; 281 bus_space_handle_t h; 282 int ofs; 283 u_int16_t v; 284 { 285 u_int16_t val; 286 287 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00)); 288 bus_space_write_2(t, h, ofs, val); 289 } 290 291 int 292 it8368_intr(arg) 293 void *arg; 294 { 295 struct it8368e_softc *sc = arg; 296 bus_space_tag_t csregt = sc->sc_csregt; 297 bus_space_handle_t csregh = sc->sc_csregh; 298 u_int16_t reg; 299 300 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG); 301 302 if (reg & IT8368_PIN_BCRDRDY) { 303 if (sc->sc_card_fun) { 304 /* clear interrupt */ 305 it8368_reg_write(csregt, csregh, 306 IT8368_GPIONEGINTSTAT_REG, 307 IT8368_PIN_BCRDRDY); 308 309 /* Dispatch card interrupt handler */ 310 (*sc->sc_card_fun)(sc->sc_card_arg); 311 } 312 } else if (reg & IT8368_PIN_CRDDET2) { 313 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG, 314 IT8368_PIN_CRDDET2); 315 printf("[CSC]\n"); 316 it8368_dump(sc); 317 it8368_chip_socket_disable(sc); 318 } else { 319 printf("unknown it8368 interrupt\n"); 320 it8368_dump(sc); 321 } 322 323 return 0; 324 } 325 326 int 327 it8368_print(arg, pnp) 328 void *arg; 329 const char *pnp; 330 { 331 if (pnp) 332 printf("pcmcia at %s", pnp); 333 334 return UNCONF; 335 } 336 337 int 338 it8368_submatch(parent, cf, aux) 339 struct device *parent; 340 struct cfdata *cf; 341 void *aux; 342 { 343 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 344 } 345 346 void 347 it8368_attach_socket(sc) 348 struct it8368e_softc *sc; 349 { 350 struct pcmciabus_attach_args paa; 351 352 paa.paa_busname = "pcmcia"; 353 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions; 354 paa.pch = (pcmcia_chipset_handle_t)sc; 355 paa.iobase = 0; /* I don't use them */ 356 paa.iosize = 0; 357 358 if ((sc->sc_pcmcia = config_found_sm((void*)sc, &paa, it8368_print, 359 it8368_submatch))) { 360 361 it8368_init_socket(sc); 362 } 363 } 364 365 void 366 it8368_init_socket(sc) 367 struct it8368e_softc *sc; 368 { 369 bus_space_tag_t csregt = sc->sc_csregt; 370 bus_space_handle_t csregh = sc->sc_csregh; 371 u_int16_t reg; 372 373 /* 374 * set up the card to interrupt on card detect 375 */ 376 reg = IT8368_PIN_CRDDET2; /* CSC */ 377 /* enable negative edge */ 378 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 379 /* disable positive edge */ 380 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0); 381 382 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq, 383 IST_EDGE, IPL_BIO, it8368_intr, sc); 384 if (sc->sc_ih == NULL) { 385 printf("%s: can't establish interrupt\n", 386 sc->sc_dev.dv_xname); 387 return; 388 } 389 390 /* 391 * if there's a card there, then attach it. 392 */ 393 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG); 394 395 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) { 396 sc->sc_laststate = IT8368_LASTSTATE_EMPTY; 397 } else { 398 pcmcia_card_attach(sc->sc_pcmcia); 399 sc->sc_laststate = IT8368_LASTSTATE_PRESENT; 400 } 401 } 402 403 void * 404 it8368_chip_intr_establish(pch, pf, ipl, ih_fun, ih_arg) 405 pcmcia_chipset_handle_t pch; 406 struct pcmcia_function *pf; 407 int ipl; 408 int (*ih_fun) __P((void *)); 409 void *ih_arg; 410 { 411 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 412 bus_space_tag_t csregt = sc->sc_csregt; 413 bus_space_handle_t csregh = sc->sc_csregh; 414 u_int16_t reg; 415 416 if (sc->sc_card_fun) 417 panic("it8368_chip_intr_establish: " 418 "duplicate card interrupt handler."); 419 420 sc->sc_card_fun = ih_fun; 421 sc->sc_card_arg = ih_arg; 422 423 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq, 424 IST_EDGE, IPL_BIO, it8368_intr, 425 sc); 426 427 /* enable card interrupt */ 428 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 429 reg |= IT8368_PIN_BCRDRDY; 430 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 431 432 return sc->sc_card_ih; 433 } 434 435 void 436 it8368_chip_intr_disestablish(pch, ih) 437 pcmcia_chipset_handle_t pch; 438 void *ih; 439 { 440 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 441 bus_space_tag_t csregt = sc->sc_csregt; 442 bus_space_handle_t csregh = sc->sc_csregh; 443 u_int16_t reg; 444 445 if (!sc->sc_card_fun) 446 panic("it8368_chip_intr_disestablish:" 447 "no handler established."); 448 assert(ih == sc->sc_card_ih); 449 450 sc->sc_card_fun = 0; 451 sc->sc_card_arg = 0; 452 453 /* disable card interrupt */ 454 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG); 455 reg &= ~IT8368_PIN_BCRDRDY; 456 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg); 457 458 tx_intr_disestablish(sc->sc_tc, ih); 459 } 460 461 int 462 it8368_chip_mem_alloc(pch, size, pcmhp) 463 pcmcia_chipset_handle_t pch; 464 bus_size_t size; 465 struct pcmcia_mem_handle *pcmhp; 466 { 467 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 468 it8368_access(sc, 0, 0); 469 470 pcmhp->memt = sc->sc_csmemt; 471 472 if (bus_space_map(sc->sc_csmemt, sc->sc_csmembase, size, 0, 473 &pcmhp->memh)) { 474 return 1; 475 } 476 477 pcmhp->addr = pcmhp->memh; 478 pcmhp->size = size; 479 pcmhp->realsize = size; 480 481 DPRINTF(("it8368_chip_mem_alloc %#x+%#x\n", pcmhp->memh, size)); 482 483 return 0; 484 } 485 486 void 487 it8368_chip_mem_free(pch, pcmhp) 488 pcmcia_chipset_handle_t pch; 489 struct pcmcia_mem_handle *pcmhp; 490 { 491 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size); 492 } 493 494 int 495 it8368_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 496 pcmcia_chipset_handle_t pch; 497 int kind; 498 bus_addr_t card_addr; 499 bus_size_t size; 500 struct pcmcia_mem_handle *pcmhp; 501 bus_addr_t *offsetp; 502 int *windowp; 503 { 504 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 505 506 it8368_access(sc, 0, 0); 507 508 *offsetp = card_addr; 509 DPRINTF(("it8368_chip_mem_map %#x+%#x\n", pcmhp->memh, size)); 510 511 return 0; 512 } 513 514 void 515 it8368_chip_mem_unmap(pch, window) 516 pcmcia_chipset_handle_t pch; 517 int window; 518 { 519 } 520 521 void 522 it8368_access(sc, io, width) 523 struct it8368e_softc *sc; 524 int io; 525 int width; 526 { 527 #if not_required_yet 528 txreg_t reg32; 529 530 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 531 if (io && width == 1) { 532 reg32 |= TX39_MEMCONFIG3_PORT8SEL; 533 } else { 534 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL; 535 } 536 if (!sc->sc_fixattr) { 537 if (io) { 538 reg32 |= TX39_MEMCONFIG3_CARD1IOEN; 539 } else { 540 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN; 541 } 542 } 543 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32); 544 545 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG); 546 if (!(reg32 & TX39_MEMCONFIG3_CARD1IOEN)) 547 printf("CARDIOEN failed\n"); 548 if (!(reg32 & TX39_MEMCONFIG3_PORT8SEL)) 549 printf("PORT8SEL failed\n"); 550 551 delay(20); 552 #endif 553 } 554 555 int 556 it8368_chip_io_alloc(pch, start, size, align, pcihp) 557 pcmcia_chipset_handle_t pch; 558 bus_addr_t start; 559 bus_size_t size; 560 bus_size_t align; 561 struct pcmcia_io_handle *pcihp; 562 { 563 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 564 565 it8368_access(sc, 1, 0); 566 567 if (start) { 568 if (bus_space_map(sc->sc_csiot, start, size, 0, 569 &pcihp->ioh)) { 570 return 1; 571 } 572 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n", 573 start, size)); 574 } else { 575 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase, 576 sc->sc_csiobase + sc->sc_csiosize, 577 size, align, 0, 0, &pcihp->addr, 578 &pcihp->ioh)) { 579 580 return 1; 581 } 582 pcihp->flags = PCMCIA_IO_ALLOCATED; 583 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n", 584 size, pcihp->addr)); 585 } 586 587 pcihp->iot = sc->sc_csiot; 588 pcihp->size = size; 589 590 return 0; 591 } 592 593 int 594 it8368_chip_io_map(pch, width, offset, size, pcihp, windowp) 595 pcmcia_chipset_handle_t pch; 596 int width; 597 bus_addr_t offset; 598 bus_size_t size; 599 struct pcmcia_io_handle *pcihp; 600 int *windowp; 601 { 602 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 603 604 it8368_access(sc, 1, 0); 605 606 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n", pcihp->ioh, offset, 607 size)); 608 609 return 0; 610 } 611 612 void 613 it8368_chip_io_free(pch, pcihp) 614 pcmcia_chipset_handle_t pch; 615 struct pcmcia_io_handle *pcihp; 616 { 617 if (pcihp->flags & PCMCIA_IO_ALLOCATED) { 618 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 619 } else { 620 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 621 } 622 DPRINTF(("it8368_chip_io_free %#x+%#x\n", pcihp->ioh, pcihp->size)); 623 } 624 625 void 626 it8368_chip_io_unmap(pch, window) 627 pcmcia_chipset_handle_t pch; 628 int window; 629 { 630 } 631 632 void 633 it8368_chip_socket_enable(pch) 634 pcmcia_chipset_handle_t pch; 635 { 636 struct it8368e_softc *sc = (struct it8368e_softc*)pch; 637 bus_space_tag_t csregt = sc->sc_csregt; 638 bus_space_handle_t csregh = sc->sc_csregh; 639 volatile u_int16_t reg; 640 641 /* Power off */ 642 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 643 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 644 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 645 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 646 delay(20000); 647 648 /* 649 * wait 300ms until power fails (Tpf). Then, wait 100ms since 650 * we are changing Vcc (Toff). 651 */ 652 delay((300 + 100) * 1000); 653 654 /* Supply Vcc */ 655 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 656 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 657 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */ 658 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 659 660 /* 661 * wait 100ms until power raise (Tpr) and 20ms to become 662 * stable (Tsu(Vcc)). 663 * 664 * some machines require some more time to be settled 665 * (300ms is added here). 666 */ 667 delay((100 + 20 + 300) * 1000); 668 669 /* Assert reset signal */ 670 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 671 reg |= IT8368_PIN_BCRDRST; 672 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 673 674 /* 675 * hold RESET at least 10us. 676 */ 677 delay(10); 678 679 /* Dessert reset signal */ 680 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 681 reg &= ~IT8368_PIN_BCRDRST; 682 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 683 delay(20000); 684 685 DPRINTF(("socket enabled\n")); 686 } 687 688 void 689 it8368_chip_socket_disable(pch) 690 pcmcia_chipset_handle_t pch; 691 { 692 struct it8368e_softc *sc = (struct it8368e_softc*) pch; 693 bus_space_tag_t csregt = sc->sc_csregt; 694 bus_space_handle_t csregh = sc->sc_csregh; 695 u_int16_t reg; 696 697 /* Power down */ 698 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG); 699 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK); 700 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V); 701 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg); 702 delay(20000); 703 704 /* 705 * wait 300ms until power fails (Tpf). 706 */ 707 delay(300 * 1000); 708 709 DPRINTF(("socket disabled\n")); 710 } 711 712 void 713 it8368_dump(sc) 714 struct it8368e_softc *sc; 715 { 716 #ifdef IT8368DEBUG 717 bus_space_tag_t csregt = sc->sc_csregt; 718 bus_space_handle_t csregh = sc->sc_csregh; 719 720 printf("[GPIO]\n"); 721 PRINTGPIO(DIR); 722 PRINTGPIO(DATAIN); 723 PRINTGPIO(DATAOUT); 724 PRINTGPIO(POSINTEN); 725 PRINTGPIO(NEGINTEN); 726 PRINTGPIO(POSINTSTAT); 727 PRINTGPIO(NEGINTSTAT); 728 printf("[MFIO]\n"); 729 PRINTMFIO(SEL); 730 PRINTMFIO(DIR); 731 PRINTMFIO(DATAIN); 732 PRINTMFIO(DATAOUT); 733 PRINTMFIO(POSINTEN); 734 PRINTMFIO(NEGINTEN); 735 PRINTMFIO(POSINTSTAT); 736 PRINTMFIO(NEGINTSTAT); 737 __bitdisp(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15, 738 "CTRL", 1); 739 __bitdisp(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG), 740 8, 11, "]CRDDET/SENSE[", 1); 741 #endif 742 } 743
Indexes created Tue Sep 30 07:10:03 GMT 2025