mq200reg.h revision 1.1.2.2
1 /* $NetBSD: mq200reg.h,v 1.1.2.2 2000/08/06 03:56:42 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Takemura Shin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #define MQ200_VENDOR_ID 0x4d51 33 #define MQ200_PRODUCT_ID 0x0200 34 #define MQ200_MAPSIZE 0x800000 35 36 #define MQ200_POWERSTATE_D0 0 37 #define MQ200_POWERSTATE_D1 1 38 #define MQ200_POWERSTATE_D2 2 39 #define MQ200_POWERSTATE_D3 3 40 41 #define MQ200_FRAMEBUFFER 0x000000 /* frame buffer base address */ 42 #define MQ200_PM 0x600000 /* power management */ 43 #define MQ200_CC 0x602000 /* CPU interface */ 44 #define MQ200_MM 0x604000 /* memory interface unit */ 45 #define MQ200_IN 0x608000 /* interrupt controller */ 46 #define MQ200_GC(n) (0x60a000+0x80*(n)) 47 #define MQ200_GC1 0x60a000 /* graphice controller 1*/ 48 #define MQ200_GC2 0x60a080 /* graphice controller 1*/ 49 #define MQ200_GE 0x60c000 /* graphics engine */ 50 #define MQ200_FP 0x60e000 /* flat panel controller*/ 51 #define MQ200_CP1 0x610000 /* color palette 1 */ 52 #define MQ200_DC 0x614000 /* device configration */ 53 #define MQ200_PC 0x616000 /* PCI configration */ 54 55 /* 56 * Power Management 57 */ 58 59 /* 60 * CPU Interface 61 */ 62 63 /* 64 * Memory Interface Unit 65 */ 66 67 /* 68 * Interrupt Controller 69 */ 70 71 /* 72 * Graphics Controller 1/2 73 */ 74 /* GC Control (index: 00h) */ 75 #define MQ200_GCCR(n) (MQ200_GC(n)+0x00) 76 # define MQ200_GCC_ENABLE (1<<0) 77 # define MQ200_GCC_HCRESET (1<<1) 78 # define MQ200_GCC_VCRESET (1<<2) 79 # define MQ200_GCC_EN (1<<3) 80 # define MQ200_GCC_DEPTH_SHIFT 4 81 # define MQ200_GCC_DEPTH_MASK 0x000000f0 82 # define MQ200_GCC_CSREN (1<<8) 83 /* bits 10-9 is reserved */ 84 # define MQ200_GCC_ALTEN (1<<11) 85 # define MQ200_GCC_ALTDEPTH_SHIFT 12 86 # define MQ200_GCC_ALTDEPTH_MASK 0x0000f000 87 # define MQ200_GCC_RCLK_MASK 0x00030000 88 # define MQ200_GCC_RCLK_BUS 0x00000000 89 # define MQ200_GCC_RCLK_PLL1 0x00010000 90 # define MQ200_GCC_RCLK_PLL2 0x00020000 91 # define MQ200_GCC_RCLK_PLL3 0x00030000 92 # define MQ200_GCC_TESTMODE0 (1<<18) 93 # define MQ200_GCC_TESTMODE1 (1<<19) 94 /* FD(first clock divisor) is 1, 1.5, 2.5, 3.5, 4.5, 5.6 or 6.5 */ 95 # define MQ200_GCC_MCLK_FD_MASK 0x00700000 96 # define MQ200_GCC_MCLK_FD_1 0x00000000 97 # define MQ200_GCC_MCLK_FD_1_5 0x00100000 98 # define MQ200_GCC_MCLK_FD_2_5 0x00200000 99 # define MQ200_GCC_MCLK_FD_3_5 0x00300000 100 # define MQ200_GCC_MCLK_FD_4_5 0x00400000 101 # define MQ200_GCC_MCLK_FD_5_5 0x00500000 102 # define MQ200_GCC_MCLK_FD_6_5 0x00600000 103 /* bit 23 is reserved */ 104 /* SD(second close divisor) is 1-255. 0 means disable */ 105 # define MQ200_GCC_MCLK_SD_SHIFT 24 106 # define MQ200_GCC_MCLK_SD_MASK 0xff000000 107 /* GCCR_DEPTH and GCCR_ALTDEPTH values */ 108 # define MQ200_GCC_1BPP 0x0 109 # define MQ200_GCC_2BPP 0x1 110 # define MQ200_GCC_4BPP 0x2 111 # define MQ200_GCC_8BPP 0x3 112 # define MQ200_GCC_16BPP 0x4 113 # define MQ200_GCC_24BPP 0x5 114 # define MQ200_GCC_ARGB888 0x6 115 # define MQ200_GCC_PALBGR 0x6 116 # define MQ200_GCC_ABGR888 0x7 117 # define MQ200_GCC_PALRGB 0x7 118 # define MQ200_GCC_16BPP_DIRECT 0xc 119 # define MQ200_GCC_24BPP_DIRECT 0xd 120 # define MQ200_GCC_ARGB888_DIRECT 0xe 121 # define MQ200_GCC_PALBGR_DIRECT 0xe 122 # define MQ200_GCC_ABGR888_DIRECT 0xf 123 # define MQ200_GCC_PALRGB_DIRECT 0xf 124 125 /* GC CRT Control (index: 04h) */ 126 #define MQ200_GCCRTCR(n) (MQ200_GC(n)+0x04) 127 # define MQ200_GCCRTC_DACEN (1<<0) 128 # define MQ200_GCCRTC_HSYNC_PMCLK (1<<2) 129 # define MQ200_GCCRTC_VSYNC_PMCLK (1<<3) 130 # define MQ200_GCCRTC_HSYNC_LOW 0x00000010 131 # define MQ200_GCCRTC_HSYNC_HIGH 0x00000020 132 # define MQ200_GCCRTC_VSYNC_LOW 0x00000040 133 # define MQ200_GCCRTC_VSYNC_HIGH 0x00000080 134 # define MQ200_GCCRTC_HSYNC_ACTVHIGH (0<<8) 135 # define MQ200_GCCRTC_HSYNC_ACTVLOW (1<<8) 136 # define MQ200_GCCRTC_VSYNC_ACTVHIGH (0<<9) 137 # define MQ200_GCCRTC_VSYNC_ACTVLOW (1<<9) 138 # define MQ200_GCCRTC_SYNC_PEDESTAL_EN (1<<10) 139 # define MQ200_GCCRTC_BLANK_PEDESTAL_EN (1<<11) 140 # define MQ200_GCCRTC_COMPOSITE_SYNC_EN (1<<12) 141 # define MQ200_GCCRTC_VREF_INTR (0<<13) 142 # define MQ200_GCCRTC_VREF_EXTR (1<<13) 143 # define MQ200_GCCRTC_MONITOR_SENCE_EN (1<<14) 144 # define MQ200_GCCRTC_CONSTAND_OUTPUT_EN (1<<15) 145 # define MQ200_GCCRTC_OUTPUT_LEVEL_MASK 0x00ff0000 146 # define MQ200_GCCRTC_OUTPUT_LEVEL_SHIFT 16 147 # define MQ200_GCCRTC_BLUE_NOTLOADED (1<<24) 148 # define MQ200_GCCRTC_RED_NOTLOADED (1<<25) 149 # define MQ200_GCCRTC_GREEN_NOTLOADED (1<<26) 150 /* bit 27 is reserved */ 151 # define MQ200_GCCRTC_COLOR (0<<28) 152 # define MQ200_GCCRTC_MONO (1<<28) 153 /* bits 31-29 are reserved */ 154 155 /* GC Hotizontal Display Control (index: 08h) */ 156 #define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08) 157 # define MQ200_GCHDC_TOTAL_MASK 0x00000fff 158 # define MQ200_GCHDC_TOTAL_SHIFT 0 159 /* bits 15-12 are reserved */ 160 # define MQ200_GCHDC_END_MASK 0x0fff0000 161 # define MQ200_GCHDC_END_SHIFT 16 162 /* bits 31-28 are reserved */ 163 164 /* GC Vertical Display Control (index: 0Ch) */ 165 #define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c) 166 # define MQ200_GCVDC_TOTAL_MASK 0x00000fff 167 # define MQ200_GCVDC_TOTAL_SHIFT 0 168 /* bits 15-12 are reserved */ 169 # define MQ200_GCVDC_END_MASK 0x0fff0000 170 # define MQ200_GCVDC_END_SHIFT 16 171 /* bits 31-28 are reserved */ 172 173 /* GC Hotizontal Sync Control (index: 10h) */ 174 #define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10) 175 # define MQ200_GCHSC_START_MASK 0x00000fff 176 # define MQ200_GCHSC_START_SHIFT 0 177 /* bits 15-12 are reserved */ 178 # define MQ200_GCHSC_END_MASK 0x0fff0000 179 # define MQ200_GCHSC_END_SHIFT 16 180 /* bits 31-28 are reserved */ 181 182 /* GC Vertical Sync Control (index: 14h) */ 183 #define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14) 184 # define MQ200_GCVSC_START_MASK 0x00000fff 185 # define MQ200_GCVSC_START_SHIFT 0 186 /* bits 15-12 are reserved */ 187 # define MQ200_GCVSC_END_MASK 0x0fff0000 188 # define MQ200_GCVSC_END_SHIFT 16 189 /* bits 31-28 are reserved */ 190 191 /* GC Vertical Display Count (index: 1Ch) */ 192 #define MQ200_GCVDCNTR(n) (MQ200_GC(n)+0x1c) 193 # define MQ200_GCVDCNT_MASK 0x00000fff 194 /* bits 31-12 are reserved */ 195 196 /* GC Horizontal Window Control (index: 20h) */ 197 #define MQ200_GCHWCR(n) (MQ200_GC(n)+0x20) 198 # define MQ200_GCHWC_START_MASK 0x00000fff 199 # define MQ200_GCHWC_START_SHIFT 0 200 /* bits 15-12 are reserved */ 201 # define MQ200_GCHWC_WIDTH_MASK 0x0fff0000 202 # define MQ200_GCHWC_WIDTH_SHIFT 16 203 /* ALD: Additional Line Delta */ 204 # define MQ200_GCHWC_ALD_MASK 0xf0000000 205 # define MQ200_GCHWC_ALD_SHIFT 28 206 207 /* GC Vertical Window Control (index: 24h) */ 208 #define MQ200_GCVWCR(n) (MQ200_GC(n)+0x24) 209 # define MQ200_GCVWC_START_MASK 0x00000fff 210 # define MQ200_GCVWC_START_SHIFT 0 211 /* bits 15-12 are reserved */ 212 # define MQ200_GCVWC_HEIGHT_MASK 0x0fff0000 213 # define MQ200_GCVWC_HEIGHT_SHIFT 16 214 /* bits 31-28 are reserved */ 215 216 /* GC Altarnate Horizontal Window Control (index: 28h) */ 217 #define MQ200_GCHAWCR(n) (MQ200_GC(n)+0x28) 218 # define MQ200_GCAHWC_START_MASK 0x00000fff 219 # define MQ200_GCAHWC_START_SHIFT 0 220 /* bits 15-12 are reserved */ 221 # define MQ200_GCAHWC_WIDTH_MASK 0x0fff0000 222 # define MQ200_GCAHWC_WIDTH_SHIFT 16 223 /* ALD: Additional Line Delta */ 224 # define MQ200_GCAHWC_ALD_MASK 0xf0000000 225 # define MQ200_GCAHWC_ALD_SHIFT 28 226 227 /* GC Alternate Vertical Window Control (index: 2Ch) */ 228 #define MQ200_GCAVWCR(n) (MQ200_GC(n)+0x2C) 229 # define MQ200_GCAVWC_START_MASK 0x00000fff 230 # define MQ200_GCAVWC_START_SHIFT 0 231 /* bits 15-12 are reserved */ 232 # define MQ200_GCAVWC_HEIGHT_MASK 0x0fff0000 233 # define MQ200_GCAVWC_HEIGHT_SHIFT 16 234 /* bits 31-28 are reserved */ 235 236 /* GC Window Start Address (index: 30h) */ 237 #define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30) 238 # define MQ200_GCWSA_MASK 0x000fffff 239 /* bits 31-21 are reserved */ 240 241 /* GC Alternate Window Start Address (index: 34h) */ 242 #define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34) 243 # define MQ200_GCAWSA_MASK 0x000fffff 244 /* bits 24-21 are reserved */ 245 # define MQ200_GCAWPI_MASK 0xfe000000 246 # define MQ200_GCAWPI_SHIFT 24 /* XXX, 24 could be usefull 247 than 23 */ 248 249 /* GC Window Stride (index: 38h) */ 250 #define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38) 251 # define MQ200_GCWST_MASK 0x0000ffff 252 # define MQ200_GCWST_SHIFT 0 253 # define MQ200_GCWST_ALTMASK 0xffff0000 254 # define MQ200_GCWST_ALTSHIFT 16 255 256 /* GC Hardware Cursor Position (index: 40h) */ 257 #define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40) 258 # define MQ200_GCHCP_HSTART_MASK 0x00000fff 259 # define MQ200_GCHCP_HSTART_SHIFT 0 260 /* bits 15-12 are reserved */ 261 # define MQ200_GCHCP_VSTART_MASK 0x0fff0000 262 # define MQ200_GCHCP_VSTART_SHIFT 16 263 /* bits 31-28 are reserved */ 264 265 /* GC Hardware Start Address and Offset (index: 44h) */ 266 #define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44) 267 # define MQ200_GCHCAO_ADDR_MASK 0x00000fff 268 # define MQ200_GCHCAO_ADDR_SHIFT 0 269 /* bits 15-12 are reserved */ 270 # define MQ200_GCHCAO_HOFFSET_MASK 0x003f0000 271 # define MQ200_GCHCAO_HOFFSET_SHIFT 16 272 /* bits 23-22 are reserved */ 273 # define MQ200_GCHCAO_VOFFSET_MASK 0x3f000000 274 # define MQ200_GCHCAO_VOFFSET_SHIFT 24 275 /* bits 31-30 are reserved */ 276 277 /* GC Hardware Cursor Foreground Color (index: 48h) */ 278 #define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48) 279 # define MQ200_GCHCFC_MASK 0x00ffffff 280 /* you can use MQ200_GC_RGB macro */ 281 /* bits 31-24 are reserved */ 282 283 /* GC Hardware Cursor Background Color (index: 4Ch) */ 284 #define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c) 285 # define MQ200_GCHCBC_MASK 0x00ffffff 286 /* you can use MQ200_GC_RGB macro */ 287 /* bits 31-24 are reserved */ 288 289 #define MQ200_GC1CR MQ200_GCCR(0) 290 #define MQ200_GC1CRTCR MQ200_GCCRTCR(0) 291 #define MQ200_GC1HDCR MQ200_GCHDCR(0) 292 #define MQ200_GC1VDCR MQ200_GCVDCR(0) 293 #define MQ200_GC1HSCR MQ200_GCHSCR(0) 294 #define MQ200_GC1VSCR MQ200_GCVSCR(0) 295 #define MQ200_GC1VDCNTR MQ200_GCVDCNTR(0) 296 #define MQ200_GC1HWCR MQ200_GCHWCR(0) 297 #define MQ200_GC1VWCR MQ200_GCVWCR(0) 298 #define MQ200_GC1HAWCR MQ200_GCHAWCR(0) 299 #define MQ200_GC1AVWCR MQ200_GCAVWCR(0) 300 #define MQ200_GC1WSAR MQ200_GCWSAR(0) 301 #define MQ200_GC1AWSAR MQ200_GCAWSAR(0) 302 #define MQ200_GC1WSTR MQ200_GCWSTR(0) 303 #define MQ200_GC1HCPR MQ200_GCHCPR(0) 304 #define MQ200_GC1HCAOR MQ200_GCHCAOR(0) 305 #define MQ200_GC1HCFCR MQ200_GCHCFCR(0) 306 #define MQ200_GC1HCBCR MQ200_GCHCBCR(0) 307 308 #define MQ200_GC2CR MQ200_GCCR(1) 309 #define MQ200_GC2CRTCR MQ200_GCCRTCR(1) 310 #define MQ200_GC2HDCR MQ200_GCHDCR(1) 311 #define MQ200_GC2VDCR MQ200_GCVDCR(1) 312 #define MQ200_GC2HSCR MQ200_GCHSCR(1) 313 #define MQ200_GC2VSCR MQ200_GCVSCR(1) 314 #define MQ200_GC2VDCNTR MQ200_GCVDCNTR(1) 315 #define MQ200_GC2HWCR MQ200_GCHWCR(1) 316 #define MQ200_GC2VWCR MQ200_GCVWCR(1) 317 #define MQ200_GC2HAWCR MQ200_GCHAWCR(1) 318 #define MQ200_GC2AVWCR MQ200_GCAVWCR(1) 319 #define MQ200_GC2WSAR MQ200_GCWSAR(1) 320 #define MQ200_GC2AWSAR MQ200_GCAWSAR(1) 321 #define MQ200_GC2WSTR MQ200_GCWSTR(1) 322 #define MQ200_GC2HCPR MQ200_GCHCPR(1) 323 #define MQ200_GC2HCAOR MQ200_GCHCAOR(1) 324 #define MQ200_GC2HCFCR MQ200_GCHCFCR(1) 325 #define MQ200_GC2HCBCR MQ200_GCHCBCR(1) 326 327 /* 328 * Graphics Engine 329 */ 330 331 /* 332 * Flat Pannel Controler 333 */ 334 /* FP Control (index: 00h) */ 335 #define MQ200_FPCR (MQ200_FP + 0x00) 336 # define MQ200_FPC_EN (1<<0) 337 # define MQ200_FPC_GC1 (0<<1) 338 # define MQ200_FPC_GC2 (1<<1) 339 # define MQ200_FPC_TFT (0<<2) 340 # define MQ200_FPC_SSTN (1<<2) 341 # define MQ200_FPC_DSTN (2<<2) 342 # define MQ200_FPC_MODE_MASK 0x000000e0 343 # define MQ200_FPC_MODE_SHIFT 5 344 # define MQ200_FPC_MONO (1<<4) 345 # define MQ200_FPC_TFT4MONO (0<<5) 346 # define MQ200_FPC_TFT12 (0<<5) 347 # define MQ200_FPC_SSTN4 (0<<5) 348 # define MQ200_FPC_DSTN8 (0<<5) 349 # define MQ200_FPC_TFT6MONO (1<<5) 350 # define MQ200_FPC_TFT18 (1<<5) 351 # define MQ200_FPC_SSTN8 (1<<5) 352 # define MQ200_FPC_DSTN16 (1<<5) 353 # define MQ200_FPC_TFT8MONO (2<<5) 354 # define MQ200_FPC_TFT24 (2<<5) 355 # define MQ200_FPC_SSTN12 (2<<5) 356 # define MQ200_FPC_DSTN24 (2<<5) 357 # define MQ200_FPC_SSTN16 (3<<5) 358 # define MQ200_FPC_SSTN24 (4<<5) 359 # define MQ200_FPC_DITH_DISABLE (0<<8) 360 # define MQ200_FPC_DITH_PTRN1 (1<<8) 361 # define MQ200_FPC_DITH_PTRN2 (2<<8) 362 # define MQ200_FPC_DITH_PTRN3 (3<<8) 363 /* bits 11-10 are reserved */ 364 # define MQ200_FPC_DITH_BC_MASK 0x00007000 365 # define MQ200_FPC_DITH_BC_SHIFT 12 366 # define MQ200_FPC_FRC_DISABLE_ALTWIN (1<<15) 367 # define MQ200_FPC_FRC_2LEVEL (0<<16) 368 # define MQ200_FPC_FRC_4LEVEL (1<<16) 369 # define MQ200_FPC_FRC_8LEVEL (2<<16) 370 # define MQ200_FPC_FRC_16LEVEL (3<<16) 371 # define MQ200_FPC_DITH_ADJ_MASK 0x0ffc0000 372 # define MQ200_FPC_DITH_ADJ_SHIFT 18 373 # define MQ200_FPC_DITH_ADJ_VAL 0x018 374 # define MQ200_FPC_DITH_ADJ1_MASK 0x00fc0000 375 # define MQ200_FPC_DITH_ADJ1_SHIFT 18 376 # define MQ200_FPC_DITH_ADJ1_VAL 0x18 377 # define MQ200_FPC_DITH_ADJ2_MASK 0x07000000 378 # define MQ200_FPC_DITH_ADJ2_SHIFT 24 379 # define MQ200_FPC_DITH_ADJ2_VAL 0x0 380 # define MQ200_FPC_DITH_ADJ3_MASK 0x08000000 381 # define MQ200_FPC_DITH_ADJ3_SHIFT 27 382 # define MQ200_FPC_DITH_ADJ3_VAL 0x0 383 # define MQ200_FPC_TESTMODE0 (1<<28) 384 # define MQ200_FPC_TESTMODE1 (1<<29) 385 # define MQ200_FPC_TESTMODE2 (1<<30) 386 # define MQ200_FPC_TESTMODE3 (1<<31) 387 388 /* FP Output Pin Control (index: 04h) */ 389 #define MQ200_FPPCR (MQ200_FP + 0x04) 390 # define MQ200_FPPC_PIN_LOW (1<<0) 391 # define MQ200_FPPC_INVERSION_EN (1<<1) 392 # define MQ200_FPPC_FDE_COMPOSITE (0<<2) 393 # define MQ200_FPPC_FDE_HORIZONTAL (1<<2) 394 # define MQ200_FPPC_FDE_FMOD_EN (1<<3) 395 # define MQ200_FPPC_FD2_DATAK (0<<4) 396 # define MQ200_FPPC_FD2_SHIFTCLK (1<<4) 397 # define MQ200_FPPC_FSCLK_EN (1<<5) 398 # define MQ200_FPPC_SHIFTCLK_DIV2 (1<<6) 399 # define MQ200_FPPC_SHIFTCLK_MASK (1<<7) 400 # define MQ200_FPPC_STNLP_BLANK (1<<8) 401 # define MQ200_FPPC_SHIFTCLK_BLANK (1<<9) 402 # define MQ200_FPPC_STNEXLP_EN (1<<10) 403 /* bit 11 is reserved */ 404 # define MQ200_FPPC_FD2_MAX (0<<12) 405 # define MQ200_FPPC_FD2_MID (1<<12) 406 # define MQ200_FPPC_FD2_MID2 (2<<12) 407 # define MQ200_FPPC_FD2_MIN (3<<12) 408 # define MQ200_FPPC_DRV_MAX (0<<12) 409 # define MQ200_FPPC_DRV_MID (1<<12) 410 # define MQ200_FPPC_DRV_MID2 (2<<12) 411 # define MQ200_FPPC_DRV_MIN (3<<12) 412 # define MQ200_FPPC_FD2_ACTVHIGH (0<<16) 413 # define MQ200_FPPC_FD2_ACTVLOW (1<<16) 414 # define MQ200_FPPC_ACTVHIGH (0<<17) 415 # define MQ200_FPPC_ACTVLOW (1<<17) 416 # define MQ200_FPPC_FDE_ACTVHIGH (0<<18) 417 # define MQ200_FPPC_FDE_ACTVLOW (1<<18) 418 # define MQ200_FPPC_FHSYNC_ACTVHIGH (0<<19) 419 # define MQ200_FPPC_FHSYNC_ACTVLOW (1<<19) 420 # define MQ200_FPPC_FVSYNC_ACTVHIGH (0<<20) 421 # define MQ200_FPPC_FVSYNC_ACTVLOW (1<<20) 422 # define MQ200_FPPC_FSCLK_ACTVHIGH (0<<21) 423 # define MQ200_FPPC_FSCLK_ACTVLOW (1<<21) 424 # define MQ200_FPPC_FSCLK_MAX (0<<22) 425 # define MQ200_FPPC_FSCLK_MID (1<<22) 426 # define MQ200_FPPC_FSCLK_MID2 (2<<22) 427 # define MQ200_FPPC_FSCLK_MIN (3<<22) 428 # define MQ200_FPPC_FSCLK_DELAY_MASK 0x07000000 429 # define MQ200_FPPC_FSCLK_DELAY_SHIFT 24 430 /* bits 31-27 are reserved */ 431 432 /* FP General Purpose Output Port Control (index: 08h) */ 433 #define MQ200_FPGPOCR (MQ200_FP + 0x08) 434 # define MQ200_FPGPOC_ENCTL_EN (0<<0) 435 # define MQ200_FPGPOC_GPO0_EN (1<<0) 436 # define MQ200_FPGPOC_OSCCLK_EN (2<<0) 437 # define MQ200_FPGPOC_PLL3_EN (3<<0) 438 # define MQ200_FPGPOC_ENVEE_EN (0<<2) 439 # define MQ200_FPGPOC_GPO1_EN (1<<2) 440 # define MQ200_FPGPOC_PWM0_EN (0<<4) 441 # define MQ200_FPGPOC_GPO2_EN (1<<4) 442 # define MQ200_FPGPOC_PWM1_EN (0<<6) 443 # define MQ200_FPGPOC_GPO3_EN (1<<6) 444 # define MQ200_FPGPOC_ENVDD_EN (0<<8) 445 # define MQ200_FPGPOC_GPO4_EN (1<<9) 446 # define MQ200_FPGPOC_PWM_MAX (0<<10) 447 # define MQ200_FPGPOC_PWM_MID (1<<10) 448 # define MQ200_FPGPOC_PWM_MID2 (2<<10) 449 # define MQ200_FPGPOC_PWM_MIN (3<<10) 450 # define MQ200_FPGPOC_GPO_MAX (0<<12) 451 # define MQ200_FPGPOC_GPO_MID (1<<12) 452 # define MQ200_FPGPOC_GPO_MID2 (2<<12) 453 # define MQ200_FPGPOC_GPO_MIN (3<<12) 454 # define MQ200_FPGPOC_DRV_MAX (0<<14) 455 # define MQ200_FPGPOC_DRV_MID (1<<14) 456 # define MQ200_FPGPOC_DRV_MID2 (2<<14) 457 # define MQ200_FPGPOC_DRV_MIN (3<<14) 458 # define MQ200_FPGPOC_GPO0 (1<<16) 459 # define MQ200_FPGPOC_GPO1 (1<<17) 460 # define MQ200_FPGPOC_GPO2 (1<<18) 461 # define MQ200_FPGPOC_GPO3 (1<<19) 462 # define MQ200_FPGPOC_GPO4 (1<<20) 463 /* bits 31-21 are reserved */ 464 465 /* FP General Purpose I/O Port Control (index: 0Ch) */ 466 #define MQ200_FPGPOICR (MQ200_FP + 0x0c) 467 # define MQ200_FPGPIOC_INPUT0_EN (0<<0) 468 # define MQ200_FPGPIOC_OUTPUT0_EN (1<<0 469 # define MQ200_FPGPIOC_PLL1_EN (2<<0) 470 # define MQ200_FPGPIOC_CRCBLUE_EN (3<<0) 471 # define MQ200_FPGPIOC_INPUT1_EN (0<<2) 472 # define MQ200_FPGPIOC_OUTPUT1_EN (1<<2 473 # define MQ200_FPGPIOC_PLL2_EN (2<<2) 474 # define MQ200_FPGPIOC_CRCGREEN_EN (3<<2) 475 # define MQ200_FPGPIOC_INPUT2_EN (0<<4) 476 # define MQ200_FPGPIOC_OUTPUT2_EN (1<<4 477 # define MQ200_FPGPIOC_PMCLK_EN (2<<4) 478 # define MQ200_FPGPIOC_CRCRED_EN (3<<4) 479 /* bits 15-6 are reserved */ 480 # define MQ200_FPGPIOC_OUTPUT0 (1<<16) 481 # define MQ200_FPGPIOC_OUTPUT1 (1<<17) 482 # define MQ200_FPGPIOC_OUTPUT2 (1<<18) 483 /* bits 23-19 are reserved */ 484 # define MQ200_FPGPIOC_INPUT0 (1<<24) 485 # define MQ200_FPGPIOC_INPUT1 (1<<25) 486 # define MQ200_FPGPIOC_INPUT2 (1<<26) 487 /* bits 31-27 are reserved */ 488 489 /* FP STN Panel Control (index: 10h) */ 490 #define MQ200_FPSTNCR (MQ200_FP + 0x10) 491 # define MQ200_FPSTNC_FRCPRM0_MASK 0x000000ff 492 # define MQ200_FPSTNC_FRCPRM0_SHIFT 0 493 # define MQ200_FPSTNC_FRCPRM1_MASK 0x0000ff00 494 # define MQ200_FPSTNC_FRCPRM1_SHIFT 8 495 # define MQ200_FPSTNC_FRCPRM2_MASK 0x00ff0000 496 # define MQ200_FPSTNC_FRCPRM2_SHIFT 16 497 # define MQ200_FPSTNC_FMOD_MASK 0x7f000000 498 # define MQ200_FPSTNC_FMOD_SHIFT 24 499 # define MQ200_FPSTNC_FMOD_FRAMECLK (0<<31) 500 # define MQ200_FPSTNC_FMOD_LINECLK (0<<31) 501 502 /* FP D-STN Half-Frame Buffer Control (index: 14h) */ 503 #define MQ200_FPHFBCR (MQ200_FP + 0x14) 504 # define MQ200_FPHFBC_START_MASK 0x00003fff 505 # define MQ200_FPHFBC_START_SHIFT -7 /* XXX, does this work? */ 506 /* bits 15-14 are reserved */ 507 # define MQ200_FPHFBC_END_MASK 0xffff0000 508 # define MQ200_FPHFBC_END_SHIFT (16-4) /* XXX, does this work? */ 509 510 /* FP Pulse Width Modulation Control (index: 3Ch) */ 511 #define MQ200_FPPWMCR (MQ200_FP + 0x3c) 512 # define MQ200_FPPWMC_PWM0_OSCCLK (0<<0) 513 # define MQ200_FPPWMC_PWM0_BUSCLK (1<<0) 514 # define MQ200_FPPWMC_PWM0_PMCLK (2<<0) 515 # define MQ200_FPPWMC_PWM0_PWSEQ_EN (0<<2) 516 # define MQ200_FPPWMC_PWM0_PWSEQ_DISABLE (1<<2) 517 /* bit 3 is reserved */ 518 # define MQ200_FPPWMC_PWM0_DIV_MASK 0x000000f0 519 # define MQ200_FPPWMC_PWM0_DIV_SHIFT 4 520 # define MQ200_FPPWMC_PWM0_DCYCLE_MASK 0x0000ff00 521 # define MQ200_FPPWMC_PWM0_DCYCLE_SHIFT 8 522 # define MQ200_FPPWMC_PWM1_OSCCLK (0<<16) 523 # define MQ200_FPPWMC_PWM1_BUSCLK (1<<16) 524 # define MQ200_FPPWMC_PWM1_PMCLK (2<<16) 525 # define MQ200_FPPWMC_PWM1_PWSEQ_EN (0<<18) 526 # define MQ200_FPPWMC_PWM1_PWSEQ_DISABLE (1<<18) 527 /* bit 19 is reserved */ 528 # define MQ200_FPPWMC_PWM1_DIV_MASK 0x00f00000 529 # define MQ200_FPPWMC_PWM1_DIV_SHIFT 20 530 # define MQ200_FPPWMC_PWM1_DCYCLE_MASK 0xff000000 531 # define MQ200_FPPWMC_PWM1_DCYCLE_SHIFT 24 532 533 /* FP Frame Rate Control Pattern (index: 40h to BCh) */ 534 #define MQ200_FPFRCPR (MQ200_FP + 0x40) 535 536 /* FP Frame Rate Control Weight (index: C0h to DCh) */ 537 #define MQ200_FPFRCWR (MQ200_FP + 0xC0) 538 539 /* 540 * Color Palette 1 541 */ 542 #define MQ200_CP(cp, idx) (MQ200_CP1 + (idx) * 4) */ 543 # define MQ200_GC_BLUE_MASK 0x00ff0000 544 # define MQ200_GC_BLUE_SHIFT 16 545 # define MQ200_GC_GREEN_MASK 0x0000ff00 546 # define MQ200_GC_GREEN_SHIFT 8 547 # define MQ200_GC_RED_MASK 0x000000ff 548 # define MQ200_GC_RED_SHIFT 0 549 # define MQ200_GC_RGB(r, g, b) \ 550 (((((unsigned long)(r))&0xff)<<0) | \ 551 ((((unsigned long)(g))&0xff)<<8) | \ 552 ((((unsigned long)(b))&0xff)<<16)) 553 554 /* 555 * Device Configration 556 */ 557 558 /* 559 * PCI configuration space 560 */ 561 #define MQ200_PC00R (MQ200_PC+0x00) /* device/vendor ID */ 562 #define MQ200_PC04R (MQ200_PC+0x04) /* command/status */ 563 #define MQ200_PC08R (MQ200_PC+0x04) /* calss code/revision */ 564 565 #define MQ200_PMR (MQ200_PC+0x40) /* power management */ 566 #define MQ200_PMCSR (MQ200_PC+0x44) /* control/status */ 567
Indexes created Mon Oct 20 16:09:52 GMT 2025