mq200reg.h revision 1.1.4.5
1 /* $NetBSD: mq200reg.h,v 1.1.4.5 2001/03/12 13:28:37 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Takemura Shin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #define MQ200_VENDOR_ID 0x4d51 33 #define MQ200_PRODUCT_ID 0x0200 34 #define MQ200_MAPSIZE 0x800000 35 36 #define MQ200_POWERSTATE_D0 0 37 #define MQ200_POWERSTATE_D1 1 38 #define MQ200_POWERSTATE_D2 2 39 #define MQ200_POWERSTATE_D3 3 40 41 #define MQ200_CLOCK_BUS 0 42 #define MQ200_CLOCK_PLL1 1 43 #define MQ200_CLOCK_PLL2 2 44 #define MQ200_CLOCK_PLL3 3 45 46 #define MQ200_FRAMEBUFFER 0x000000 /* frame buffer base address */ 47 #define MQ200_PM 0x600000 /* power management */ 48 #define MQ200_CC 0x602000 /* CPU interface */ 49 #define MQ200_MM 0x604000 /* memory interface unit */ 50 #define MQ200_IN 0x608000 /* interrupt controller */ 51 #define MQ200_GC(n) (0x60a000+0x80*(n)) 52 #define MQ200_GE 0x60c000 /* graphics engine */ 53 #define MQ200_FP 0x60e000 /* flat panel controller*/ 54 #define MQ200_CP1 0x610000 /* color palette 1 */ 55 #define MQ200_DC 0x614000 /* device configration */ 56 #define MQ200_PC 0x616000 /* PCI configration */ 57 58 /* 59 * Power Management 60 */ 61 62 /* 63 * CPU Interface 64 */ 65 66 /* 67 * Memory Interface Unit 68 */ 69 #define MQ200_MMR(n) (MQ200_MM+(n)*4) 70 # define MQ200_MM00_ENABLE (1<<0) 71 # define MQ200_MM00_RESET (1<<1) 72 # define MQ200_MM00_DRAM_RESET (1<<2) 73 # define MQ200_MM01_CLK_PLL1 (0<<0) 74 # define MQ200_MM01_CLK_BUS (1<<0) 75 # define MQ200_MM01_CLK_PLL2 (1<<0) 76 77 /* 78 * Interrupt Controller 79 */ 80 81 /* 82 * Graphics Controller 1/2 83 */ 84 #define MQ200_GC1 0 /* graphice controller 1*/ 85 #define MQ200_GC2 1 /* graphice controller 2*/ 86 #define MQ200_GCR(n) (MQ200_GC(0)+(n)*4) 87 /* GC Control (GC00R and GC20R) */ 88 #define MQ200_GCCR(n) (MQ200_GC(n)+0x00) 89 # define MQ200_GCC_ENABLE (1<<0) 90 # define MQ200_GCC_HCRESET (1<<1) 91 # define MQ200_GCC_VCRESET (1<<2) 92 # define MQ200_GCC_WINEN (1<<3) 93 # define MQ200_GCC_DEPTH_SHIFT 4 94 # define MQ200_GCC_DEPTH_MASK 0x000000f0 95 # define MQ200_GCC_HCEN (1<<8) 96 /* bits 10-9 is reserved */ 97 # define MQ200_GCC_ALTEN (1<<11) 98 # define MQ200_GCC_ALTDEPTH_SHIFT 12 99 # define MQ200_GCC_ALTDEPTH_MASK 0x0000f000 100 # define MQ200_GCC_RCLK_SHIFT 16 101 # define MQ200_GCC_RCLK_MASK 0x00030000 102 # define MQ200_GCC_RCLK_BUS 0x00000000 103 # define MQ200_GCC_RCLK_PLL1 0x00010000 104 # define MQ200_GCC_RCLK_PLL2 0x00020000 105 # define MQ200_GCC_RCLK_PLL3 0x00030000 106 # define MQ200_GCC_TESTMODE0 (1<<18) 107 # define MQ200_GCC_TESTMODE1 (1<<19) 108 /* FD(first clock divisor) is 1, 1.5, 2.5, 3.5, 4.5, 5.6 or 6.5 */ 109 # define MQ200_GCC_MCLK_FD_SHIFT 20 110 # define MQ200_GCC_MCLK_FD_MASK 0x00700000 111 # define MQ200_GCC_MCLK_FD_1 0x00000000 112 # define MQ200_GCC_MCLK_FD_1_5 0x00100000 113 # define MQ200_GCC_MCLK_FD_2_5 0x00200000 114 # define MQ200_GCC_MCLK_FD_3_5 0x00300000 115 # define MQ200_GCC_MCLK_FD_4_5 0x00400000 116 # define MQ200_GCC_MCLK_FD_5_5 0x00500000 117 # define MQ200_GCC_MCLK_FD_6_5 0x00600000 118 /* bit 23 is reserved */ 119 /* SD(second close divisor) is 1-255. 0 means disable */ 120 # define MQ200_GCC_MCLK_SD_SHIFT 24 121 # define MQ200_GCC_MCLK_SD_MASK 0xff000000 122 /* GCCR_DEPTH and GCCR_ALTDEPTH values */ 123 # define MQ200_GCC_1BPP 0x0 124 # define MQ200_GCC_2BPP 0x1 125 # define MQ200_GCC_4BPP 0x2 126 # define MQ200_GCC_8BPP 0x3 127 # define MQ200_GCC_16BPP 0x4 128 # define MQ200_GCC_24BPP 0x5 129 # define MQ200_GCC_ARGB888 0x6 130 # define MQ200_GCC_PALBGR 0x6 131 # define MQ200_GCC_ABGR888 0x7 132 # define MQ200_GCC_PALRGB 0x7 133 # define MQ200_GCC_16BPP_DIRECT 0xc 134 # define MQ200_GCC_24BPP_DIRECT 0xd 135 # define MQ200_GCC_ARGB888_DIRECT 0xe 136 # define MQ200_GCC_PALBGR_DIRECT 0xe 137 # define MQ200_GCC_ABGR888_DIRECT 0xf 138 # define MQ200_GCC_PALRGB_DIRECT 0xf 139 140 /* GC CRT Control (GC1only) */ 141 #define MQ200_GC1CRTCR MQ200_GCR(0x01) 142 # define MQ200_GC1CRTC_DACEN (1<<0) 143 # define MQ200_GC1CRTC_HSYNC_PMCLK (1<<2) 144 # define MQ200_GC1CRTC_VSYNC_PMCLK (1<<3) 145 # define MQ200_GC1CRTC_HSYNC_PMMASK 0x00000030 146 # define MQ200_GC1CRTC_HSYNC_PMNORMAL 0x00000000 147 # define MQ200_GC1CRTC_HSYNC_PMLOW 0x00000010 148 # define MQ200_GC1CRTC_HSYNC_PMHIGH 0x00000020 149 # define MQ200_GC1CRTC_VSYNC_PMMASK 0x000000c0 150 # define MQ200_GC1CRTC_VSYNC_PMNORMAL 0x00000000 151 # define MQ200_GC1CRTC_VSYNC_PMLOW 0x00000040 152 # define MQ200_GC1CRTC_VSYNC_PMHIGH 0x00000080 153 # define MQ200_GC1CRTC_HSYNC_ACTVHIGH (0<<8) 154 # define MQ200_GC1CRTC_HSYNC_ACTVLOW (1<<8) 155 # define MQ200_GC1CRTC_VSYNC_ACTVHIGH (0<<9) 156 # define MQ200_GC1CRTC_VSYNC_ACTVLOW (1<<9) 157 # define MQ200_GC1CRTC_SYNC_PEDESTAL_EN (1<<10) 158 # define MQ200_GC1CRTC_BLANK_PEDESTAL_EN (1<<11) 159 # define MQ200_GC1CRTC_COMPOSITE_SYNC_EN (1<<12) 160 # define MQ200_GC1CRTC_VREF_INTR (0<<13) 161 # define MQ200_GC1CRTC_VREF_EXTR (1<<13) 162 # define MQ200_GC1CRTC_MONITOR_SENCE_EN (1<<14) 163 # define MQ200_GC1CRTC_CONSTANT_OUTPUT_EN (1<<15) 164 # define MQ200_GC1CRTC_OUTPUT_LEVEL_MASK 0x00ff0000 165 # define MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT 16 166 # define MQ200_GC1CRTC_BLUE_NOTLOADED (1<<24) 167 # define MQ200_GC1CRTC_RED_NOTLOADED (1<<25) 168 # define MQ200_GC1CRTC_GREEN_NOTLOADED (1<<26) 169 /* bit 27 is reserved */ 170 # define MQ200_GC1CRTC_COLOR (0<<28) 171 # define MQ200_GC1CRTC_MONO (1<<28) 172 /* bits 31-29 are reserved */ 173 174 /* GC CRC Control (GC2 only) */ 175 #define MQ200_GC2CRCCR MQ200_GCR(0x21) 176 # define MQ200_GC2CRCC_ENABLE (1<<0) 177 # define MQ200_GC2CRCC_WAIT1VSYNC (0<<1) 178 # define MQ200_GC2CRCC_WAIT2VSYNC (1<<1) 179 # define MQ200_GC2CRCC_BLUE (0x0<<2) 180 # define MQ200_GC2CRCC_GREEN (0x1<<2) 181 # define MQ200_GC2CRCC_RED (0x2<<2) 182 # define MQ200_GC2CRCC_RESULT_SHIFT 8 183 # define MQ200_GC2CRCC_RESULT_MASK 0x3fffff00 184 185 /* GC Hotizontal Display Control (GC02R and GC22R) */ 186 #define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08) 187 # define MQ200_GC1HDC_TOTAL_MASK 0x00000fff 188 # define MQ200_GC1HDC_TOTAL_SHIFT 0 189 /* bits 15-12 are reserved */ 190 # define MQ200_GCHDC_END_MASK 0x0fff0000 191 # define MQ200_GCHDC_END_SHIFT 16 192 /* bits 31-28 are reserved */ 193 194 /* GC Vertical Display Control (GC03R and GC23R) */ 195 #define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c) 196 # define MQ200_GC1VDC_TOTAL_MASK 0x00000fff 197 # define MQ200_GC1VDC_TOTAL_SHIFT 0 198 /* bits 15-12 are reserved */ 199 # define MQ200_GCVDC_END_MASK 0x0fff0000 200 # define MQ200_GCVDC_END_SHIFT 16 201 /* bits 31-28 are reserved */ 202 203 /* GC Hotizontal Sync Control (GC04R and GC24R) */ 204 #define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10) 205 # define MQ200_GCHSC_START_MASK 0x00000fff 206 # define MQ200_GCHSC_START_SHIFT 0 207 /* bits 15-12 are reserved */ 208 # define MQ200_GCHSC_END_MASK 0x0fff0000 209 # define MQ200_GCHSC_END_SHIFT 16 210 /* bits 31-28 are reserved */ 211 212 /* GC Vertical Sync Control (GC05R and GC25R) */ 213 #define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14) 214 # define MQ200_GCVSC_START_MASK 0x00000fff 215 # define MQ200_GCVSC_START_SHIFT 0 216 /* bits 15-12 are reserved */ 217 # define MQ200_GCVSC_END_MASK 0x0fff0000 218 # define MQ200_GCVSC_END_SHIFT 16 219 /* bits 31-28 are reserved */ 220 221 /* GC Vertical Display Count (GC07R) */ 222 #define MQ200_GC1VDCNTR MQ200_GCR(0x07) 223 # define MQ200_GC1VDCNT_MASK 0x00000fff 224 /* bits 31-12 are reserved */ 225 226 /* GC Window Horizontal Control (GC08R and GC28R) */ 227 #define MQ200_GCWHCR(n) (MQ200_GC(n)+0x20) 228 # define MQ200_GCWHC_START_MASK 0x00000fff 229 # define MQ200_GCWHC_START_SHIFT 0 230 /* bits 15-12 are reserved */ 231 # define MQ200_GCWHC_WIDTH_MASK 0x0fff0000 232 # define MQ200_GCWHC_WIDTH_SHIFT 16 233 /* ALD: Additional Line Delta (GC1 only) */ 234 # define MQ200_GC1WHC_ALD_MASK 0xf0000000 235 # define MQ200_GC1WHC_ALD_SHIFT 28 236 237 /* GC Window Vertical Control (GC09R and GC29R) */ 238 #define MQ200_GCWVCR(n) (MQ200_GC(n)+0x24) 239 # define MQ200_GCWVC_START_MASK 0x00000fff 240 # define MQ200_GCWVC_START_SHIFT 0 241 /* bits 15-12 are reserved */ 242 # define MQ200_GCWVC_HEIGHT_MASK 0x0fff0000 243 # define MQ200_GCWVC_HEIGHT_SHIFT 16 244 /* bits 31-28 are reserved */ 245 246 /* GC Altarnate Window Horizontal Control (GC0AR and GC2AR) */ 247 #define MQ200_GCAWHCR(n) (MQ200_GC(n)+0x28) 248 # define MQ200_GCAWHC_START_MASK 0x00000fff 249 # define MQ200_GCAWHC_START_SHIFT 0 250 /* bits 15-12 are reserved */ 251 # define MQ200_GCAWHC_WIDTH_MASK 0x0fff0000 252 # define MQ200_GCAWHC_WIDTH_SHIFT 16 253 /* ALD: Additional Line Delta (GC1 only) */ 254 # define MQ200_GC1AWHC_ALD_MASK 0xf0000000 255 # define MQ200_GC1AWHC_ALD_SHIFT 28 256 257 /* GC Alternate Window Vertical Control (GC0BR and GC2BR) */ 258 #define MQ200_GCAWVCR(n) (MQ200_GC(n)+0x2C) 259 # define MQ200_GCAWVC_START_MASK 0x00000fff 260 # define MQ200_GCAWVC_START_SHIFT 0 261 /* bits 15-12 are reserved */ 262 # define MQ200_GCAWVC_HEIGHT_MASK 0x0fff0000 263 # define MQ200_GCAWVC_HEIGHT_SHIFT 16 264 /* bits 31-28 are reserved */ 265 266 /* GC Window Start Address (GC0CR and GC2CR) */ 267 #define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30) 268 # define MQ200_GCWSA_MASK 0x000fffff 269 /* bits 31-21 are reserved */ 270 271 /* GC Alternate Window Start Address (GC0DR and GC2DR) */ 272 #define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34) 273 # define MQ200_GCAWSA_MASK 0x000fffff 274 /* bits 24-21 are reserved */ 275 # define MQ200_GCAWPI_MASK 0xfe000000 276 # define MQ200_GCAWPI_SHIFT 24 /* XXX, 24 could be usefull 277 than 23 */ 278 279 /* GC Window Stride (GC0ER and GC2ER) */ 280 #define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38) 281 # define MQ200_GCWST_MASK 0x0000ffff 282 # define MQ200_GCWST_SHIFT 0 283 # define MQ200_GCAWST_MASK 0xffff0000 284 # define MQ200_GCAWST_SHIFT 16 285 286 /* GC2 Line Size (GC2 only, GC2FR) */ 287 #define MQ200_GC2LSR MQ200_GCR(0x2f) 288 # define MQ200_GC2WLS_MASK 0x00003fff 289 # define MQ200_GC2WLS_SHIFT 0 290 # define MQ200_GC2AWLS_MASK 0x3fff0000 291 # define MQ200_GC2AWLS_SHIFT 16 292 293 294 /* GC Hardware Cursor Position (GC10R and GC30R) */ 295 #define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40) 296 # define MQ200_GCHCP_HSTART_MASK 0x00000fff 297 # define MQ200_GCHCP_HSTART_SHIFT 0 298 /* bits 15-12 are reserved */ 299 # define MQ200_GCHCP_VSTART_MASK 0x0fff0000 300 # define MQ200_GCHCP_VSTART_SHIFT 16 301 /* bits 31-28 are reserved */ 302 303 /* GC Hardware Start Address and Offset (GC11R and GC31R) */ 304 #define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44) 305 # define MQ200_GCHCAO_ADDR_MASK 0x00000fff 306 # define MQ200_GCHCAO_ADDR_SHIFT 0 307 /* bits 15-12 are reserved */ 308 # define MQ200_GCHCAO_HOFFSET_MASK 0x003f0000 309 # define MQ200_GCHCAO_HOFFSET_SHIFT 16 310 /* bits 23-22 are reserved */ 311 # define MQ200_GCHCAO_VOFFSET_MASK 0x3f000000 312 # define MQ200_GCHCAO_VOFFSET_SHIFT 24 313 /* bits 31-30 are reserved */ 314 315 /* GC Hardware Cursor Foreground Color (GC13R and GC33R) */ 316 #define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48) 317 # define MQ200_GCHCFC_MASK 0x00ffffff 318 /* you can use MQ200_GC_RGB macro */ 319 /* bits 31-24 are reserved */ 320 321 /* GC Hardware Cursor Background Color (GC14R and GC34R) */ 322 #define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c) 323 # define MQ200_GCHCBC_MASK 0x00ffffff 324 /* you can use MQ200_GC_RGB macro */ 325 /* bits 31-24 are reserved */ 326 327 #define MQ200_GC1CR MQ200_GCCR(0) 328 #define MQ200_GC1HDCR MQ200_GCHDCR(0) 329 #define MQ200_GC1VDCR MQ200_GCVDCR(0) 330 #define MQ200_GC1HSCR MQ200_GCHSCR(0) 331 #define MQ200_GC1VSCR MQ200_GCVSCR(0) 332 #define MQ200_GC1HWCR MQ200_GCHWCR(0) 333 #define MQ200_GC1VWCR MQ200_GCVWCR(0) 334 #define MQ200_GC1HAWCR MQ200_GCHAWCR(0) 335 #define MQ200_GC1AVWCR MQ200_GCAVWCR(0) 336 #define MQ200_GC1WSAR MQ200_GCWSAR(0) 337 #define MQ200_GC1AWSAR MQ200_GCAWSAR(0) 338 #define MQ200_GC1WSTR MQ200_GCWSTR(0) 339 #define MQ200_GC1HCPR MQ200_GCHCPR(0) 340 #define MQ200_GC1HCAOR MQ200_GCHCAOR(0) 341 #define MQ200_GC1HCFCR MQ200_GCHCFCR(0) 342 #define MQ200_GC1HCBCR MQ200_GCHCBCR(0) 343 344 #define MQ200_GC2CR MQ200_GCCR(1) 345 #define MQ200_GC2HDCR MQ200_GCHDCR(1) 346 #define MQ200_GC2VDCR MQ200_GCVDCR(1) 347 #define MQ200_GC2HSCR MQ200_GCHSCR(1) 348 #define MQ200_GC2VSCR MQ200_GCVSCR(1) 349 #define MQ200_GC2HWCR MQ200_GCHWCR(1) 350 #define MQ200_GC2VWCR MQ200_GCVWCR(1) 351 #define MQ200_GC2HAWCR MQ200_GCHAWCR(1) 352 #define MQ200_GC2AVWCR MQ200_GCAVWCR(1) 353 #define MQ200_GC2WSAR MQ200_GCWSAR(1) 354 #define MQ200_GC2AWSAR MQ200_GCAWSAR(1) 355 #define MQ200_GC2WSTR MQ200_GCWSTR(1) 356 #define MQ200_GC2HCPR MQ200_GCHCPR(1) 357 #define MQ200_GC2HCAOR MQ200_GCHCAOR(1) 358 #define MQ200_GC2HCFCR MQ200_GCHCFCR(1) 359 #define MQ200_GC2HCBCR MQ200_GCHCBCR(1) 360 361 /* 362 * Graphics Engine 363 */ 364 365 /* 366 * Flat Pannel Controler 367 */ 368 #define MQ200_FPR(n) (MQ200_FP + (n)*4) 369 /* FP Control (FP00R) */ 370 #define MQ200_FPCR MQ200_FPR(0) 371 # define MQ200_FPC_ENABLE (1<<0) 372 # define MQ200_FPC_GC1 (0<<1) 373 # define MQ200_FPC_GC2 (1<<1) 374 # define MQ200_FPC_TYPE_MASK 0x000000fc 375 # define MQ200_FPC_TYPE_SHIFT 2 376 377 # define MQ200_FPC_TFT (0<<2) 378 # define MQ200_FPC_SSTN (1<<2) 379 # define MQ200_FPC_DSTN (2<<2) 380 381 # define MQ200_FPC_COLOR (0<<4) 382 # define MQ200_FPC_MONO (1<<4) 383 384 # define MQ200_FPC_TFTCOLOR (MQ200_FPC_TFT|MQ200_FPC_COLOR) 385 # define MQ200_FPC_SSTNCOLOR (MQ200_FPC_SSTN|MQ200_FPC_COLOR) 386 # define MQ200_FPC_DSTNCOLOR (MQ200_FPC_DSTN|MQ200_FPC_COLOR) 387 388 # define MQ200_FPC_TFTMONO (MQ200_FPC_TFT|MQ200_FPC_MONO) 389 # define MQ200_FPC_SSTNMONO (MQ200_FPC_SSTN|MQ200_FPC_MONO) 390 # define MQ200_FPC_DSTNMONO (MQ200_FPC_DSTN|MQ200_FPC_MONO) 391 392 # define MQ200_FPC_TFT4MONO ((0<<5)|MQ200_FPC_TFTMONO) 393 # define MQ200_FPC_TFT12 ((0<<5)|MQ200_FPC_TFTCOLOR) 394 # define MQ200_FPC_SSTN4 ((0<<5)|MQ200_FPC_SSTNCOLOR) 395 # define MQ200_FPC_DSTN8 ((0<<5)|MQ200_FPC_DSTNCOLOR) 396 # define MQ200_FPC_TFT6MONO ((1<<5)|MQ200_FPC_TFTMONO) 397 # define MQ200_FPC_TFT18 ((1<<5)|MQ200_FPC_TFTCOLOR) 398 # define MQ200_FPC_SSTN8 ((1<<5)|MQ200_FPC_SSTNCOLOR) 399 # define MQ200_FPC_DSTN16 ((1<<5)|MQ200_FPC_DSTNCOLOR) 400 # define MQ200_FPC_TFT8MONO ((2<<5)|MQ200_FPC_TFTMONO) 401 # define MQ200_FPC_TFT24 ((2<<5)|MQ200_FPC_TFTCOLOR) 402 # define MQ200_FPC_SSTN12 ((2<<5)|MQ200_FPC_SSTNCOLOR) 403 # define MQ200_FPC_DSTN24 ((2<<5)|MQ200_FPC_DSTNCOLOR) 404 # define MQ200_FPC_SSTN16 ((3<<5)|MQ200_FPC_SSTNCOLOR) 405 # define MQ200_FPC_SSTN24 ((4<<5)|MQ200_FPC_SSTNCOLOR) 406 # define MQ200_FPC_DITH_DISABLE (0<<8) 407 # define MQ200_FPC_DITH_PTRN1 (1<<8) 408 # define MQ200_FPC_DITH_PTRN2 (2<<8) 409 # define MQ200_FPC_DITH_PTRN3 (3<<8) 410 /* bits 11-10 are reserved */ 411 # define MQ200_FPC_DITH_BC_MASK 0x00007000 412 # define MQ200_FPC_DITH_BC_SHIFT 12 413 # define MQ200_FPC_FRC_DISABLE_ALTWIN (1<<15) 414 # define MQ200_FPC_FRC_2LEVEL (0<<16) 415 # define MQ200_FPC_FRC_4LEVEL (1<<16) 416 # define MQ200_FPC_FRC_8LEVEL (2<<16) 417 # define MQ200_FPC_FRC_16LEVEL (3<<16) 418 # define MQ200_FPC_DITH_ADJ_MASK 0x0ffc0000 419 # define MQ200_FPC_DITH_ADJ_SHIFT 18 420 # define MQ200_FPC_DITH_ADJ_VAL 0x018 421 # define MQ200_FPC_DITH_ADJ1_MASK 0x00fc0000 422 # define MQ200_FPC_DITH_ADJ1_SHIFT 18 423 # define MQ200_FPC_DITH_ADJ1_VAL 0x18 424 # define MQ200_FPC_DITH_ADJ2_MASK 0x07000000 425 # define MQ200_FPC_DITH_ADJ2_SHIFT 24 426 # define MQ200_FPC_DITH_ADJ2_VAL 0x0 427 # define MQ200_FPC_DITH_ADJ3_MASK 0x08000000 428 # define MQ200_FPC_DITH_ADJ3_SHIFT 27 429 # define MQ200_FPC_DITH_ADJ3_VAL 0x0 430 # define MQ200_FPC_TESTMODE0 (1<<28) 431 # define MQ200_FPC_TESTMODE1 (1<<29) 432 # define MQ200_FPC_TESTMODE2 (1<<30) 433 # define MQ200_FPC_TESTMODE3 (1<<31) 434 435 /* FP Output Pin Control (FP01R) */ 436 #define MQ200_FPPCR MQ200_FPR(1) 437 # define MQ200_FPPC_PIN_LOW (1<<0) 438 # define MQ200_FPPC_INVERSION_EN (1<<1) 439 # define MQ200_FPPC_FDE_COMPOSITE (0<<2) 440 # define MQ200_FPPC_FDE_HORIZONTAL (1<<2) 441 # define MQ200_FPPC_FDE_FMOD_EN (1<<3) 442 # define MQ200_FPPC_FD2_DATAK (0<<4) 443 # define MQ200_FPPC_FD2_SHIFTCLK (1<<4) 444 # define MQ200_FPPC_FSCLK_EN (1<<5) 445 # define MQ200_FPPC_SHIFTCLK_DIV2 (1<<6) 446 # define MQ200_FPPC_SHIFTCLK_MASK (1<<7) 447 # define MQ200_FPPC_STNLP_BLANK (1<<8) 448 # define MQ200_FPPC_SHIFTCLK_BLANK (1<<9) 449 # define MQ200_FPPC_STNEXLP_EN (1<<10) 450 /* bit 11 is reserved */ 451 # define MQ200_FPPC_FD2_MAX (0<<12) 452 # define MQ200_FPPC_FD2_MID (1<<12) 453 # define MQ200_FPPC_FD2_MID2 (2<<12) 454 # define MQ200_FPPC_FD2_MIN (3<<12) 455 # define MQ200_FPPC_DRV_MAX (0<<12) 456 # define MQ200_FPPC_DRV_MID (1<<12) 457 # define MQ200_FPPC_DRV_MID2 (2<<12) 458 # define MQ200_FPPC_DRV_MIN (3<<12) 459 # define MQ200_FPPC_FD2_ACTVHIGH (0<<16) 460 # define MQ200_FPPC_FD2_ACTVLOW (1<<16) 461 # define MQ200_FPPC_ACTVHIGH (0<<17) 462 # define MQ200_FPPC_ACTVLOW (1<<17) 463 # define MQ200_FPPC_FDE_ACTVHIGH (0<<18) 464 # define MQ200_FPPC_FDE_ACTVLOW (1<<18) 465 # define MQ200_FPPC_FHSYNC_ACTVHIGH (0<<19) 466 # define MQ200_FPPC_FHSYNC_ACTVLOW (1<<19) 467 # define MQ200_FPPC_FVSYNC_ACTVHIGH (0<<20) 468 # define MQ200_FPPC_FVSYNC_ACTVLOW (1<<20) 469 # define MQ200_FPPC_FSCLK_ACTVHIGH (0<<21) 470 # define MQ200_FPPC_FSCLK_ACTVLOW (1<<21) 471 # define MQ200_FPPC_FSCLK_MAX (0<<22) 472 # define MQ200_FPPC_FSCLK_MID (1<<22) 473 # define MQ200_FPPC_FSCLK_MID2 (2<<22) 474 # define MQ200_FPPC_FSCLK_MIN (3<<22) 475 # define MQ200_FPPC_FSCLK_DELAY_MASK 0x07000000 476 # define MQ200_FPPC_FSCLK_DELAY_SHIFT 24 477 /* bits 31-27 are reserved */ 478 479 /* FP General Purpose Output Port Control (FP02R) */ 480 #define MQ200_FPGPOCR MQ200_FPR(2) 481 # define MQ200_FPGPOC_ENCTL_EN (0<<0) 482 # define MQ200_FPGPOC_GPO0_EN (1<<0) 483 # define MQ200_FPGPOC_OSCCLK_EN (2<<0) 484 # define MQ200_FPGPOC_PLL3_EN (3<<0) 485 # define MQ200_FPGPOC_ENVEE_EN (0<<2) 486 # define MQ200_FPGPOC_GPO1_EN (1<<2) 487 # define MQ200_FPGPOC_PWM0_EN (0<<4) 488 # define MQ200_FPGPOC_GPO2_EN (1<<4) 489 # define MQ200_FPGPOC_PWM1_EN (0<<6) 490 # define MQ200_FPGPOC_GPO3_EN (1<<6) 491 # define MQ200_FPGPOC_ENVDD_EN (0<<8) 492 # define MQ200_FPGPOC_GPO4_EN (1<<9) 493 # define MQ200_FPGPOC_PWM_MAX (0<<10) 494 # define MQ200_FPGPOC_PWM_MID (1<<10) 495 # define MQ200_FPGPOC_PWM_MID2 (2<<10) 496 # define MQ200_FPGPOC_PWM_MIN (3<<10) 497 # define MQ200_FPGPOC_GPO_MAX (0<<12) 498 # define MQ200_FPGPOC_GPO_MID (1<<12) 499 # define MQ200_FPGPOC_GPO_MID2 (2<<12) 500 # define MQ200_FPGPOC_GPO_MIN (3<<12) 501 # define MQ200_FPGPOC_DRV_MAX (0<<14) 502 # define MQ200_FPGPOC_DRV_MID (1<<14) 503 # define MQ200_FPGPOC_DRV_MID2 (2<<14) 504 # define MQ200_FPGPOC_DRV_MIN (3<<14) 505 # define MQ200_FPGPOC_GPO0 (1<<16) 506 # define MQ200_FPGPOC_GPO1 (1<<17) 507 # define MQ200_FPGPOC_GPO2 (1<<18) 508 # define MQ200_FPGPOC_GPO3 (1<<19) 509 # define MQ200_FPGPOC_GPO4 (1<<20) 510 /* bits 31-21 are reserved */ 511 512 /* FP General Purpose I/O Port Control (FP03R) */ 513 #define MQ200_FPGPOICR MQ200_FPR(3) 514 # define MQ200_FPGPIOC_INPUT0_EN (0<<0) 515 # define MQ200_FPGPIOC_OUTPUT0_EN (1<<0 516 # define MQ200_FPGPIOC_PLL1_EN (2<<0) 517 # define MQ200_FPGPIOC_CRCBLUE_EN (3<<0) 518 # define MQ200_FPGPIOC_INPUT1_EN (0<<2) 519 # define MQ200_FPGPIOC_OUTPUT1_EN (1<<2 520 # define MQ200_FPGPIOC_PLL2_EN (2<<2) 521 # define MQ200_FPGPIOC_CRCGREEN_EN (3<<2) 522 # define MQ200_FPGPIOC_INPUT2_EN (0<<4) 523 # define MQ200_FPGPIOC_OUTPUT2_EN (1<<4 524 # define MQ200_FPGPIOC_PMCLK_EN (2<<4) 525 # define MQ200_FPGPIOC_CRCRED_EN (3<<4) 526 /* bits 15-6 are reserved */ 527 # define MQ200_FPGPIOC_OUTPUT0 (1<<16) 528 # define MQ200_FPGPIOC_OUTPUT1 (1<<17) 529 # define MQ200_FPGPIOC_OUTPUT2 (1<<18) 530 /* bits 23-19 are reserved */ 531 # define MQ200_FPGPIOC_INPUT0 (1<<24) 532 # define MQ200_FPGPIOC_INPUT1 (1<<25) 533 # define MQ200_FPGPIOC_INPUT2 (1<<26) 534 /* bits 31-27 are reserved */ 535 536 /* FP STN Panel Control (FP04R) */ 537 #define MQ200_FPSTNCR MQ200_FPR(4) 538 # define MQ200_FPSTNC_FRCPRM0_MASK 0x000000ff 539 # define MQ200_FPSTNC_FRCPRM0_SHIFT 0 540 # define MQ200_FPSTNC_FRCPRM1_MASK 0x0000ff00 541 # define MQ200_FPSTNC_FRCPRM1_SHIFT 8 542 # define MQ200_FPSTNC_FRCPRM2_MASK 0x00ff0000 543 # define MQ200_FPSTNC_FRCPRM2_SHIFT 16 544 # define MQ200_FPSTNC_FMOD_MASK 0x7f000000 545 # define MQ200_FPSTNC_FMOD_SHIFT 24 546 # define MQ200_FPSTNC_FMOD_FRAMECLK (0<<31) 547 # define MQ200_FPSTNC_FMOD_LINECLK (0<<31) 548 549 /* FP D-STN Half-Frame Buffer Control (FP05R) */ 550 #define MQ200_FPHFBCR MQ200_FPR(5) 551 # define MQ200_FPHFBC_START_MASK 0x00003fff 552 # define MQ200_FPHFBC_START_SHIFT -7 /* XXX, does this work? */ 553 /* bits 15-14 are reserved */ 554 # define MQ200_FPHFBC_END_MASK 0xffff0000 555 # define MQ200_FPHFBC_END_SHIFT (16-4) /* XXX, does this work? */ 556 557 /* FP Pulse Width Modulation Control (FP0FR) */ 558 #define MQ200_FPPWMCR MQ200_FPR(0xf) 559 # define MQ200_FPPWMC_PWM0_OSCCLK (0<<0) 560 # define MQ200_FPPWMC_PWM0_BUSCLK (1<<0) 561 # define MQ200_FPPWMC_PWM0_PMCLK (2<<0) 562 # define MQ200_FPPWMC_PWM0_PWSEQ_EN (0<<2) 563 # define MQ200_FPPWMC_PWM0_PWSEQ_DISABLE (1<<2) 564 /* bit 3 is reserved */ 565 # define MQ200_FPPWMC_PWM0_DIV_MASK 0x000000f0 566 # define MQ200_FPPWMC_PWM0_DIV_SHIFT 4 567 # define MQ200_FPPWMC_PWM0_DCYCLE_MASK 0x0000ff00 568 # define MQ200_FPPWMC_PWM0_DCYCLE_SHIFT 8 569 # define MQ200_FPPWMC_PWM1_OSCCLK (0<<16) 570 # define MQ200_FPPWMC_PWM1_BUSCLK (1<<16) 571 # define MQ200_FPPWMC_PWM1_PMCLK (2<<16) 572 # define MQ200_FPPWMC_PWM1_PWSEQ_EN (0<<18) 573 # define MQ200_FPPWMC_PWM1_PWSEQ_DISABLE (1<<18) 574 /* bit 19 is reserved */ 575 # define MQ200_FPPWMC_PWM1_DIV_MASK 0x00f00000 576 # define MQ200_FPPWMC_PWM1_DIV_SHIFT 20 577 # define MQ200_FPPWMC_PWM1_DCYCLE_MASK 0xff000000 578 # define MQ200_FPPWMC_PWM1_DCYCLE_SHIFT 24 579 580 /* FP Frame Rate Control Pattern (FP10R to FP2FR) */ 581 #define MQ200_FPFRCPR(n) MQ200_FPR(0x10+n) 582 583 /* FP Frame Rate Control Weight (FP30R to FP37R) */ 584 #define MQ200_FPFRCWR(n) MQ200_FPR(0x30+n) 585 586 /* 587 * Color Palette 1 588 */ 589 #define MQ200_CP(cp, idx) (MQ200_CP1 + (idx) * 4) */ 590 # define MQ200_GC_BLUE_MASK 0x00ff0000 591 # define MQ200_GC_BLUE_SHIFT 16 592 # define MQ200_GC_GREEN_MASK 0x0000ff00 593 # define MQ200_GC_GREEN_SHIFT 8 594 # define MQ200_GC_RED_MASK 0x000000ff 595 # define MQ200_GC_RED_SHIFT 0 596 # define MQ200_GC_RGB(r, g, b) \ 597 (((((unsigned long)(r))&0xff)<<0) | \ 598 ((((unsigned long)(g))&0xff)<<8) | \ 599 ((((unsigned long)(b))&0xff)<<16)) 600 601 /* 602 * Device Configration 603 */ 604 605 /* 606 * PCI configuration space 607 */ 608 #define MQ200_PC00R (MQ200_PC+0x00) /* device/vendor ID */ 609 #define MQ200_PC04R (MQ200_PC+0x04) /* command/status */ 610 #define MQ200_PC08R (MQ200_PC+0x04) /* calss code/revision */ 611 612 #define MQ200_PMR (MQ200_PC+0x40) /* power management */ 613 #define MQ200_PMCSR (MQ200_PC+0x44) /* control/status */ 614 615 /* 616 * Power Management 617 */ 618 #define MQ200_PMCR (MQ200_PM + 0x00) 619 # define MQ200_PMC_PLL1_N (1<<0) 620 # define MQ200_PMC_PLL2_ENABLE (1<<2) 621 # define MQ200_PMC_PLL3_ENABLE (1<<3) 622 # define MQ200_PMC_IMMEDIATELY (1<<5) 623 # define MQ200_PMC_GE_ENABLE (1<<8) 624 # define MQ200_PMC_GE_FORCE_BUSY (1<<9) 625 # define MQ200_PMC_GE_FORCE_BUSY_LOCAL (1<<10) 626 # define MQ200_PMC_GE_CLK_MASK 0x00001800 627 # define MQ200_PMC_GE_CLK_SHIFT 11 628 # define MQ200_PMC_GE_CLK_BUS (0<<11) 629 # define MQ200_PMC_GE_CLK_PLL1 (1<<11) 630 # define MQ200_PMC_GE_CLK_PLL2 (2<<11) 631 # define MQ200_PMC_GE_CLK_PLL3 (3<<11) 632 # define MQ200_PMC_GE_COMMAND_RESET (1<<13) 633 # define MQ200_PMC_GE_SOURCE_RESET (1<<14) 634 # define MQ200_PMC_MIU_SEQ_ENABLE (1<<15) 635 # define MQ200_PMC_D3_REFRESH (1<<16) 636 # define MQ200_PMC_D4_REFRESH (1<<17) 637 # define MQ200_PMC_SEQINTVL_MASK (3<<18) 638 # define MQ200_PMC_SEQINTVL_SHIFT 18 639 # define MQ200_PMC_SEQINTVL_4 (0<<18) 640 # define MQ200_PMC_SEQINTVL_8 (0<<18) 641 # define MQ200_PMC_SEQINTVL_16 (0<<18) 642 # define MQ200_PMC_SEQINTVL_2048 (0<<18) 643 # define MQ200_PMC_FP_SEQINTVL_MASK (3<<20) 644 # define MQ200_PMC_FP_SEQINTVL_SHIFT 20 645 # define MQ200_PMC_FP_SEQINTVL_512 (0<<20) 646 # define MQ200_PMC_FP_SEQINTVL_1024 (1<<20) 647 # define MQ200_PMC_FP_SEQINTVL_2048 (2<<20) 648 # define MQ200_PMC_FP_SEQINTVL_128K (3<<20) 649 # define MQ200_PMC_SEQINTVL_ALL (1<<22) 650 # define MQ200_PMC_TESTMODE (1<<23) 651 # define MQ200_PMC_STATE_MASK (3<<24) 652 # define MQ200_PMC_STATE_SHIFT 24 653 # define MQ200_PMC_SEQPROGRESS (1<<26) 654 #define MQ200_PMD1CR (MQ200_PM + 0x04) 655 #define MQ200_PMD2CR (MQ200_PM + 0x08) 656 657 #define MQ200_DCMISCR (MQ200_DC + 0x00) 658 # define MQ200_DCMISC_OSC_BYPASS (1<<0) 659 # define MQ200_DCMISC_OSC_ENABLE (1<<1) 660 # define MQ200_DCMISC_PLL1_BYPASS (1<<2) 661 # define MQ200_DCMISC_PLL1_ENABLE (1<<3) 662 # define MQ200_DCMISC_SA_SLOWBUS (1<<13) 663 # define MQ200_DCMISC_CHIP_RESET (1<<14) 664 # define MQ200_DCMISC_MEMSTANDBY_DISABLE (1<<15) 665 # define MQ200_DCMISC_OSCSHAPER_DISABLE (1<<24) 666 # define MQ200_DCMISC_FASTPOWSEQ_DISABLE (1<<25) 667 # define MQ200_DCMISC_OSCFREQ_MASK (3<<26) 668 # define MQ200_DCMISC_OSCFREQ_12_25 (3<<26) 669 670 /* 671 * Fout = Fref*(M+1)/(N+1)/(2^P) 672 * Fout: PLL output frequency 673 * Fref: reference frequency(internal oscillator or external clock) 674 */ 675 #define MQ200_PLL1R (MQ200_DC + 0x00) 676 #define MQ200_PLL2R (MQ200_PM + 0x18) 677 #define MQ200_PLL3R (MQ200_PM + 0x1c) 678 #define MQ200_PLL_EXTCLK (1<<0) 679 #define MQ200_PLL_BYPASS (1<<1) 680 #define MQ200_PLL_P_MASK 0x00000070 681 #define MQ200_PLL_P_SHIFT 4 682 #define MQ200_PLL_N_MASK 0x00001f00 683 #define MQ200_PLL_N_SHIFT 8 684 #define MQ200_PLL_M_MASK 0x00ff0000 685 #define MQ200_PLL_M_SHIFT 16 686 #define MQ200_PLL_PARAM_MASK (MQ200_PLL_P_MASK|MQ200_PLL_N_MASK|MQ200_PLL_M_MASK) 687 #define MQ200_PLL_TRIM_MASK 0xf0000000 688 #define MQ200_PLL_TRIM_SHIFT 28 689
Indexes created Tue Oct 21 06:10:07 GMT 2025