mq200reg.h revision 1.3
1 /* $NetBSD: mq200reg.h,v 1.3 2000/12/03 13:24:33 takemura Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Takemura Shin 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #define MQ200_VENDOR_ID 0x4d51 33 #define MQ200_PRODUCT_ID 0x0200 34 #define MQ200_MAPSIZE 0x800000 35 36 #define MQ200_POWERSTATE_D0 0 37 #define MQ200_POWERSTATE_D1 1 38 #define MQ200_POWERSTATE_D2 2 39 #define MQ200_POWERSTATE_D3 3 40 41 #define MQ200_FRAMEBUFFER 0x000000 /* frame buffer base address */ 42 #define MQ200_PM 0x600000 /* power management */ 43 #define MQ200_CC 0x602000 /* CPU interface */ 44 #define MQ200_MM 0x604000 /* memory interface unit */ 45 #define MQ200_IN 0x608000 /* interrupt controller */ 46 #define MQ200_GC(n) (0x60a000+0x80*(n)) 47 #define MQ200_GC1 0x60a000 /* graphice controller 1*/ 48 #define MQ200_GC2 0x60a080 /* graphice controller 1*/ 49 #define MQ200_GE 0x60c000 /* graphics engine */ 50 #define MQ200_FP 0x60e000 /* flat panel controller*/ 51 #define MQ200_CP1 0x610000 /* color palette 1 */ 52 #define MQ200_DC 0x614000 /* device configration */ 53 #define MQ200_PC 0x616000 /* PCI configration */ 54 55 /* 56 * Power Management 57 */ 58 59 /* 60 * CPU Interface 61 */ 62 63 /* 64 * Memory Interface Unit 65 */ 66 67 /* 68 * Interrupt Controller 69 */ 70 71 /* 72 * Graphics Controller 1/2 73 */ 74 #define MQ200_GCR(n) (MQ200_GC1+(n)*4) 75 /* GC Control (GC00R and GC20R) */ 76 #define MQ200_GCCR(n) (MQ200_GC(n)+0x00) 77 # define MQ200_GCC_ENABLE (1<<0) 78 # define MQ200_GCC_HCRESET (1<<1) 79 # define MQ200_GCC_VCRESET (1<<2) 80 # define MQ200_GCC_WINEN (1<<3) 81 # define MQ200_GCC_DEPTH_SHIFT 4 82 # define MQ200_GCC_DEPTH_MASK 0x000000f0 83 # define MQ200_GCC_HCEN (1<<8) 84 /* bits 10-9 is reserved */ 85 # define MQ200_GCC_ALTEN (1<<11) 86 # define MQ200_GCC_ALTDEPTH_SHIFT 12 87 # define MQ200_GCC_ALTDEPTH_MASK 0x0000f000 88 # define MQ200_GCC_RCLK_SHIFT 16 89 # define MQ200_GCC_RCLK_MASK 0x00030000 90 # define MQ200_GCC_RCLK_BUS 0x00000000 91 # define MQ200_GCC_RCLK_PLL1 0x00010000 92 # define MQ200_GCC_RCLK_PLL2 0x00020000 93 # define MQ200_GCC_RCLK_PLL3 0x00030000 94 # define MQ200_GCC_TESTMODE0 (1<<18) 95 # define MQ200_GCC_TESTMODE1 (1<<19) 96 /* FD(first clock divisor) is 1, 1.5, 2.5, 3.5, 4.5, 5.6 or 6.5 */ 97 # define MQ200_GCC_MCLK_FD_SHIFT 20 98 # define MQ200_GCC_MCLK_FD_MASK 0x00700000 99 # define MQ200_GCC_MCLK_FD_1 0x00000000 100 # define MQ200_GCC_MCLK_FD_1_5 0x00100000 101 # define MQ200_GCC_MCLK_FD_2_5 0x00200000 102 # define MQ200_GCC_MCLK_FD_3_5 0x00300000 103 # define MQ200_GCC_MCLK_FD_4_5 0x00400000 104 # define MQ200_GCC_MCLK_FD_5_5 0x00500000 105 # define MQ200_GCC_MCLK_FD_6_5 0x00600000 106 /* bit 23 is reserved */ 107 /* SD(second close divisor) is 1-255. 0 means disable */ 108 # define MQ200_GCC_MCLK_SD_SHIFT 24 109 # define MQ200_GCC_MCLK_SD_MASK 0xff000000 110 /* GCCR_DEPTH and GCCR_ALTDEPTH values */ 111 # define MQ200_GCC_1BPP 0x0 112 # define MQ200_GCC_2BPP 0x1 113 # define MQ200_GCC_4BPP 0x2 114 # define MQ200_GCC_8BPP 0x3 115 # define MQ200_GCC_16BPP 0x4 116 # define MQ200_GCC_24BPP 0x5 117 # define MQ200_GCC_ARGB888 0x6 118 # define MQ200_GCC_PALBGR 0x6 119 # define MQ200_GCC_ABGR888 0x7 120 # define MQ200_GCC_PALRGB 0x7 121 # define MQ200_GCC_16BPP_DIRECT 0xc 122 # define MQ200_GCC_24BPP_DIRECT 0xd 123 # define MQ200_GCC_ARGB888_DIRECT 0xe 124 # define MQ200_GCC_PALBGR_DIRECT 0xe 125 # define MQ200_GCC_ABGR888_DIRECT 0xf 126 # define MQ200_GCC_PALRGB_DIRECT 0xf 127 128 /* GC CRT Control (GC1only) */ 129 #define MQ200_GC1CRTCR MQ200_GCR(0x01) 130 # define MQ200_GC1CRTC_DACEN (1<<0) 131 # define MQ200_GC1CRTC_HSYNC_PMCLK (1<<2) 132 # define MQ200_GC1CRTC_VSYNC_PMCLK (1<<3) 133 # define MQ200_GC1CRTC_HSYNC_PMMASK 0x00000030 134 # define MQ200_GC1CRTC_HSYNC_PMNORMAL 0x00000000 135 # define MQ200_GC1CRTC_HSYNC_PMLOW 0x00000010 136 # define MQ200_GC1CRTC_HSYNC_PMHIGH 0x00000020 137 # define MQ200_GC1CRTC_VSYNC_PMMASK 0x000000c0 138 # define MQ200_GC1CRTC_VSYNC_PMNORMAL 0x00000000 139 # define MQ200_GC1CRTC_VSYNC_PMLOW 0x00000040 140 # define MQ200_GC1CRTC_VSYNC_PMHIGH 0x00000080 141 # define MQ200_GC1CRTC_HSYNC_ACTVHIGH (0<<8) 142 # define MQ200_GC1CRTC_HSYNC_ACTVLOW (1<<8) 143 # define MQ200_GC1CRTC_VSYNC_ACTVHIGH (0<<9) 144 # define MQ200_GC1CRTC_VSYNC_ACTVLOW (1<<9) 145 # define MQ200_GC1CRTC_SYNC_PEDESTAL_EN (1<<10) 146 # define MQ200_GC1CRTC_BLANK_PEDESTAL_EN (1<<11) 147 # define MQ200_GC1CRTC_COMPOSITE_SYNC_EN (1<<12) 148 # define MQ200_GC1CRTC_VREF_INTR (0<<13) 149 # define MQ200_GC1CRTC_VREF_EXTR (1<<13) 150 # define MQ200_GC1CRTC_MONITOR_SENCE_EN (1<<14) 151 # define MQ200_GC1CRTC_CONSTANT_OUTPUT_EN (1<<15) 152 # define MQ200_GC1CRTC_OUTPUT_LEVEL_MASK 0x00ff0000 153 # define MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT 16 154 # define MQ200_GC1CRTC_BLUE_NOTLOADED (1<<24) 155 # define MQ200_GC1CRTC_RED_NOTLOADED (1<<25) 156 # define MQ200_GC1CRTC_GREEN_NOTLOADED (1<<26) 157 /* bit 27 is reserved */ 158 # define MQ200_GC1CRTC_COLOR (0<<28) 159 # define MQ200_GC1CRTC_MONO (1<<28) 160 /* bits 31-29 are reserved */ 161 162 /* GC CRC Control (GC2 only) */ 163 #define MQ200_GC2CRCCR MQ200_GCR(0x21) 164 # define MQ200_GC2CRCC_ENABLE (1<<0) 165 # define MQ200_GC2CRCC_WAIT1VSYNC (0<<1) 166 # define MQ200_GC2CRCC_WAIT2VSYNC (1<<1) 167 # define MQ200_GC2CRCC_BLUE (0x0<<2) 168 # define MQ200_GC2CRCC_GREEN (0x1<<2) 169 # define MQ200_GC2CRCC_RED (0x2<<2) 170 # define MQ200_GC2CRCC_RESULT_SHIFT 8 171 # define MQ200_GC2CRCC_RESULT_MASK 0x3fffff00 172 173 /* GC Hotizontal Display Control (GC02R and GC22R) */ 174 #define MQ200_GCHDCR(n) (MQ200_GC(n)+0x08) 175 # define MQ200_GC1HDC_TOTAL_MASK 0x00000fff 176 # define MQ200_GC1HDC_TOTAL_SHIFT 0 177 /* bits 15-12 are reserved */ 178 # define MQ200_GCHDC_END_MASK 0x0fff0000 179 # define MQ200_GCHDC_END_SHIFT 16 180 /* bits 31-28 are reserved */ 181 182 /* GC Vertical Display Control (GC03R and GC23R) */ 183 #define MQ200_GCVDCR(n) (MQ200_GC(n)+0x0c) 184 # define MQ200_GCVDC_TOTAL_MASK 0x00000fff 185 # define MQ200_GCVDC_TOTAL_SHIFT 0 186 /* bits 15-12 are reserved */ 187 # define MQ200_GCVDC_END_MASK 0x0fff0000 188 # define MQ200_GCVDC_END_SHIFT 16 189 /* bits 31-28 are reserved */ 190 191 /* GC Hotizontal Sync Control (GC04R and GC24R) */ 192 #define MQ200_GCHSCR(n) (MQ200_GC(n)+0x10) 193 # define MQ200_GCHSC_START_MASK 0x00000fff 194 # define MQ200_GCHSC_START_SHIFT 0 195 /* bits 15-12 are reserved */ 196 # define MQ200_GCHSC_END_MASK 0x0fff0000 197 # define MQ200_GCHSC_END_SHIFT 16 198 /* bits 31-28 are reserved */ 199 200 /* GC Vertical Sync Control (GC05R and GC25R) */ 201 #define MQ200_GCVSCR(n) (MQ200_GC(n)+0x14) 202 # define MQ200_GCVSC_START_MASK 0x00000fff 203 # define MQ200_GCVSC_START_SHIFT 0 204 /* bits 15-12 are reserved */ 205 # define MQ200_GCVSC_END_MASK 0x0fff0000 206 # define MQ200_GCVSC_END_SHIFT 16 207 /* bits 31-28 are reserved */ 208 209 /* GC Vertical Display Count (GC07R) */ 210 #define MQ200_GC1VDCNTR MQ200_GCR(0x07) 211 # define MQ200_GC1VDCNT_MASK 0x00000fff 212 /* bits 31-12 are reserved */ 213 214 /* GC Window Horizontal Control (GC08R and GC28R) */ 215 #define MQ200_GCWHCR(n) (MQ200_GC(n)+0x20) 216 # define MQ200_GCWHC_START_MASK 0x00000fff 217 # define MQ200_GCWHC_START_SHIFT 0 218 /* bits 15-12 are reserved */ 219 # define MQ200_GCWHC_WIDTH_MASK 0x0fff0000 220 # define MQ200_GCWHC_WIDTH_SHIFT 16 221 /* ALD: Additional Line Delta (GC1 only) */ 222 # define MQ200_GC1WHC_ALD_MASK 0xf0000000 223 # define MQ200_GC1WHC_ALD_SHIFT 28 224 225 /* GC Window Vertical Control (GC09R and GC29R) */ 226 #define MQ200_GCWVCR(n) (MQ200_GC(n)+0x24) 227 # define MQ200_GCWVC_START_MASK 0x00000fff 228 # define MQ200_GCWVC_START_SHIFT 0 229 /* bits 15-12 are reserved */ 230 # define MQ200_GCWVC_HEIGHT_MASK 0x0fff0000 231 # define MQ200_GCWVC_HEIGHT_SHIFT 16 232 /* bits 31-28 are reserved */ 233 234 /* GC Altarnate Window Horizontal Control (GC0AR and GC2AR) */ 235 #define MQ200_GCAWHCR(n) (MQ200_GC(n)+0x28) 236 # define MQ200_GCAWHC_START_MASK 0x00000fff 237 # define MQ200_GCAWHC_START_SHIFT 0 238 /* bits 15-12 are reserved */ 239 # define MQ200_GCAWHC_WIDTH_MASK 0x0fff0000 240 # define MQ200_GCAWHC_WIDTH_SHIFT 16 241 /* ALD: Additional Line Delta (GC1 only) */ 242 # define MQ200_GC1AWHC_ALD_MASK 0xf0000000 243 # define MQ200_GC1AWHC_ALD_SHIFT 28 244 245 /* GC Alternate Window Vertical Control (GC0BR and GC2BR) */ 246 #define MQ200_GCAWVCR(n) (MQ200_GC(n)+0x2C) 247 # define MQ200_GCAWVC_START_MASK 0x00000fff 248 # define MQ200_GCAWVC_START_SHIFT 0 249 /* bits 15-12 are reserved */ 250 # define MQ200_GCAWVC_HEIGHT_MASK 0x0fff0000 251 # define MQ200_GCAWVC_HEIGHT_SHIFT 16 252 /* bits 31-28 are reserved */ 253 254 /* GC Window Start Address (GC0CR and GC2CR) */ 255 #define MQ200_GCWSAR(n) (MQ200_GC(n)+0x30) 256 # define MQ200_GCWSA_MASK 0x000fffff 257 /* bits 31-21 are reserved */ 258 259 /* GC Alternate Window Start Address (GC0DR and GC2DR) */ 260 #define MQ200_GCAWSAR(n) (MQ200_GC(n)+0x34) 261 # define MQ200_GCAWSA_MASK 0x000fffff 262 /* bits 24-21 are reserved */ 263 # define MQ200_GCAWPI_MASK 0xfe000000 264 # define MQ200_GCAWPI_SHIFT 24 /* XXX, 24 could be usefull 265 than 23 */ 266 267 /* GC Window Stride (GC0ER and GC2ER) */ 268 #define MQ200_GCWSTR(n) (MQ200_GC(n)+0x38) 269 # define MQ200_GCWST_MASK 0x0000ffff 270 # define MQ200_GCWST_SHIFT 0 271 # define MQ200_GCAWST_MASK 0xffff0000 272 # define MQ200_GCAWST_SHIFT 16 273 274 /* GC2 Line Size (GC2 only, GC2FR) */ 275 #define MQ200_GC2LSR MQ200_GCR(0x2f) 276 # define MQ200_GC2WLS_MASK 0x00003fff 277 # define MQ200_GC2WLS_SHIFT 0 278 # define MQ200_GC2AWLS_MASK 0x3fff0000 279 # define MQ200_GC2AWLS_SHIFT 16 280 281 282 /* GC Hardware Cursor Position (GC10R and GC30R) */ 283 #define MQ200_GCHCPR(n) (MQ200_GC(n)+0x40) 284 # define MQ200_GCHCP_HSTART_MASK 0x00000fff 285 # define MQ200_GCHCP_HSTART_SHIFT 0 286 /* bits 15-12 are reserved */ 287 # define MQ200_GCHCP_VSTART_MASK 0x0fff0000 288 # define MQ200_GCHCP_VSTART_SHIFT 16 289 /* bits 31-28 are reserved */ 290 291 /* GC Hardware Start Address and Offset (GC11R and GC31R) */ 292 #define MQ200_GCHCAOR(n) (MQ200_GC(n)+0x44) 293 # define MQ200_GCHCAO_ADDR_MASK 0x00000fff 294 # define MQ200_GCHCAO_ADDR_SHIFT 0 295 /* bits 15-12 are reserved */ 296 # define MQ200_GCHCAO_HOFFSET_MASK 0x003f0000 297 # define MQ200_GCHCAO_HOFFSET_SHIFT 16 298 /* bits 23-22 are reserved */ 299 # define MQ200_GCHCAO_VOFFSET_MASK 0x3f000000 300 # define MQ200_GCHCAO_VOFFSET_SHIFT 24 301 /* bits 31-30 are reserved */ 302 303 /* GC Hardware Cursor Foreground Color (GC13R and GC33R) */ 304 #define MQ200_GCHCFCR(n) (MQ200_GC(n)+0x48) 305 # define MQ200_GCHCFC_MASK 0x00ffffff 306 /* you can use MQ200_GC_RGB macro */ 307 /* bits 31-24 are reserved */ 308 309 /* GC Hardware Cursor Background Color (GC14R and GC34R) */ 310 #define MQ200_GCHCBCR(n) (MQ200_GC(n)+0x4c) 311 # define MQ200_GCHCBC_MASK 0x00ffffff 312 /* you can use MQ200_GC_RGB macro */ 313 /* bits 31-24 are reserved */ 314 315 #define MQ200_GC1CR MQ200_GCCR(0) 316 #define MQ200_GC1HDCR MQ200_GCHDCR(0) 317 #define MQ200_GC1VDCR MQ200_GCVDCR(0) 318 #define MQ200_GC1HSCR MQ200_GCHSCR(0) 319 #define MQ200_GC1VSCR MQ200_GCVSCR(0) 320 #define MQ200_GC1HWCR MQ200_GCHWCR(0) 321 #define MQ200_GC1VWCR MQ200_GCVWCR(0) 322 #define MQ200_GC1HAWCR MQ200_GCHAWCR(0) 323 #define MQ200_GC1AVWCR MQ200_GCAVWCR(0) 324 #define MQ200_GC1WSAR MQ200_GCWSAR(0) 325 #define MQ200_GC1AWSAR MQ200_GCAWSAR(0) 326 #define MQ200_GC1WSTR MQ200_GCWSTR(0) 327 #define MQ200_GC1HCPR MQ200_GCHCPR(0) 328 #define MQ200_GC1HCAOR MQ200_GCHCAOR(0) 329 #define MQ200_GC1HCFCR MQ200_GCHCFCR(0) 330 #define MQ200_GC1HCBCR MQ200_GCHCBCR(0) 331 332 #define MQ200_GC2CR MQ200_GCCR(1) 333 #define MQ200_GC2HDCR MQ200_GCHDCR(1) 334 #define MQ200_GC2VDCR MQ200_GCVDCR(1) 335 #define MQ200_GC2HSCR MQ200_GCHSCR(1) 336 #define MQ200_GC2VSCR MQ200_GCVSCR(1) 337 #define MQ200_GC2HWCR MQ200_GCHWCR(1) 338 #define MQ200_GC2VWCR MQ200_GCVWCR(1) 339 #define MQ200_GC2HAWCR MQ200_GCHAWCR(1) 340 #define MQ200_GC2AVWCR MQ200_GCAVWCR(1) 341 #define MQ200_GC2WSAR MQ200_GCWSAR(1) 342 #define MQ200_GC2AWSAR MQ200_GCAWSAR(1) 343 #define MQ200_GC2WSTR MQ200_GCWSTR(1) 344 #define MQ200_GC2HCPR MQ200_GCHCPR(1) 345 #define MQ200_GC2HCAOR MQ200_GCHCAOR(1) 346 #define MQ200_GC2HCFCR MQ200_GCHCFCR(1) 347 #define MQ200_GC2HCBCR MQ200_GCHCBCR(1) 348 349 /* 350 * Graphics Engine 351 */ 352 353 /* 354 * Flat Pannel Controler 355 */ 356 #define MQ200_FPR(n) (MQ200_FP + (n)*4) 357 /* FP Control (FP00R) */ 358 #define MQ200_FPCR MQ200_FPR(0) 359 # define MQ200_FPC_ENABLE (1<<0) 360 # define MQ200_FPC_GC1 (0<<1) 361 # define MQ200_FPC_GC2 (1<<1) 362 # define MQ200_FPC_TYPE_MASK 0x000000fc 363 # define MQ200_FPC_TYPE_SHIFT 2 364 365 # define MQ200_FPC_TFT (0<<2) 366 # define MQ200_FPC_SSTN (1<<2) 367 # define MQ200_FPC_DSTN (2<<2) 368 369 # define MQ200_FPC_COLOR (0<<4) 370 # define MQ200_FPC_MONO (1<<4) 371 372 # define MQ200_FPC_TFTCOLOR (MQ200_FPC_TFT|MQ200_FPC_COLOR) 373 # define MQ200_FPC_SSTNCOLOR (MQ200_FPC_SSTN|MQ200_FPC_COLOR) 374 # define MQ200_FPC_DSTNCOLOR (MQ200_FPC_DSTN|MQ200_FPC_COLOR) 375 376 # define MQ200_FPC_TFTMONO (MQ200_FPC_TFT|MQ200_FPC_MONO) 377 # define MQ200_FPC_SSTNMONO (MQ200_FPC_SSTN|MQ200_FPC_MONO) 378 # define MQ200_FPC_DSTNMONO (MQ200_FPC_DSTN|MQ200_FPC_MONO) 379 380 # define MQ200_FPC_TFT4MONO ((0<<5)|MQ200_FPC_TFTMONO) 381 # define MQ200_FPC_TFT12 ((0<<5)|MQ200_FPC_TFTCOLOR) 382 # define MQ200_FPC_SSTN4 ((0<<5)|MQ200_FPC_SSTNCOLOR) 383 # define MQ200_FPC_DSTN8 ((0<<5)|MQ200_FPC_DSTNCOLOR) 384 # define MQ200_FPC_TFT6MONO ((1<<5)|MQ200_FPC_TFTMONO) 385 # define MQ200_FPC_TFT18 ((1<<5)|MQ200_FPC_TFTCOLOR) 386 # define MQ200_FPC_SSTN8 ((1<<5)|MQ200_FPC_SSTNCOLOR) 387 # define MQ200_FPC_DSTN16 ((1<<5)|MQ200_FPC_DSTNCOLOR) 388 # define MQ200_FPC_TFT8MONO ((2<<5)|MQ200_FPC_TFTMONO) 389 # define MQ200_FPC_TFT24 ((2<<5)|MQ200_FPC_TFTCOLOR) 390 # define MQ200_FPC_SSTN12 ((2<<5)|MQ200_FPC_SSTNCOLOR) 391 # define MQ200_FPC_DSTN24 ((2<<5)|MQ200_FPC_DSTNCOLOR) 392 # define MQ200_FPC_SSTN16 ((3<<5)|MQ200_FPC_SSTNCOLOR) 393 # define MQ200_FPC_SSTN24 ((4<<5)|MQ200_FPC_SSTNCOLOR) 394 # define MQ200_FPC_DITH_DISABLE (0<<8) 395 # define MQ200_FPC_DITH_PTRN1 (1<<8) 396 # define MQ200_FPC_DITH_PTRN2 (2<<8) 397 # define MQ200_FPC_DITH_PTRN3 (3<<8) 398 /* bits 11-10 are reserved */ 399 # define MQ200_FPC_DITH_BC_MASK 0x00007000 400 # define MQ200_FPC_DITH_BC_SHIFT 12 401 # define MQ200_FPC_FRC_DISABLE_ALTWIN (1<<15) 402 # define MQ200_FPC_FRC_2LEVEL (0<<16) 403 # define MQ200_FPC_FRC_4LEVEL (1<<16) 404 # define MQ200_FPC_FRC_8LEVEL (2<<16) 405 # define MQ200_FPC_FRC_16LEVEL (3<<16) 406 # define MQ200_FPC_DITH_ADJ_MASK 0x0ffc0000 407 # define MQ200_FPC_DITH_ADJ_SHIFT 18 408 # define MQ200_FPC_DITH_ADJ_VAL 0x018 409 # define MQ200_FPC_DITH_ADJ1_MASK 0x00fc0000 410 # define MQ200_FPC_DITH_ADJ1_SHIFT 18 411 # define MQ200_FPC_DITH_ADJ1_VAL 0x18 412 # define MQ200_FPC_DITH_ADJ2_MASK 0x07000000 413 # define MQ200_FPC_DITH_ADJ2_SHIFT 24 414 # define MQ200_FPC_DITH_ADJ2_VAL 0x0 415 # define MQ200_FPC_DITH_ADJ3_MASK 0x08000000 416 # define MQ200_FPC_DITH_ADJ3_SHIFT 27 417 # define MQ200_FPC_DITH_ADJ3_VAL 0x0 418 # define MQ200_FPC_TESTMODE0 (1<<28) 419 # define MQ200_FPC_TESTMODE1 (1<<29) 420 # define MQ200_FPC_TESTMODE2 (1<<30) 421 # define MQ200_FPC_TESTMODE3 (1<<31) 422 423 /* FP Output Pin Control (FP01R) */ 424 #define MQ200_FPPCR MQ200_FPR(1) 425 # define MQ200_FPPC_PIN_LOW (1<<0) 426 # define MQ200_FPPC_INVERSION_EN (1<<1) 427 # define MQ200_FPPC_FDE_COMPOSITE (0<<2) 428 # define MQ200_FPPC_FDE_HORIZONTAL (1<<2) 429 # define MQ200_FPPC_FDE_FMOD_EN (1<<3) 430 # define MQ200_FPPC_FD2_DATAK (0<<4) 431 # define MQ200_FPPC_FD2_SHIFTCLK (1<<4) 432 # define MQ200_FPPC_FSCLK_EN (1<<5) 433 # define MQ200_FPPC_SHIFTCLK_DIV2 (1<<6) 434 # define MQ200_FPPC_SHIFTCLK_MASK (1<<7) 435 # define MQ200_FPPC_STNLP_BLANK (1<<8) 436 # define MQ200_FPPC_SHIFTCLK_BLANK (1<<9) 437 # define MQ200_FPPC_STNEXLP_EN (1<<10) 438 /* bit 11 is reserved */ 439 # define MQ200_FPPC_FD2_MAX (0<<12) 440 # define MQ200_FPPC_FD2_MID (1<<12) 441 # define MQ200_FPPC_FD2_MID2 (2<<12) 442 # define MQ200_FPPC_FD2_MIN (3<<12) 443 # define MQ200_FPPC_DRV_MAX (0<<12) 444 # define MQ200_FPPC_DRV_MID (1<<12) 445 # define MQ200_FPPC_DRV_MID2 (2<<12) 446 # define MQ200_FPPC_DRV_MIN (3<<12) 447 # define MQ200_FPPC_FD2_ACTVHIGH (0<<16) 448 # define MQ200_FPPC_FD2_ACTVLOW (1<<16) 449 # define MQ200_FPPC_ACTVHIGH (0<<17) 450 # define MQ200_FPPC_ACTVLOW (1<<17) 451 # define MQ200_FPPC_FDE_ACTVHIGH (0<<18) 452 # define MQ200_FPPC_FDE_ACTVLOW (1<<18) 453 # define MQ200_FPPC_FHSYNC_ACTVHIGH (0<<19) 454 # define MQ200_FPPC_FHSYNC_ACTVLOW (1<<19) 455 # define MQ200_FPPC_FVSYNC_ACTVHIGH (0<<20) 456 # define MQ200_FPPC_FVSYNC_ACTVLOW (1<<20) 457 # define MQ200_FPPC_FSCLK_ACTVHIGH (0<<21) 458 # define MQ200_FPPC_FSCLK_ACTVLOW (1<<21) 459 # define MQ200_FPPC_FSCLK_MAX (0<<22) 460 # define MQ200_FPPC_FSCLK_MID (1<<22) 461 # define MQ200_FPPC_FSCLK_MID2 (2<<22) 462 # define MQ200_FPPC_FSCLK_MIN (3<<22) 463 # define MQ200_FPPC_FSCLK_DELAY_MASK 0x07000000 464 # define MQ200_FPPC_FSCLK_DELAY_SHIFT 24 465 /* bits 31-27 are reserved */ 466 467 /* FP General Purpose Output Port Control (FP02R) */ 468 #define MQ200_FPGPOCR MQ200_FPR(2) 469 # define MQ200_FPGPOC_ENCTL_EN (0<<0) 470 # define MQ200_FPGPOC_GPO0_EN (1<<0) 471 # define MQ200_FPGPOC_OSCCLK_EN (2<<0) 472 # define MQ200_FPGPOC_PLL3_EN (3<<0) 473 # define MQ200_FPGPOC_ENVEE_EN (0<<2) 474 # define MQ200_FPGPOC_GPO1_EN (1<<2) 475 # define MQ200_FPGPOC_PWM0_EN (0<<4) 476 # define MQ200_FPGPOC_GPO2_EN (1<<4) 477 # define MQ200_FPGPOC_PWM1_EN (0<<6) 478 # define MQ200_FPGPOC_GPO3_EN (1<<6) 479 # define MQ200_FPGPOC_ENVDD_EN (0<<8) 480 # define MQ200_FPGPOC_GPO4_EN (1<<9) 481 # define MQ200_FPGPOC_PWM_MAX (0<<10) 482 # define MQ200_FPGPOC_PWM_MID (1<<10) 483 # define MQ200_FPGPOC_PWM_MID2 (2<<10) 484 # define MQ200_FPGPOC_PWM_MIN (3<<10) 485 # define MQ200_FPGPOC_GPO_MAX (0<<12) 486 # define MQ200_FPGPOC_GPO_MID (1<<12) 487 # define MQ200_FPGPOC_GPO_MID2 (2<<12) 488 # define MQ200_FPGPOC_GPO_MIN (3<<12) 489 # define MQ200_FPGPOC_DRV_MAX (0<<14) 490 # define MQ200_FPGPOC_DRV_MID (1<<14) 491 # define MQ200_FPGPOC_DRV_MID2 (2<<14) 492 # define MQ200_FPGPOC_DRV_MIN (3<<14) 493 # define MQ200_FPGPOC_GPO0 (1<<16) 494 # define MQ200_FPGPOC_GPO1 (1<<17) 495 # define MQ200_FPGPOC_GPO2 (1<<18) 496 # define MQ200_FPGPOC_GPO3 (1<<19) 497 # define MQ200_FPGPOC_GPO4 (1<<20) 498 /* bits 31-21 are reserved */ 499 500 /* FP General Purpose I/O Port Control (FP03R) */ 501 #define MQ200_FPGPOICR MQ200_FPR(3) 502 # define MQ200_FPGPIOC_INPUT0_EN (0<<0) 503 # define MQ200_FPGPIOC_OUTPUT0_EN (1<<0 504 # define MQ200_FPGPIOC_PLL1_EN (2<<0) 505 # define MQ200_FPGPIOC_CRCBLUE_EN (3<<0) 506 # define MQ200_FPGPIOC_INPUT1_EN (0<<2) 507 # define MQ200_FPGPIOC_OUTPUT1_EN (1<<2 508 # define MQ200_FPGPIOC_PLL2_EN (2<<2) 509 # define MQ200_FPGPIOC_CRCGREEN_EN (3<<2) 510 # define MQ200_FPGPIOC_INPUT2_EN (0<<4) 511 # define MQ200_FPGPIOC_OUTPUT2_EN (1<<4 512 # define MQ200_FPGPIOC_PMCLK_EN (2<<4) 513 # define MQ200_FPGPIOC_CRCRED_EN (3<<4) 514 /* bits 15-6 are reserved */ 515 # define MQ200_FPGPIOC_OUTPUT0 (1<<16) 516 # define MQ200_FPGPIOC_OUTPUT1 (1<<17) 517 # define MQ200_FPGPIOC_OUTPUT2 (1<<18) 518 /* bits 23-19 are reserved */ 519 # define MQ200_FPGPIOC_INPUT0 (1<<24) 520 # define MQ200_FPGPIOC_INPUT1 (1<<25) 521 # define MQ200_FPGPIOC_INPUT2 (1<<26) 522 /* bits 31-27 are reserved */ 523 524 /* FP STN Panel Control (FP04R) */ 525 #define MQ200_FPSTNCR MQ200_FPR(4) 526 # define MQ200_FPSTNC_FRCPRM0_MASK 0x000000ff 527 # define MQ200_FPSTNC_FRCPRM0_SHIFT 0 528 # define MQ200_FPSTNC_FRCPRM1_MASK 0x0000ff00 529 # define MQ200_FPSTNC_FRCPRM1_SHIFT 8 530 # define MQ200_FPSTNC_FRCPRM2_MASK 0x00ff0000 531 # define MQ200_FPSTNC_FRCPRM2_SHIFT 16 532 # define MQ200_FPSTNC_FMOD_MASK 0x7f000000 533 # define MQ200_FPSTNC_FMOD_SHIFT 24 534 # define MQ200_FPSTNC_FMOD_FRAMECLK (0<<31) 535 # define MQ200_FPSTNC_FMOD_LINECLK (0<<31) 536 537 /* FP D-STN Half-Frame Buffer Control (FP05R) */ 538 #define MQ200_FPHFBCR MQ200_FPR(5) 539 # define MQ200_FPHFBC_START_MASK 0x00003fff 540 # define MQ200_FPHFBC_START_SHIFT -7 /* XXX, does this work? */ 541 /* bits 15-14 are reserved */ 542 # define MQ200_FPHFBC_END_MASK 0xffff0000 543 # define MQ200_FPHFBC_END_SHIFT (16-4) /* XXX, does this work? */ 544 545 /* FP Pulse Width Modulation Control (FP0FR) */ 546 #define MQ200_FPPWMCR MQ200_FPR(0xf) 547 # define MQ200_FPPWMC_PWM0_OSCCLK (0<<0) 548 # define MQ200_FPPWMC_PWM0_BUSCLK (1<<0) 549 # define MQ200_FPPWMC_PWM0_PMCLK (2<<0) 550 # define MQ200_FPPWMC_PWM0_PWSEQ_EN (0<<2) 551 # define MQ200_FPPWMC_PWM0_PWSEQ_DISABLE (1<<2) 552 /* bit 3 is reserved */ 553 # define MQ200_FPPWMC_PWM0_DIV_MASK 0x000000f0 554 # define MQ200_FPPWMC_PWM0_DIV_SHIFT 4 555 # define MQ200_FPPWMC_PWM0_DCYCLE_MASK 0x0000ff00 556 # define MQ200_FPPWMC_PWM0_DCYCLE_SHIFT 8 557 # define MQ200_FPPWMC_PWM1_OSCCLK (0<<16) 558 # define MQ200_FPPWMC_PWM1_BUSCLK (1<<16) 559 # define MQ200_FPPWMC_PWM1_PMCLK (2<<16) 560 # define MQ200_FPPWMC_PWM1_PWSEQ_EN (0<<18) 561 # define MQ200_FPPWMC_PWM1_PWSEQ_DISABLE (1<<18) 562 /* bit 19 is reserved */ 563 # define MQ200_FPPWMC_PWM1_DIV_MASK 0x00f00000 564 # define MQ200_FPPWMC_PWM1_DIV_SHIFT 20 565 # define MQ200_FPPWMC_PWM1_DCYCLE_MASK 0xff000000 566 # define MQ200_FPPWMC_PWM1_DCYCLE_SHIFT 24 567 568 /* FP Frame Rate Control Pattern (FP10R to FP2FR) */ 569 #define MQ200_FPFRCPR(n) MQ200_FPR(0x10+n) 570 571 /* FP Frame Rate Control Weight (FP30R to FP37R) */ 572 #define MQ200_FPFRCWR(n) MQ200_FPR(0x30+n) 573 574 /* 575 * Color Palette 1 576 */ 577 #define MQ200_CP(cp, idx) (MQ200_CP1 + (idx) * 4) */ 578 # define MQ200_GC_BLUE_MASK 0x00ff0000 579 # define MQ200_GC_BLUE_SHIFT 16 580 # define MQ200_GC_GREEN_MASK 0x0000ff00 581 # define MQ200_GC_GREEN_SHIFT 8 582 # define MQ200_GC_RED_MASK 0x000000ff 583 # define MQ200_GC_RED_SHIFT 0 584 # define MQ200_GC_RGB(r, g, b) \ 585 (((((unsigned long)(r))&0xff)<<0) | \ 586 ((((unsigned long)(g))&0xff)<<8) | \ 587 ((((unsigned long)(b))&0xff)<<16)) 588 589 /* 590 * Device Configration 591 */ 592 593 /* 594 * PCI configuration space 595 */ 596 #define MQ200_PC00R (MQ200_PC+0x00) /* device/vendor ID */ 597 #define MQ200_PC04R (MQ200_PC+0x04) /* command/status */ 598 #define MQ200_PC08R (MQ200_PC+0x04) /* calss code/revision */ 599 600 #define MQ200_PMR (MQ200_PC+0x40) /* power management */ 601 #define MQ200_PMCSR (MQ200_PC+0x44) /* control/status */ 602
Indexes created Thu Oct 23 22:10:10 GMT 2025