plumicu.c revision 1.1
1 /* $NetBSD: plumicu.c,v 1.1 1999/11/21 06:50:26 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include "opt_tx39_debug.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #define TAILQ_FOREACH(var, head, field) \ 37 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 38 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <hpcmips/tx/tx39var.h> 44 #include <hpcmips/dev/plumvar.h> 45 #include <hpcmips/dev/plumicuvar.h> 46 #include <hpcmips/dev/plumicureg.h> 47 48 #define PLUMICUDEBUG 49 #ifdef PLUMICUDEBUG 50 #define DPRINTF(arg) printf arg 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 int plumicu_match __P((struct device*, struct cfdata*, void*)); 56 void plumicu_attach __P((struct device*, struct device*, void*)); 57 int plumicu_intr __P((void*)); 58 59 struct plum_intr_ctrl { 60 plumreg_t ic_ackpat1; 61 plumreg_t ic_ackpat2; 62 int ic_ackreg2; 63 plumreg_t ic_ienpat; 64 int ic_ienreg; 65 plumreg_t ic_senpat; 66 int ic_senreg; 67 } pi_ctrl[] = { 68 [PLUM_INT_C1IO] = {PLUM_INT_INTSTA_PCCINT, 69 PLUM_INT_PCCINTS_C1IO, PLUM_INT_PCCINTS_REG, 70 PLUM_INT_PCCIEN_IENC1IO, PLUM_INT_PCCIEN_REG, 71 PLUM_INT_PCCIEN_SENC1IO, PLUM_INT_PCCIEN_REG 72 }, 73 [PLUM_INT_C1RI] = {PLUM_INT_INTSTA_PCCINT, 74 PLUM_INT_PCCINTS_C1RI, PLUM_INT_PCCINTS_REG, 75 PLUM_INT_PCCIEN_IENC1RI, PLUM_INT_PCCIEN_REG, 76 PLUM_INT_PCCIEN_SENC1RI, PLUM_INT_PCCIEN_REG 77 }, 78 [PLUM_INT_C1SC] = {PLUM_INT_INTSTA_C1SCINT, 0, 0, 0, 0, 0, 0}, 79 [PLUM_INT_C2IO] = {PLUM_INT_INTSTA_PCCINT, 80 PLUM_INT_PCCINTS_C2IO, PLUM_INT_PCCINTS_REG, 81 PLUM_INT_PCCIEN_IENC2IO, PLUM_INT_PCCIEN_REG, 82 PLUM_INT_PCCIEN_SENC2IO, PLUM_INT_PCCIEN_REG 83 }, 84 [PLUM_INT_C2RI] = {PLUM_INT_INTSTA_PCCINT, 85 PLUM_INT_PCCINTS_C2RI, PLUM_INT_PCCINTS_REG, 86 PLUM_INT_PCCIEN_IENC2RI, PLUM_INT_PCCIEN_REG, 87 PLUM_INT_PCCIEN_SENC2RI, PLUM_INT_PCCIEN_REG 88 }, 89 [PLUM_INT_C2SC] = {PLUM_INT_INTSTA_C2SCINT, 0, 0, 0, 0, 0, 0}, 90 [PLUM_INT_DISP] = {PLUM_INT_INTSTA_DISPINT, 0, 0, 0, 0, 0, 0}, 91 [PLUM_INT_USB] = {PLUM_INT_INTSTA_USBINT, 92 0, 0, 93 PLUM_INT_USBINTEN_IEN, PLUM_INT_USBINTEN_REG, 94 0, 0 95 }, 96 [PLUM_INT_USBWAKE] = {PLUM_INT_INTSTA_USBWAKE, 97 0, 0, 98 PLUM_INT_USBINTEN_WIEN, PLUM_INT_USBINTEN_REG, 99 0, 0 100 }, 101 [PLUM_INT_SM] = {PLUM_INT_INTSTA_SMINT, 102 0, 0, 103 PLUM_INT_SMIEN, PLUM_INT_SMIEN_REG, 104 0, 0 105 }, 106 [PLUM_INT_EXT5IO0] = {PLUM_INT_INTSTA_EXTINT, 107 PLUM_INT_EXTINTS_IO5INT0, PLUM_INT_EXTINTS_REG, 108 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 109 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 110 }, 111 [PLUM_INT_EXT5IO1] = {PLUM_INT_INTSTA_EXTINT, 112 PLUM_INT_EXTINTS_IO5INT1, PLUM_INT_EXTINTS_REG, 113 PLUM_INT_EXTIEN_IENIO5INT1, PLUM_INT_EXTIEN_REG, 114 PLUM_INT_EXTIEN_SENIO5INT1, PLUM_INT_EXTIEN_REG, 115 }, 116 [PLUM_INT_EXT5IO2] = {PLUM_INT_INTSTA_EXTINT, 117 PLUM_INT_EXTINTS_IO5INT2, PLUM_INT_EXTINTS_REG, 118 PLUM_INT_EXTIEN_IENIO5INT2, PLUM_INT_EXTIEN_REG, 119 PLUM_INT_EXTIEN_SENIO5INT2, PLUM_INT_EXTIEN_REG, 120 }, 121 [PLUM_INT_EXT5IO3] = {PLUM_INT_INTSTA_EXTINT, 122 PLUM_INT_EXTINTS_IO5INT3, PLUM_INT_EXTINTS_REG, 123 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 124 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 125 }, 126 [PLUM_INT_EXT3IO0] = {PLUM_INT_INTSTA_EXTINT, 127 PLUM_INT_EXTINTS_IO3INT0, PLUM_INT_EXTINTS_REG, 128 PLUM_INT_EXTIEN_IENIO3INT0, PLUM_INT_EXTIEN_REG, 129 PLUM_INT_EXTIEN_SENIO3INT0, PLUM_INT_EXTIEN_REG, 130 }, 131 [PLUM_INT_EXT3IO1] = {PLUM_INT_INTSTA_EXTINT, 132 PLUM_INT_EXTINTS_IO3INT1, PLUM_INT_EXTINTS_REG, 133 PLUM_INT_EXTIEN_IENIO3INT1, PLUM_INT_EXTIEN_REG, 134 PLUM_INT_EXTIEN_SENIO3INT1, PLUM_INT_EXTIEN_REG, 135 } 136 }; 137 138 struct plum_intr_entry { 139 int pi_line; 140 int (*pi_fun) __P((void*)); 141 void *pi_arg; 142 struct plum_intr_ctrl *pi_ctrl; 143 TAILQ_ENTRY(plum_intr_entry) pi_link; 144 }; 145 146 struct plumicu_softc { 147 struct device sc_dev; 148 plum_chipset_tag_t sc_pc; 149 bus_space_tag_t sc_regt; 150 bus_space_handle_t sc_regh; 151 void *sc_ih; 152 int sc_enable_count; 153 TAILQ_HEAD(, plum_intr_entry) sc_pi_head[PLUM_INTR_MAX]; 154 }; 155 156 struct cfattach plumicu_ca = { 157 sizeof(struct plumicu_softc), plumicu_match, plumicu_attach 158 }; 159 160 void plumicu_dump __P((struct plumicu_softc*)); 161 162 int 163 plumicu_match(parent, cf, aux) 164 struct device *parent; 165 struct cfdata *cf; 166 void *aux; 167 { 168 return 2; /* 1st attach group */ 169 } 170 171 void 172 plumicu_attach(parent, self, aux) 173 struct device *parent; 174 struct device *self; 175 void *aux; 176 { 177 struct plum_attach_args *pa = aux; 178 struct plumicu_softc *sc = (void*)self; 179 struct plum_intr_ctrl *pic; 180 bus_space_tag_t regt; 181 bus_space_handle_t regh; 182 plumreg_t reg; 183 int i; 184 185 sc->sc_pc = pa->pa_pc; 186 sc->sc_regt = pa->pa_regt; 187 188 /* map plum2 interrupt controller register space */ 189 if (bus_space_map(sc->sc_regt, PLUM_INT_REGBASE, 190 PLUM_INT_REGSIZE, 0, &sc->sc_regh)) { 191 printf(":interrupt register map failed\n"); 192 return; 193 } 194 195 /* disable all interrupt */ 196 regt = sc->sc_regt; 197 regh = sc->sc_regh; 198 for (i = 0; i < PLUM_INTR_MAX; i++) { 199 pic = &pi_ctrl[i]; 200 if (pic->ic_ienreg) { 201 reg = plum_conf_read(regt, regh, pic->ic_ienreg); 202 reg &= ~pic->ic_ienpat; 203 plum_conf_write(regt, regh, pic->ic_ienreg, reg); 204 } 205 if (pic->ic_senreg) { 206 reg = plum_conf_read(regt, regh, pic->ic_senreg); 207 reg &= ~pic->ic_senpat; 208 plum_conf_write(regt, regh, pic->ic_senreg, reg); 209 } 210 } 211 212 for (i = 0; i < PLUM_INTR_MAX; i++) { 213 TAILQ_INIT(&sc->sc_pi_head[i]); 214 } 215 216 /* register handle to plum_chipset_tag */ 217 plum_conf_register_intr(sc->sc_pc, (void*)sc); 218 219 /* disable interrupt redirect to TX39 core */ 220 plum_conf_write(sc->sc_regt, sc->sc_regh, PLUM_INT_INTIEN_REG, 0); 221 222 if (!(sc->sc_ih = tx_intr_establish(sc->sc_pc->pc_tc, pa->pa_irq, 223 IST_EDGE, IPL_BIO, plumicu_intr, sc))) { 224 printf(": can't establish interrupt\n"); 225 } 226 printf("\n"); 227 228 plumicu_dump(sc); 229 } 230 231 void* 232 plum_intr_establish(pc, line, mode, level, ih_fun, ih_arg) 233 plum_chipset_tag_t pc; 234 int line; 235 int mode; /* no meaning */ 236 int level; /* XXX not yet */ 237 int (*ih_fun) __P((void*)); 238 void *ih_arg; 239 { 240 struct plumicu_softc *sc = pc->pc_intrt; 241 bus_space_tag_t regt = sc->sc_regt; 242 bus_space_handle_t regh = sc->sc_regh; 243 plumreg_t reg; 244 struct plum_intr_entry *pi; 245 246 if (!LEGAL_PRUM_INTR(line)) { 247 panic("plum_intr_establish: bogus interrupt line"); 248 } 249 250 if (!(pi = malloc(sizeof(struct plum_intr_entry), 251 M_DEVBUF, M_NOWAIT))) { 252 panic ("plum_intr_establish: no memory."); 253 } 254 255 memset(pi, 0, sizeof(struct plum_intr_entry)); 256 pi->pi_line = line; 257 pi->pi_fun = ih_fun; 258 pi->pi_arg = ih_arg; 259 pi->pi_ctrl = &pi_ctrl[line]; 260 TAILQ_INSERT_TAIL(&sc->sc_pi_head[line], pi, pi_link); 261 262 /* Enable interrupt */ 263 if (pi->pi_ctrl->ic_ienreg) { 264 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 265 reg |= pi->pi_ctrl->ic_ienpat; 266 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 267 } 268 if (pi->pi_ctrl->ic_senreg) { 269 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 270 reg |= pi->pi_ctrl->ic_senpat; 271 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 272 } 273 274 /* Enable redirect to TX39 core */ 275 DPRINTF(("plum_intr_establish: %d (count=%d)\n", line, sc->sc_enable_count)); 276 sc->sc_enable_count++; 277 plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 1); 278 279 return ih_fun; 280 } 281 282 void 283 plum_intr_disestablish(pc, arg) 284 plum_chipset_tag_t pc; 285 void *arg; 286 { 287 struct plumicu_softc *sc = pc->pc_intrt; 288 bus_space_tag_t regt = sc->sc_regt; 289 bus_space_handle_t regh = sc->sc_regh; 290 plumreg_t reg; 291 struct plum_intr_entry *pi; 292 int i; 293 294 sc = pc->pc_intrt; 295 for (i = 0; i < PLUM_INTR_MAX; i++) { 296 TAILQ_FOREACH(pi, &sc->sc_pi_head[i], pi_link) { 297 if (pi->pi_fun == arg) { 298 TAILQ_REMOVE(&sc->sc_pi_head[i], pi, pi_link); 299 DPRINTF(("plum_intr_disestablish: %d (count=%d)\n", 300 pi->pi_line, sc->sc_enable_count - 1)); 301 free(pi, M_DEVBUF); 302 goto found; 303 } 304 } 305 } 306 panic("plum_intr_disestablish: can't find entry."); 307 found: 308 /* Disable interrupt */ 309 if (pi->pi_ctrl->ic_ienreg) { 310 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 311 reg &= ~(pi->pi_ctrl->ic_ienpat); 312 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 313 } 314 if (pi->pi_ctrl->ic_senreg) { 315 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 316 reg &= ~(pi->pi_ctrl->ic_senpat); 317 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 318 } 319 320 /* Disable redirect to TX39 core */ 321 if (--sc->sc_enable_count == 0) { 322 /* Disable redirect to TX39 core to avoid lost interrupt */ 323 plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 0); 324 } 325 } 326 327 int 328 plumicu_intr(arg) 329 void *arg; 330 { 331 struct plumicu_softc *sc = arg; 332 struct plum_intr_entry *pi; 333 bus_space_tag_t regt = sc->sc_regt; 334 bus_space_handle_t regh = sc->sc_regh; 335 plumreg_t reg1, reg2; 336 int i; 337 338 reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 339 for (i = 0; i < PLUM_INTR_MAX; i++) { 340 struct plum_intr_ctrl *pic = &pi_ctrl[i]; 341 if (pic->ic_ackpat1 & reg1) { 342 if (pic->ic_ackpat2) { 343 reg2 = plum_conf_read(regt, regh, 344 pic->ic_ackreg2); 345 TAILQ_FOREACH(pi, &sc->sc_pi_head[i], 346 pi_link) { 347 if (pi->pi_ctrl->ic_ackpat2 & reg2) { 348 plum_conf_write( 349 regt, regh, 350 pic->ic_ackreg2, 351 pi->pi_ctrl->ic_ackpat2); 352 (*pi->pi_fun)(pi->pi_arg); 353 } 354 } 355 } else { 356 TAILQ_FOREACH(pi, &sc->sc_pi_head[i], 357 pi_link) { 358 (*pi->pi_fun)(pi->pi_arg); 359 printf("INT(2) %d:", i); 360 } 361 } 362 } 363 } 364 365 return 0; 366 } 367 368 void 369 plumicu_dump(sc) 370 struct plumicu_softc *sc; 371 { 372 bus_space_tag_t regt = sc->sc_regt; 373 bus_space_handle_t regh = sc->sc_regh; 374 plumreg_t reg; 375 376 printf("status:"); 377 reg = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 378 bitdisp(reg); 379 printf("ExtIO\n"); 380 printf("status:"); 381 reg = plum_conf_read(regt, regh, PLUM_INT_EXTINTS_REG); 382 bitdisp(reg); 383 printf("enable:"); 384 reg = plum_conf_read(regt, regh, PLUM_INT_EXTIEN_REG); 385 bitdisp(reg); 386 387 } 388
Indexes created Thu Sep 25 16:09:42 GMT 2025