plumicu.c revision 1.2
1 /* $NetBSD: plumicu.c,v 1.2 1999/12/07 17:53:04 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include "opt_tx39_debug.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 #include <sys/queue.h> 36 #define TAILQ_FOREACH(var, head, field) \ 37 for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field)) 38 #define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) 39 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <hpcmips/tx/tx39var.h> 44 #include <hpcmips/dev/plumvar.h> 45 #include <hpcmips/dev/plumicuvar.h> 46 #include <hpcmips/dev/plumicureg.h> 47 48 #define PLUMICUDEBUG 49 #ifdef PLUMICUDEBUG 50 #define DPRINTF(arg) printf arg 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 int plumicu_match __P((struct device*, struct cfdata*, void*)); 56 void plumicu_attach __P((struct device*, struct device*, void*)); 57 int plumicu_intr __P((void*)); 58 59 struct plum_intr_ctrl { 60 plumreg_t ic_ackpat1; 61 plumreg_t ic_ackpat2; int ic_ackreg2; 62 plumreg_t ic_ienpat; int ic_ienreg; 63 plumreg_t ic_senpat; int ic_senreg; 64 } pi_ctrl[PLUM_INTR_MAX] = { 65 [PLUM_INT_C1IO] = {PLUM_INT_INTSTA_PCCINT, 66 PLUM_INT_PCCINTS_C1IO, PLUM_INT_PCCINTS_REG, 67 PLUM_INT_PCCIEN_IENC1IO, PLUM_INT_PCCIEN_REG, 68 PLUM_INT_PCCIEN_SENC1IO, PLUM_INT_PCCIEN_REG 69 }, 70 [PLUM_INT_C1RI] = {PLUM_INT_INTSTA_PCCINT, 71 PLUM_INT_PCCINTS_C1RI, PLUM_INT_PCCINTS_REG, 72 PLUM_INT_PCCIEN_IENC1RI, PLUM_INT_PCCIEN_REG, 73 PLUM_INT_PCCIEN_SENC1RI, PLUM_INT_PCCIEN_REG 74 }, 75 [PLUM_INT_C1SC] = {PLUM_INT_INTSTA_C1SCINT, 0, 0, 0, 0, 0, 0}, 76 [PLUM_INT_C2IO] = {PLUM_INT_INTSTA_PCCINT, 77 PLUM_INT_PCCINTS_C2IO, PLUM_INT_PCCINTS_REG, 78 PLUM_INT_PCCIEN_IENC2IO, PLUM_INT_PCCIEN_REG, 79 PLUM_INT_PCCIEN_SENC2IO, PLUM_INT_PCCIEN_REG 80 }, 81 [PLUM_INT_C2RI] = {PLUM_INT_INTSTA_PCCINT, 82 PLUM_INT_PCCINTS_C2RI, PLUM_INT_PCCINTS_REG, 83 PLUM_INT_PCCIEN_IENC2RI, PLUM_INT_PCCIEN_REG, 84 PLUM_INT_PCCIEN_SENC2RI, PLUM_INT_PCCIEN_REG 85 }, 86 [PLUM_INT_C2SC] = {PLUM_INT_INTSTA_C2SCINT, 0, 0, 0, 0, 0, 0}, 87 [PLUM_INT_DISP] = {PLUM_INT_INTSTA_DISPINT, 0, 0, 0, 0, 0, 0}, 88 [PLUM_INT_USB] = {PLUM_INT_INTSTA_USBINT, 89 0, 0, 90 PLUM_INT_USBINTEN_IEN, PLUM_INT_USBINTEN_REG, 91 0, 0 92 }, 93 [PLUM_INT_USBWAKE] = {PLUM_INT_INTSTA_USBWAKE, 94 0, 0, 95 PLUM_INT_USBINTEN_WIEN, PLUM_INT_USBINTEN_REG, 96 0, 0 97 }, 98 [PLUM_INT_SM] = {PLUM_INT_INTSTA_SMINT, 99 0, 0, 100 PLUM_INT_SMIEN, PLUM_INT_SMIEN_REG, 101 0, 0 102 }, 103 [PLUM_INT_EXT5IO0] = {PLUM_INT_INTSTA_EXTINT, 104 PLUM_INT_EXTINTS_IO5INT0, PLUM_INT_EXTINTS_REG, 105 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 106 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 107 }, 108 [PLUM_INT_EXT5IO1] = {PLUM_INT_INTSTA_EXTINT, 109 PLUM_INT_EXTINTS_IO5INT1, PLUM_INT_EXTINTS_REG, 110 PLUM_INT_EXTIEN_IENIO5INT1, PLUM_INT_EXTIEN_REG, 111 PLUM_INT_EXTIEN_SENIO5INT1, PLUM_INT_EXTIEN_REG, 112 }, 113 [PLUM_INT_EXT5IO2] = {PLUM_INT_INTSTA_EXTINT, 114 PLUM_INT_EXTINTS_IO5INT2, PLUM_INT_EXTINTS_REG, 115 PLUM_INT_EXTIEN_IENIO5INT2, PLUM_INT_EXTIEN_REG, 116 PLUM_INT_EXTIEN_SENIO5INT2, PLUM_INT_EXTIEN_REG, 117 }, 118 [PLUM_INT_EXT5IO3] = {PLUM_INT_INTSTA_EXTINT, 119 PLUM_INT_EXTINTS_IO5INT3, PLUM_INT_EXTINTS_REG, 120 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 121 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 122 }, 123 [PLUM_INT_EXT3IO0] = {PLUM_INT_INTSTA_EXTINT, 124 PLUM_INT_EXTINTS_IO3INT0, PLUM_INT_EXTINTS_REG, 125 PLUM_INT_EXTIEN_IENIO3INT0, PLUM_INT_EXTIEN_REG, 126 PLUM_INT_EXTIEN_SENIO3INT0, PLUM_INT_EXTIEN_REG, 127 }, 128 [PLUM_INT_EXT3IO1] = {PLUM_INT_INTSTA_EXTINT, 129 PLUM_INT_EXTINTS_IO3INT1, PLUM_INT_EXTINTS_REG, 130 PLUM_INT_EXTIEN_IENIO3INT1, PLUM_INT_EXTIEN_REG, 131 PLUM_INT_EXTIEN_SENIO3INT1, PLUM_INT_EXTIEN_REG, 132 } 133 }; 134 135 struct plum_intr_entry { 136 int pi_line; 137 int (*pi_fun) __P((void*)); 138 void *pi_arg; 139 struct plum_intr_ctrl *pi_ctrl; 140 TAILQ_ENTRY(plum_intr_entry) pi_link; 141 }; 142 143 struct plumicu_softc { 144 struct device sc_dev; 145 plum_chipset_tag_t sc_pc; 146 bus_space_tag_t sc_regt; 147 bus_space_handle_t sc_regh; 148 void *sc_ih; 149 int sc_enable_count; 150 TAILQ_HEAD(, plum_intr_entry) sc_pi_head[PLUM_INTR_MAX]; 151 }; 152 153 struct cfattach plumicu_ca = { 154 sizeof(struct plumicu_softc), plumicu_match, plumicu_attach 155 }; 156 157 void plumicu_dump __P((struct plumicu_softc*)); 158 159 int 160 plumicu_match(parent, cf, aux) 161 struct device *parent; 162 struct cfdata *cf; 163 void *aux; 164 { 165 return 2; /* 1st attach group */ 166 } 167 168 void 169 plumicu_attach(parent, self, aux) 170 struct device *parent; 171 struct device *self; 172 void *aux; 173 { 174 struct plum_attach_args *pa = aux; 175 struct plumicu_softc *sc = (void*)self; 176 struct plum_intr_ctrl *pic; 177 bus_space_tag_t regt; 178 bus_space_handle_t regh; 179 plumreg_t reg; 180 int i; 181 182 sc->sc_pc = pa->pa_pc; 183 sc->sc_regt = pa->pa_regt; 184 185 /* map plum2 interrupt controller register space */ 186 if (bus_space_map(sc->sc_regt, PLUM_INT_REGBASE, 187 PLUM_INT_REGSIZE, 0, &sc->sc_regh)) { 188 printf(":interrupt register map failed\n"); 189 return; 190 } 191 192 /* disable all interrupt */ 193 regt = sc->sc_regt; 194 regh = sc->sc_regh; 195 for (i = 0; i < PLUM_INTR_MAX; i++) { 196 pic = &pi_ctrl[i]; 197 if (pic->ic_ienreg) { 198 reg = plum_conf_read(regt, regh, pic->ic_ienreg); 199 reg &= ~pic->ic_ienpat; 200 plum_conf_write(regt, regh, pic->ic_ienreg, reg); 201 } 202 if (pic->ic_senreg) { 203 reg = plum_conf_read(regt, regh, pic->ic_senreg); 204 reg &= ~pic->ic_senpat; 205 plum_conf_write(regt, regh, pic->ic_senreg, reg); 206 } 207 } 208 209 for (i = 0; i < PLUM_INTR_MAX; i++) { 210 TAILQ_INIT(&sc->sc_pi_head[i]); 211 } 212 213 /* register handle to plum_chipset_tag */ 214 plum_conf_register_intr(sc->sc_pc, (void*)sc); 215 216 /* disable interrupt redirect to TX39 core */ 217 plum_conf_write(sc->sc_regt, sc->sc_regh, PLUM_INT_INTIEN_REG, 0); 218 219 if (!(sc->sc_ih = tx_intr_establish(sc->sc_pc->pc_tc, pa->pa_irq, 220 IST_EDGE, IPL_BIO, plumicu_intr, sc))) { 221 printf(": can't establish interrupt\n"); 222 } 223 printf("\n"); 224 225 plumicu_dump(sc); 226 } 227 228 void* 229 plum_intr_establish(pc, line, mode, level, ih_fun, ih_arg) 230 plum_chipset_tag_t pc; 231 int line; 232 int mode; /* no meaning */ 233 int level; /* XXX not yet */ 234 int (*ih_fun) __P((void*)); 235 void *ih_arg; 236 { 237 struct plumicu_softc *sc = pc->pc_intrt; 238 bus_space_tag_t regt = sc->sc_regt; 239 bus_space_handle_t regh = sc->sc_regh; 240 plumreg_t reg; 241 struct plum_intr_entry *pi; 242 243 if (!LEGAL_PRUM_INTR(line)) { 244 panic("plum_intr_establish: bogus interrupt line"); 245 } 246 247 if (!(pi = malloc(sizeof(struct plum_intr_entry), 248 M_DEVBUF, M_NOWAIT))) { 249 panic ("plum_intr_establish: no memory."); 250 } 251 252 memset(pi, 0, sizeof(struct plum_intr_entry)); 253 pi->pi_line = line; 254 pi->pi_fun = ih_fun; 255 pi->pi_arg = ih_arg; 256 pi->pi_ctrl = &pi_ctrl[line]; 257 TAILQ_INSERT_TAIL(&sc->sc_pi_head[line], pi, pi_link); 258 259 /* Enable interrupt */ 260 /* status enable */ 261 if (pi->pi_ctrl->ic_senreg) { 262 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 263 reg |= pi->pi_ctrl->ic_senpat; 264 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 265 } 266 /* interrupt enable */ 267 if (pi->pi_ctrl->ic_ienreg) { 268 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 269 reg |= pi->pi_ctrl->ic_ienpat; 270 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 271 } 272 273 /* Enable redirect to TX39 core */ 274 DPRINTF(("plum_intr_establish: %d (count=%d)\n", line, sc->sc_enable_count)); 275 276 if (!sc->sc_enable_count++) { 277 plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, PLUM_INT_INTIEN); 278 } 279 280 return ih_fun; 281 } 282 283 void 284 plum_intr_disestablish(pc, arg) 285 plum_chipset_tag_t pc; 286 void *arg; 287 { 288 struct plumicu_softc *sc = pc->pc_intrt; 289 bus_space_tag_t regt = sc->sc_regt; 290 bus_space_handle_t regh = sc->sc_regh; 291 plumreg_t reg; 292 struct plum_intr_entry *pi; 293 int i; 294 295 sc = pc->pc_intrt; 296 for (i = 0; i < PLUM_INTR_MAX; i++) { 297 TAILQ_FOREACH(pi, &sc->sc_pi_head[i], pi_link) { 298 if (pi->pi_fun == arg) { 299 TAILQ_REMOVE(&sc->sc_pi_head[i], pi, pi_link); 300 DPRINTF(("plum_intr_disestablish: %d (count=%d)\n", 301 pi->pi_line, sc->sc_enable_count - 1)); 302 goto found; 303 } 304 } 305 } 306 panic("plum_intr_disestablish: can't find entry."); 307 found: 308 /* Disable interrupt */ 309 if (pi->pi_ctrl->ic_ienreg) { 310 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 311 reg &= ~(pi->pi_ctrl->ic_ienpat); 312 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 313 } 314 if (pi->pi_ctrl->ic_senreg) { 315 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 316 reg &= ~(pi->pi_ctrl->ic_senpat); 317 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 318 } 319 free(pi, M_DEVBUF); 320 321 /* Disable redirect to TX39 core */ 322 if (--sc->sc_enable_count == 0) { 323 /* Disable redirect to TX39 core */ 324 plum_conf_write(regt, regh, PLUM_INT_INTIEN_REG, 0); 325 } 326 } 327 328 int 329 plumicu_intr(arg) 330 void *arg; 331 { 332 struct plumicu_softc *sc = arg; 333 struct plum_intr_entry *pi; 334 bus_space_tag_t regt = sc->sc_regt; 335 bus_space_handle_t regh = sc->sc_regh; 336 plumreg_t reg1, reg2; 337 int i; 338 339 reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 340 341 for (i = 0; i < PLUM_INTR_MAX; i++) { 342 struct plum_intr_ctrl *pic = &pi_ctrl[i]; 343 if (pic->ic_ackpat1 & reg1) { 344 if (pic->ic_ackpat2) { 345 reg2 = plum_conf_read(regt, regh, 346 pic->ic_ackreg2); 347 if (pic->ic_ackpat2 & reg2) { 348 plum_conf_write( 349 regt, regh, 350 pic->ic_ackreg2, 351 pic->ic_ackpat2); 352 TAILQ_FOREACH(pi, 353 &sc->sc_pi_head[i], 354 pi_link) { 355 (*pi->pi_fun)(pi->pi_arg); 356 } 357 } 358 } else { 359 TAILQ_FOREACH(pi, &sc->sc_pi_head[i], 360 pi_link) { 361 (*pi->pi_fun)(pi->pi_arg); 362 printf("INT(2) %d:", i); 363 } 364 } 365 } 366 } 367 368 return 0; 369 } 370 371 void 372 plumicu_dump(sc) 373 struct plumicu_softc *sc; 374 { 375 bus_space_tag_t regt = sc->sc_regt; 376 bus_space_handle_t regh = sc->sc_regh; 377 plumreg_t reg; 378 379 printf("status:"); 380 reg = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 381 bitdisp(reg); 382 printf("ExtIO\n"); 383 printf("status:"); 384 reg = plum_conf_read(regt, regh, PLUM_INT_EXTINTS_REG); 385 bitdisp(reg); 386 printf("enable:"); 387 reg = plum_conf_read(regt, regh, PLUM_INT_EXTIEN_REG); 388 bitdisp(reg); 389 390 } 391
Indexes created Fri Sep 26 20:09:58 GMT 2025