plumicu.c revision 1.5
1 /* $NetBSD: plumicu.c,v 1.5 2002/01/29 18:53:10 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <hpcmips/tx/tx39var.h> 47 #include <hpcmips/dev/plumvar.h> 48 #include <hpcmips/dev/plumicuvar.h> 49 #include <hpcmips/dev/plumicureg.h> 50 51 #ifdef PLUMICUDEBUG 52 #define DPRINTF(arg) printf arg 53 #else 54 #define DPRINTF(arg) 55 #endif 56 57 int plumicu_match(struct device *, struct cfdata *, void *); 58 void plumicu_attach(struct device *, struct device *, void *); 59 int plumicu_intr(void *); 60 61 static __inline__ void plum_di(plum_chipset_tag_t); 62 static __inline__ void plum_ei(plum_chipset_tag_t); 63 64 const struct plum_intr_ctrl { 65 plumreg_t ic_ackpat1; 66 plumreg_t ic_ackpat2; int ic_ackreg2; 67 plumreg_t ic_ienpat; int ic_ienreg; 68 plumreg_t ic_senpat; int ic_senreg; 69 } pi_ctrl[PLUM_INTR_MAX] = { 70 [PLUM_INT_C1IO] = {PLUM_INT_INTSTA_PCCINT, 71 PLUM_INT_PCCINTS_C1IO, PLUM_INT_PCCINTS_REG, 72 PLUM_INT_PCCIEN_IENC1IO, PLUM_INT_PCCIEN_REG, 73 PLUM_INT_PCCIEN_SENC1IO, PLUM_INT_PCCIEN_REG 74 }, 75 [PLUM_INT_C1RI] = {PLUM_INT_INTSTA_PCCINT, 76 PLUM_INT_PCCINTS_C1RI, PLUM_INT_PCCINTS_REG, 77 PLUM_INT_PCCIEN_IENC1RI, PLUM_INT_PCCIEN_REG, 78 PLUM_INT_PCCIEN_SENC1RI, PLUM_INT_PCCIEN_REG 79 }, 80 [PLUM_INT_C1SC] = {PLUM_INT_INTSTA_C1SCINT, 0, 0, 0, 0, 0, 0}, 81 [PLUM_INT_C2IO] = {PLUM_INT_INTSTA_PCCINT, 82 PLUM_INT_PCCINTS_C2IO, PLUM_INT_PCCINTS_REG, 83 PLUM_INT_PCCIEN_IENC2IO, PLUM_INT_PCCIEN_REG, 84 PLUM_INT_PCCIEN_SENC2IO, PLUM_INT_PCCIEN_REG 85 }, 86 [PLUM_INT_C2RI] = {PLUM_INT_INTSTA_PCCINT, 87 PLUM_INT_PCCINTS_C2RI, PLUM_INT_PCCINTS_REG, 88 PLUM_INT_PCCIEN_IENC2RI, PLUM_INT_PCCIEN_REG, 89 PLUM_INT_PCCIEN_SENC2RI, PLUM_INT_PCCIEN_REG 90 }, 91 [PLUM_INT_C2SC] = {PLUM_INT_INTSTA_C2SCINT, 0, 0, 0, 0, 0, 0}, 92 [PLUM_INT_DISP] = {PLUM_INT_INTSTA_DISPINT, 0, 0, 0, 0, 0, 0}, 93 [PLUM_INT_USB] = {PLUM_INT_INTSTA_USBINT, 94 0, 0, 95 PLUM_INT_USBINTEN_IEN, PLUM_INT_USBINTEN_REG, 96 0, 0 97 }, 98 [PLUM_INT_USBWAKE] = {PLUM_INT_INTSTA_USBWAKE, 99 0, 0, 100 PLUM_INT_USBINTEN_WIEN, PLUM_INT_USBINTEN_REG, 101 0, 0 102 }, 103 [PLUM_INT_SM] = {PLUM_INT_INTSTA_SMINT, 104 0, 0, 105 PLUM_INT_SMIEN, PLUM_INT_SMIEN_REG, 106 0, 0 107 }, 108 [PLUM_INT_EXT5IO0] = {PLUM_INT_INTSTA_EXTINT, 109 PLUM_INT_EXTINTS_IO5INT0, PLUM_INT_EXTINTS_REG, 110 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 111 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 112 }, 113 [PLUM_INT_EXT5IO1] = {PLUM_INT_INTSTA_EXTINT, 114 PLUM_INT_EXTINTS_IO5INT1, PLUM_INT_EXTINTS_REG, 115 PLUM_INT_EXTIEN_IENIO5INT1, PLUM_INT_EXTIEN_REG, 116 PLUM_INT_EXTIEN_SENIO5INT1, PLUM_INT_EXTIEN_REG, 117 }, 118 [PLUM_INT_EXT5IO2] = {PLUM_INT_INTSTA_EXTINT, 119 PLUM_INT_EXTINTS_IO5INT2, PLUM_INT_EXTINTS_REG, 120 PLUM_INT_EXTIEN_IENIO5INT2, PLUM_INT_EXTIEN_REG, 121 PLUM_INT_EXTIEN_SENIO5INT2, PLUM_INT_EXTIEN_REG, 122 }, 123 [PLUM_INT_EXT5IO3] = {PLUM_INT_INTSTA_EXTINT, 124 PLUM_INT_EXTINTS_IO5INT3, PLUM_INT_EXTINTS_REG, 125 PLUM_INT_EXTIEN_IENIO5INT0, PLUM_INT_EXTIEN_REG, 126 PLUM_INT_EXTIEN_SENIO5INT0, PLUM_INT_EXTIEN_REG, 127 }, 128 [PLUM_INT_EXT3IO0] = {PLUM_INT_INTSTA_EXTINT, 129 PLUM_INT_EXTINTS_IO3INT0, PLUM_INT_EXTINTS_REG, 130 PLUM_INT_EXTIEN_IENIO3INT0, PLUM_INT_EXTIEN_REG, 131 PLUM_INT_EXTIEN_SENIO3INT0, PLUM_INT_EXTIEN_REG, 132 }, 133 [PLUM_INT_EXT3IO1] = {PLUM_INT_INTSTA_EXTINT, 134 PLUM_INT_EXTINTS_IO3INT1, PLUM_INT_EXTINTS_REG, 135 PLUM_INT_EXTIEN_IENIO3INT1, PLUM_INT_EXTIEN_REG, 136 PLUM_INT_EXTIEN_SENIO3INT1, PLUM_INT_EXTIEN_REG, 137 } 138 }; 139 140 struct plum_intr_entry { 141 int pi_enabled; 142 int pi_line; 143 int (*pi_fun)(void *); 144 void *pi_arg; 145 const struct plum_intr_ctrl *pi_ctrl; 146 }; 147 148 struct plumicu_softc { 149 struct device sc_dev; 150 plum_chipset_tag_t sc_pc; 151 bus_space_tag_t sc_regt; 152 bus_space_handle_t sc_regh; 153 void *sc_ih; 154 int sc_enable_count; 155 struct plum_intr_entry sc_intr[PLUM_INTR_MAX]; 156 }; 157 158 struct cfattach plumicu_ca = { 159 sizeof(struct plumicu_softc), plumicu_match, plumicu_attach 160 }; 161 162 #ifdef PLUMICUDEBUG 163 void plumicu_dump(struct plumicu_softc *); 164 #endif 165 166 int 167 plumicu_match(struct device *parent, struct cfdata *cf, void *aux) 168 { 169 170 return (2); /* 1st attach group */ 171 } 172 173 void 174 plumicu_attach(struct device *parent, struct device *self, void *aux) 175 { 176 struct plum_attach_args *pa = aux; 177 struct plumicu_softc *sc = (void*)self; 178 const struct plum_intr_ctrl *pic; 179 bus_space_tag_t regt; 180 bus_space_handle_t regh; 181 plumreg_t reg; 182 int i; 183 184 sc->sc_pc = pa->pa_pc; 185 sc->sc_regt = pa->pa_regt; 186 187 /* map plum2 interrupt controller register space */ 188 if (bus_space_map(sc->sc_regt, PLUM_INT_REGBASE, 189 PLUM_INT_REGSIZE, 0, &sc->sc_regh)) { 190 printf(":interrupt register map failed\n"); 191 return; 192 } 193 #ifdef PLUMICUDEBUG 194 plumicu_dump(sc); 195 #endif 196 /* disable all interrupt */ 197 regt = sc->sc_regt; 198 regh = sc->sc_regh; 199 for (i = 0; i < PLUM_INTR_MAX; i++) { 200 pic = &pi_ctrl[i]; 201 if (pic->ic_ienreg) { 202 reg = plum_conf_read(regt, regh, pic->ic_ienreg); 203 reg &= ~pic->ic_ienpat; 204 plum_conf_write(regt, regh, pic->ic_ienreg, reg); 205 } 206 if (pic->ic_senreg) { 207 reg = plum_conf_read(regt, regh, pic->ic_senreg); 208 reg &= ~pic->ic_senpat; 209 plum_conf_write(regt, regh, pic->ic_senreg, reg); 210 } 211 } 212 213 /* register handle to plum_chipset_tag */ 214 plum_conf_register_intr(sc->sc_pc, (void*)sc); 215 216 /* disable interrupt redirect to TX39 core */ 217 plum_di(sc->sc_pc); 218 219 if (!(sc->sc_ih = tx_intr_establish(sc->sc_pc->pc_tc, pa->pa_irq, 220 IST_EDGE, IPL_BIO, 221 plumicu_intr, sc))) { 222 printf(": can't establish interrupt\n"); 223 } 224 printf("\n"); 225 } 226 227 __inline__ void 228 plum_di(plum_chipset_tag_t pc) 229 { 230 struct plumicu_softc *sc = pc->pc_intrt; 231 232 plum_conf_write(sc->sc_regt, sc->sc_regh, PLUM_INT_INTIEN_REG, 0); 233 } 234 235 __inline__ void 236 plum_ei(plum_chipset_tag_t pc) 237 { 238 struct plumicu_softc *sc = pc->pc_intrt; 239 240 plum_conf_write(sc->sc_regt, sc->sc_regh, PLUM_INT_INTIEN_REG, 241 PLUM_INT_INTIEN); 242 } 243 244 void* 245 plum_intr_establish(plum_chipset_tag_t pc, int line, int mode, int level, 246 int (*ih_fun)(void *), void *ih_arg) 247 { 248 struct plumicu_softc *sc = pc->pc_intrt; 249 bus_space_tag_t regt = sc->sc_regt; 250 bus_space_handle_t regh = sc->sc_regh; 251 plumreg_t reg; 252 struct plum_intr_entry *pi; 253 254 if (!LEGAL_PRUM_INTR(line)) { 255 panic("plum_intr_establish: bogus interrupt line"); 256 } 257 258 pi = &sc->sc_intr[line]; 259 pi->pi_line = line; 260 pi->pi_fun = ih_fun; 261 pi->pi_arg = ih_arg; 262 pi->pi_ctrl = &pi_ctrl[line]; 263 264 /* Enable interrupt */ 265 266 /* status enable */ 267 if (pi->pi_ctrl->ic_senreg) { 268 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 269 reg |= pi->pi_ctrl->ic_senpat; 270 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 271 } 272 /* interrupt enable */ 273 if (pi->pi_ctrl->ic_ienreg) { 274 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 275 reg |= pi->pi_ctrl->ic_ienpat; 276 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 277 } 278 279 /* Enable redirect to TX39 core */ 280 DPRINTF(("plum_intr_establish: %d (count=%d)\n", line, 281 sc->sc_enable_count)); 282 283 if (sc->sc_enable_count++ == 0) 284 plum_ei(pc); 285 286 pi->pi_enabled = 1; 287 288 return (ih_fun); 289 } 290 291 void 292 plum_intr_disestablish(plum_chipset_tag_t pc, void *arg) 293 { 294 struct plumicu_softc *sc = pc->pc_intrt; 295 bus_space_tag_t regt = sc->sc_regt; 296 bus_space_handle_t regh = sc->sc_regh; 297 plumreg_t reg; 298 struct plum_intr_entry *pi; 299 int i; 300 301 sc = pc->pc_intrt; 302 303 for (i = 0; i < PLUM_INTR_MAX; i++) { 304 pi = &sc->sc_intr[i]; 305 if (pi->pi_fun != arg) 306 continue; 307 DPRINTF(("plum_intr_disestablish: %d (count=%d)\n", 308 pi->pi_line, sc->sc_enable_count - 1)); 309 goto found; 310 } 311 panic("plum_intr_disestablish: can't find entry."); 312 /* NOTREACHED */ 313 found: 314 pi->pi_enabled = 0; 315 /* Disable interrupt */ 316 if (pi->pi_ctrl->ic_ienreg) { 317 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_ienreg); 318 reg &= ~(pi->pi_ctrl->ic_ienpat); 319 plum_conf_write(regt, regh, pi->pi_ctrl->ic_ienreg, reg); 320 } 321 if (pi->pi_ctrl->ic_senreg) { 322 reg = plum_conf_read(regt, regh, pi->pi_ctrl->ic_senreg); 323 reg &= ~(pi->pi_ctrl->ic_senpat); 324 plum_conf_write(regt, regh, pi->pi_ctrl->ic_senreg, reg); 325 } 326 327 /* Disable/Enable interrupt redirect to TX39 core */ 328 if (--sc->sc_enable_count == 0) 329 plum_di(pc); 330 } 331 332 int 333 plumicu_intr(void *arg) 334 { 335 struct plumicu_softc *sc = arg; 336 bus_space_tag_t regt = sc->sc_regt; 337 bus_space_handle_t regh = sc->sc_regh; 338 plumreg_t reg1, reg2, reg_ext, reg_pccard; 339 int i; 340 341 plum_di(sc->sc_pc); 342 /* read level 1 status */ 343 reg1 = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 344 345 /* read level 2 status and acknowledge */ 346 reg_ext = plum_conf_read(regt, regh, PLUM_INT_EXTINTS_REG); 347 plum_conf_write(regt, regh, PLUM_INT_EXTINTS_REG, reg_ext); 348 349 reg_pccard = plum_conf_read(regt, regh, PLUM_INT_PCCINTS_REG); 350 plum_conf_write(regt, regh, PLUM_INT_PCCINTS_REG, reg_pccard); 351 352 for (i = 0; i < PLUM_INTR_MAX; i++) { 353 register struct plum_intr_entry *pi; 354 register const struct plum_intr_ctrl *pic = &pi_ctrl[i]; 355 356 if (!(pic->ic_ackpat1 & reg1)) 357 continue; 358 359 pi = &sc->sc_intr[i]; 360 if (!pi->pi_enabled) 361 continue; 362 363 if (pic->ic_ackreg2 == 0) { 364 (*pi->pi_fun)(pi->pi_arg); 365 continue; 366 } 367 368 reg2 = pic->ic_ackreg2 == PLUM_INT_PCCINTS_REG 369 ? reg_pccard : reg_ext; 370 371 if (pic->ic_ackpat2 & reg2) 372 (*pi->pi_fun)(pi->pi_arg); 373 } 374 plum_ei(sc->sc_pc); 375 376 return (0); 377 } 378 379 #ifdef PLUMICUDEBUG 380 void 381 plumicu_dump(struct plumicu_softc *sc) 382 { 383 bus_space_tag_t regt = sc->sc_regt; 384 bus_space_handle_t regh = sc->sc_regh; 385 plumreg_t reg; 386 387 printf("status:"); 388 reg = plum_conf_read(regt, regh, PLUM_INT_INTSTA_REG); 389 dbg_bit_print(reg); 390 printf("ExtIO\n"); 391 printf("status:"); 392 reg = plum_conf_read(regt, regh, PLUM_INT_EXTINTS_REG); 393 dbg_bit_print(reg); 394 printf("enable:"); 395 reg = plum_conf_read(regt, regh, PLUM_INT_EXTIEN_REG); 396 dbg_bit_print(reg); 397 398 } 399 #endif /* PLUMICUDEBUG */ 400
Indexes created Thu Sep 25 16:09:42 GMT 2025