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      1  1.5  andvar /*	$NetBSD: plumicureg.h,v 1.5 2022/05/31 11:22:33 andvar Exp $ */
      2  1.1     uch 
      3  1.3     uch /*-
      4  1.3     uch  * Copyright (c) 1999 The NetBSD Foundation, Inc.
      5  1.1     uch  * All rights reserved.
      6  1.1     uch  *
      7  1.3     uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.3     uch  * by UCHIYAMA Yasushi.
      9  1.3     uch  *
     10  1.1     uch  * Redistribution and use in source and binary forms, with or without
     11  1.1     uch  * modification, are permitted provided that the following conditions
     12  1.1     uch  * are met:
     13  1.1     uch  * 1. Redistributions of source code must retain the above copyright
     14  1.1     uch  *    notice, this list of conditions and the following disclaimer.
     15  1.3     uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.3     uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.3     uch  *    documentation and/or other materials provided with the distribution.
     18  1.1     uch  *
     19  1.3     uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  1.3     uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  1.3     uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  1.3     uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  1.3     uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  1.3     uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  1.3     uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  1.3     uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  1.3     uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  1.3     uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  1.3     uch  * POSSIBILITY OF SUCH DAMAGE.
     30  1.1     uch  */
     31  1.1     uch 
     32  1.1     uch /*
     33  1.2     uch  * PLUM2 INTERRUPT CONTROLLER UNIT
     34  1.1     uch  */
     35  1.1     uch #define	PLUM_INT_REGBASE		0x8000
     36  1.1     uch #define	PLUM_INT_REGSIZE		0x1000
     37  1.1     uch 
     38  1.2     uch /*
     39  1.2     uch  *  Interrupt status register
     40  1.2     uch  */
     41  1.1     uch #define	PLUM_INT_INTSTA_REG		0x000
     42  1.1     uch #define PLUM_INT_INTSTA_EXTINT		0x00000080
     43  1.1     uch #define PLUM_INT_INTSTA_SMINT		0x00000040
     44  1.1     uch #define PLUM_INT_INTSTA_USBWAKE		0x00000020
     45  1.1     uch #define PLUM_INT_INTSTA_USBINT		0x00000010
     46  1.1     uch #define PLUM_INT_INTSTA_DISPINT		0x00000008
     47  1.1     uch #define PLUM_INT_INTSTA_C2SCINT		0x00000004
     48  1.1     uch #define PLUM_INT_INTSTA_C1SCINT		0x00000002
     49  1.1     uch #define PLUM_INT_INTSTA_PCCINT		0x00000001
     50  1.1     uch 
     51  1.2     uch /*
     52  1.2     uch  *  Interrupt enable register
     53  1.2     uch  */
     54  1.1     uch #define	PLUM_INT_INTIEN_REG		0x010
     55  1.1     uch #define PLUM_INT_INTIEN			0x00000001
     56  1.1     uch 
     57  1.2     uch /*
     58  1.2     uch  *  External interrupts
     59  1.2     uch  */
     60  1.1     uch /* outside input interrupt status register */
     61  1.1     uch #define	PLUM_INT_EXTINTS_REG		0x100
     62  1.1     uch 
     63  1.2     uch #define	PLUM_INT_EXTINTS_IO3INT1	0x00000020
     64  1.2     uch #define	PLUM_INT_EXTINTS_IO3INT0	0x00000010
     65  1.2     uch #define	PLUM_INT_EXTINTS_IO5INT3	0x00000008
     66  1.2     uch #define	PLUM_INT_EXTINTS_IO5INT2	0x00000004
     67  1.2     uch #define	PLUM_INT_EXTINTS_IO5INT1	0x00000002
     68  1.2     uch #define	PLUM_INT_EXTINTS_IO5INT0	0x00000001
     69  1.2     uch 
     70  1.2     uch /* outside input interrupt status register (after the mask) */
     71  1.1     uch #define	PLUM_INT_EXTINTM_REG		0x104
     72  1.2     uch 
     73  1.2     uch /* interrupt enable register from the outside input */
     74  1.1     uch #define	PLUM_INT_EXTIEN_REG		0x110
     75  1.1     uch 
     76  1.2     uch #define	PLUM_INT_EXTIEN_IENIO3INT1	0x00000020
     77  1.2     uch #define	PLUM_INT_EXTIEN_IENIO3INT0	0x00000010
     78  1.2     uch #define	PLUM_INT_EXTIEN_IENIO5INT3	0x00000008
     79  1.2     uch #define	PLUM_INT_EXTIEN_IENIO5INT2	0x00000004
     80  1.2     uch #define	PLUM_INT_EXTIEN_IENIO5INT1	0x00000002
     81  1.2     uch #define	PLUM_INT_EXTIEN_IENIO5INT0	0x00000001
     82  1.2     uch 
     83  1.2     uch #define	PLUM_INT_EXTIEN_SENIO3INT1	0x00002000
     84  1.2     uch #define	PLUM_INT_EXTIEN_SENIO3INT0	0x00001000
     85  1.2     uch #define	PLUM_INT_EXTIEN_SENIO5INT3	0x00000800
     86  1.2     uch #define	PLUM_INT_EXTIEN_SENIO5INT2	0x00000400
     87  1.2     uch #define	PLUM_INT_EXTIEN_SENIO5INT1	0x00000200
     88  1.2     uch #define	PLUM_INT_EXTIEN_SENIO5INT0	0x00000100
     89  1.1     uch 
     90  1.2     uch /*
     91  1.2     uch  *  PC-card interrupts
     92  1.2     uch  */
     93  1.1     uch /* PC-card interrupt status register */
     94  1.1     uch #define	PLUM_INT_PCCINTS_REG		0x200
     95  1.2     uch 
     96  1.1     uch #define PLUM_INT_PCCINTS_C2RI		0x00000008
     97  1.1     uch #define PLUM_INT_PCCINTS_C2IO		0x00000004
     98  1.1     uch #define PLUM_INT_PCCINTS_C1RI		0x00000002
     99  1.1     uch #define PLUM_INT_PCCINTS_C1IO		0x00000001
    100  1.1     uch 
    101  1.1     uch /* PC-card interrupt status register (masked) */
    102  1.1     uch #define	PLUM_INT_PCCINTM_REG		0x204
    103  1.1     uch /* PC-card interrupt enable register */
    104  1.1     uch #define	PLUM_INT_PCCIEN_REG		0x210
    105  1.1     uch 
    106  1.2     uch #define PLUM_INT_PCCIEN_SENC2RI		0x00000800
    107  1.2     uch #define PLUM_INT_PCCIEN_SENC2IO		0x00000400
    108  1.2     uch #define PLUM_INT_PCCIEN_SENC1RI		0x00000200
    109  1.2     uch #define PLUM_INT_PCCIEN_SENC1IO		0x00000100
    110  1.1     uch #define PLUM_INT_PCCIEN_IENC2RI		0x00000008
    111  1.1     uch #define PLUM_INT_PCCIEN_IENC2IO		0x00000004
    112  1.1     uch #define PLUM_INT_PCCIEN_IENC1RI		0x00000002
    113  1.1     uch #define PLUM_INT_PCCIEN_IENC1IO		0x00000001
    114  1.1     uch 
    115  1.1     uch /* PC-card interrupt detection register */
    116  1.1     uch #define	PLUM_INT_PCCLKSL_REG		0x220
    117  1.1     uch #define	PLUM_INT_PCCLKSL_RTC		0x00000001 /*(for suspend mode)*/
    118  1.1     uch 
    119  1.2     uch /*
    120  1.2     uch  *  USB interrupts
    121  1.2     uch  */
    122  1.1     uch /* USB interrupt enable register */
    123  1.1     uch #define	PLUM_INT_USBINTEN_REG		0x310
    124  1.1     uch 
    125  1.2     uch /* master-enables the USB interrupts */
    126  1.2     uch #define	PLUM_INT_USBINTEN_IEN		0x00000002
    127  1.5  andvar /* enables the clock restart request interrupts */
    128  1.2     uch #define	PLUM_INT_USBINTEN_WIEN		0x00000001
    129  1.1     uch 
    130  1.2     uch /*
    131  1.2     uch  *  SmartMedia interrupts
    132  1.2     uch  */
    133  1.1     uch /* SmartMedia interrupt enable register */
    134  1.1     uch #define	PLUM_INT_SMIEN_REG		0x410
    135  1.1     uch 
    136  1.1     uch #define	PLUM_INT_SMIEN			0x00000001
    137