plumicureg.h revision 1.2.2.1
1 1.2.2.1 wrstuden /* $NetBSD: plumicureg.h,v 1.2.2.1 1999/12/27 18:32:02 wrstuden Exp $ */ 2 1.1 uch 3 1.1 uch /* 4 1.1 uch * Copyright (c) 1999, by UCHIYAMA Yasushi 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * Redistribution and use in source and binary forms, with or without 8 1.1 uch * modification, are permitted provided that the following conditions 9 1.1 uch * are met: 10 1.1 uch * 1. Redistributions of source code must retain the above copyright 11 1.1 uch * notice, this list of conditions and the following disclaimer. 12 1.1 uch * 2. The name of the developer may NOT be used to endorse or promote products 13 1.1 uch * derived from this software without specific prior written permission. 14 1.1 uch * 15 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 1.1 uch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 1.1 uch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 1.1 uch * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 1.1 uch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 1.1 uch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 1.1 uch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 1.1 uch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 1.1 uch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 1.1 uch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 1.1 uch * SUCH DAMAGE. 26 1.1 uch * 27 1.1 uch */ 28 1.1 uch 29 1.1 uch /* 30 1.2 uch * PLUM2 INTERRUPT CONTROLLER UNIT 31 1.1 uch */ 32 1.1 uch #define PLUM_INT_REGBASE 0x8000 33 1.1 uch #define PLUM_INT_REGSIZE 0x1000 34 1.1 uch 35 1.2 uch /* 36 1.2 uch * Interrupt status register 37 1.2 uch */ 38 1.1 uch #define PLUM_INT_INTSTA_REG 0x000 39 1.1 uch #define PLUM_INT_INTSTA_EXTINT 0x00000080 40 1.1 uch #define PLUM_INT_INTSTA_SMINT 0x00000040 41 1.1 uch #define PLUM_INT_INTSTA_USBWAKE 0x00000020 42 1.1 uch #define PLUM_INT_INTSTA_USBINT 0x00000010 43 1.1 uch #define PLUM_INT_INTSTA_DISPINT 0x00000008 44 1.1 uch #define PLUM_INT_INTSTA_C2SCINT 0x00000004 45 1.1 uch #define PLUM_INT_INTSTA_C1SCINT 0x00000002 46 1.1 uch #define PLUM_INT_INTSTA_PCCINT 0x00000001 47 1.1 uch 48 1.2 uch /* 49 1.2 uch * Interrupt enable register 50 1.2 uch */ 51 1.1 uch #define PLUM_INT_INTIEN_REG 0x010 52 1.1 uch #define PLUM_INT_INTIEN 0x00000001 53 1.1 uch 54 1.2 uch /* 55 1.2 uch * External interrupts 56 1.2 uch */ 57 1.1 uch /* outside input interrupt status register */ 58 1.1 uch #define PLUM_INT_EXTINTS_REG 0x100 59 1.1 uch 60 1.2 uch #define PLUM_INT_EXTINTS_IO3INT1 0x00000020 61 1.2 uch #define PLUM_INT_EXTINTS_IO3INT0 0x00000010 62 1.2 uch #define PLUM_INT_EXTINTS_IO5INT3 0x00000008 63 1.2 uch #define PLUM_INT_EXTINTS_IO5INT2 0x00000004 64 1.2 uch #define PLUM_INT_EXTINTS_IO5INT1 0x00000002 65 1.2 uch #define PLUM_INT_EXTINTS_IO5INT0 0x00000001 66 1.2 uch 67 1.2 uch /* outside input interrupt status register (after the mask) */ 68 1.1 uch #define PLUM_INT_EXTINTM_REG 0x104 69 1.2 uch 70 1.2 uch /* interrupt enable register from the outside input */ 71 1.1 uch #define PLUM_INT_EXTIEN_REG 0x110 72 1.1 uch 73 1.2 uch #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020 74 1.2 uch #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010 75 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008 76 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004 77 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002 78 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001 79 1.2 uch 80 1.2 uch #define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000 81 1.2 uch #define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000 82 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800 83 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400 84 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200 85 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100 86 1.1 uch 87 1.2 uch /* 88 1.2 uch * PC-card interrupts 89 1.2 uch */ 90 1.1 uch /* PC-card interrupt status register */ 91 1.1 uch #define PLUM_INT_PCCINTS_REG 0x200 92 1.2 uch 93 1.1 uch #define PLUM_INT_PCCINTS_C2RI 0x00000008 94 1.1 uch #define PLUM_INT_PCCINTS_C2IO 0x00000004 95 1.1 uch #define PLUM_INT_PCCINTS_C1RI 0x00000002 96 1.1 uch #define PLUM_INT_PCCINTS_C1IO 0x00000001 97 1.1 uch 98 1.1 uch /* PC-card interrupt status register (masked) */ 99 1.1 uch #define PLUM_INT_PCCINTM_REG 0x204 100 1.1 uch /* PC-card interrupt enable register */ 101 1.1 uch #define PLUM_INT_PCCIEN_REG 0x210 102 1.1 uch 103 1.2 uch #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 104 1.2 uch #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 105 1.2 uch #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 106 1.2 uch #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 107 1.1 uch #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 108 1.1 uch #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 109 1.1 uch #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 110 1.1 uch #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 111 1.1 uch 112 1.1 uch /* PC-card interrupt detection register */ 113 1.1 uch #define PLUM_INT_PCCLKSL_REG 0x220 114 1.1 uch #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 115 1.1 uch 116 1.2 uch /* 117 1.2 uch * USB interrupts 118 1.2 uch */ 119 1.1 uch /* USB interrupt enable register */ 120 1.1 uch #define PLUM_INT_USBINTEN_REG 0x310 121 1.1 uch 122 1.2 uch /* master-enables the USB interrupts */ 123 1.2 uch #define PLUM_INT_USBINTEN_IEN 0x00000002 124 1.2 uch /* enbales the clock restart request interrupts */ 125 1.2 uch #define PLUM_INT_USBINTEN_WIEN 0x00000001 126 1.1 uch 127 1.2 uch /* 128 1.2 uch * SmartMedia interrupts 129 1.2 uch */ 130 1.1 uch /* SmartMedia interrupt enable register */ 131 1.1 uch #define PLUM_INT_SMIEN_REG 0x410 132 1.1 uch 133 1.1 uch #define PLUM_INT_SMIEN 0x00000001 134
Indexes created Thu Oct 23 22:10:10 GMT 2025