plumicureg.h revision 1.3
1 1.3 uch /* $NetBSD: plumicureg.h,v 1.3 2001/09/15 12:47:06 uch Exp $ */ 2 1.1 uch 3 1.3 uch /*- 4 1.3 uch * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.3 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.3 uch * by UCHIYAMA Yasushi. 9 1.3 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.3 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.3 uch * notice, this list of conditions and the following disclaimer in the 17 1.3 uch * documentation and/or other materials provided with the distribution. 18 1.3 uch * 3. All advertising materials mentioning features or use of this software 19 1.3 uch * must display the following acknowledgement: 20 1.3 uch * This product includes software developed by the NetBSD 21 1.3 uch * Foundation, Inc. and its contributors. 22 1.3 uch * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.3 uch * contributors may be used to endorse or promote products derived 24 1.3 uch * from this software without specific prior written permission. 25 1.1 uch * 26 1.3 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.3 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.3 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.3 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.3 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.3 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.3 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.3 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.3 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.3 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.3 uch * POSSIBILITY OF SUCH DAMAGE. 37 1.1 uch */ 38 1.1 uch 39 1.1 uch /* 40 1.2 uch * PLUM2 INTERRUPT CONTROLLER UNIT 41 1.1 uch */ 42 1.1 uch #define PLUM_INT_REGBASE 0x8000 43 1.1 uch #define PLUM_INT_REGSIZE 0x1000 44 1.1 uch 45 1.2 uch /* 46 1.2 uch * Interrupt status register 47 1.2 uch */ 48 1.1 uch #define PLUM_INT_INTSTA_REG 0x000 49 1.1 uch #define PLUM_INT_INTSTA_EXTINT 0x00000080 50 1.1 uch #define PLUM_INT_INTSTA_SMINT 0x00000040 51 1.1 uch #define PLUM_INT_INTSTA_USBWAKE 0x00000020 52 1.1 uch #define PLUM_INT_INTSTA_USBINT 0x00000010 53 1.1 uch #define PLUM_INT_INTSTA_DISPINT 0x00000008 54 1.1 uch #define PLUM_INT_INTSTA_C2SCINT 0x00000004 55 1.1 uch #define PLUM_INT_INTSTA_C1SCINT 0x00000002 56 1.1 uch #define PLUM_INT_INTSTA_PCCINT 0x00000001 57 1.1 uch 58 1.2 uch /* 59 1.2 uch * Interrupt enable register 60 1.2 uch */ 61 1.1 uch #define PLUM_INT_INTIEN_REG 0x010 62 1.1 uch #define PLUM_INT_INTIEN 0x00000001 63 1.1 uch 64 1.2 uch /* 65 1.2 uch * External interrupts 66 1.2 uch */ 67 1.1 uch /* outside input interrupt status register */ 68 1.1 uch #define PLUM_INT_EXTINTS_REG 0x100 69 1.1 uch 70 1.2 uch #define PLUM_INT_EXTINTS_IO3INT1 0x00000020 71 1.2 uch #define PLUM_INT_EXTINTS_IO3INT0 0x00000010 72 1.2 uch #define PLUM_INT_EXTINTS_IO5INT3 0x00000008 73 1.2 uch #define PLUM_INT_EXTINTS_IO5INT2 0x00000004 74 1.2 uch #define PLUM_INT_EXTINTS_IO5INT1 0x00000002 75 1.2 uch #define PLUM_INT_EXTINTS_IO5INT0 0x00000001 76 1.2 uch 77 1.2 uch /* outside input interrupt status register (after the mask) */ 78 1.1 uch #define PLUM_INT_EXTINTM_REG 0x104 79 1.2 uch 80 1.2 uch /* interrupt enable register from the outside input */ 81 1.1 uch #define PLUM_INT_EXTIEN_REG 0x110 82 1.1 uch 83 1.2 uch #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020 84 1.2 uch #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010 85 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008 86 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004 87 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002 88 1.2 uch #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001 89 1.2 uch 90 1.2 uch #define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000 91 1.2 uch #define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000 92 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800 93 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400 94 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200 95 1.2 uch #define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100 96 1.1 uch 97 1.2 uch /* 98 1.2 uch * PC-card interrupts 99 1.2 uch */ 100 1.1 uch /* PC-card interrupt status register */ 101 1.1 uch #define PLUM_INT_PCCINTS_REG 0x200 102 1.2 uch 103 1.1 uch #define PLUM_INT_PCCINTS_C2RI 0x00000008 104 1.1 uch #define PLUM_INT_PCCINTS_C2IO 0x00000004 105 1.1 uch #define PLUM_INT_PCCINTS_C1RI 0x00000002 106 1.1 uch #define PLUM_INT_PCCINTS_C1IO 0x00000001 107 1.1 uch 108 1.1 uch /* PC-card interrupt status register (masked) */ 109 1.1 uch #define PLUM_INT_PCCINTM_REG 0x204 110 1.1 uch /* PC-card interrupt enable register */ 111 1.1 uch #define PLUM_INT_PCCIEN_REG 0x210 112 1.1 uch 113 1.2 uch #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 114 1.2 uch #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 115 1.2 uch #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 116 1.2 uch #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 117 1.1 uch #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 118 1.1 uch #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 119 1.1 uch #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 120 1.1 uch #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 121 1.1 uch 122 1.1 uch /* PC-card interrupt detection register */ 123 1.1 uch #define PLUM_INT_PCCLKSL_REG 0x220 124 1.1 uch #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 125 1.1 uch 126 1.2 uch /* 127 1.2 uch * USB interrupts 128 1.2 uch */ 129 1.1 uch /* USB interrupt enable register */ 130 1.1 uch #define PLUM_INT_USBINTEN_REG 0x310 131 1.1 uch 132 1.2 uch /* master-enables the USB interrupts */ 133 1.2 uch #define PLUM_INT_USBINTEN_IEN 0x00000002 134 1.2 uch /* enbales the clock restart request interrupts */ 135 1.2 uch #define PLUM_INT_USBINTEN_WIEN 0x00000001 136 1.1 uch 137 1.2 uch /* 138 1.2 uch * SmartMedia interrupts 139 1.2 uch */ 140 1.1 uch /* SmartMedia interrupt enable register */ 141 1.1 uch #define PLUM_INT_SMIEN_REG 0x410 142 1.1 uch 143 1.1 uch #define PLUM_INT_SMIEN 0x00000001 144
Indexes created Sat Sep 27 22:09:54 GMT 2025