plumicureg.h revision 1.1
1 /* $NetBSD: plumicureg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * INTERRUPT CONTROLLER 31 */ 32 #define PLUM_INT_REGBASE 0x8000 33 #define PLUM_INT_REGSIZE 0x1000 34 35 /* interrupt status register */ 36 #define PLUM_INT_INTSTA_REG 0x000 37 #define PLUM_INT_INTSTA_EXTINT 0x00000080 38 #define PLUM_INT_INTSTA_SMINT 0x00000040 39 #define PLUM_INT_INTSTA_USBWAKE 0x00000020 40 #define PLUM_INT_INTSTA_USBINT 0x00000010 41 #define PLUM_INT_INTSTA_DISPINT 0x00000008 42 #define PLUM_INT_INTSTA_C2SCINT 0x00000004 43 #define PLUM_INT_INTSTA_C1SCINT 0x00000002 44 #define PLUM_INT_INTSTA_PCCINT 0x00000001 45 46 /* interrupt enable register */ 47 #define PLUM_INT_INTIEN_REG 0x010 48 #define PLUM_INT_INTIEN 0x00000001 49 50 /* outside input interrupt status register */ 51 #define PLUM_INT_EXTINTS_REG 0x100 52 #define PLUM_INT_EXTINTS_IO5INT0 0x00000020 53 #define PLUM_INT_EXTINTS_IO5INT1 0x00000010 54 #define PLUM_INT_EXTINTS_IO5INT2 0x00000008 55 #define PLUM_INT_EXTINTS_IO5INT3 0x00000004 56 #define PLUM_INT_EXTINTS_IO3INT0 0x00000002 57 #define PLUM_INT_EXTINTS_IO3INT1 0x00000001 58 59 #define PLUM_INT_EXTINTM_REG 0x104 60 #define PLUM_INT_EXTIEN_REG 0x110 61 62 #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000020 63 #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000010 64 #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000008 65 #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000004 66 #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000002 67 #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000001 68 #define PLUM_INT_EXTIEN_SENIO5INT0 0x00002000 69 #define PLUM_INT_EXTIEN_SENIO5INT1 0x00001000 70 #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000800 71 #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000400 72 #define PLUM_INT_EXTIEN_SENIO3INT0 0x00000200 73 #define PLUM_INT_EXTIEN_SENIO3INT1 0x00000100 74 75 76 /* PC-card interrupt status register */ 77 #define PLUM_INT_PCCINTS_REG 0x200 78 #define PLUM_INT_PCCINTS_C2RI 0x00000008 79 #define PLUM_INT_PCCINTS_C2IO 0x00000004 80 #define PLUM_INT_PCCINTS_C1RI 0x00000002 81 #define PLUM_INT_PCCINTS_C1IO 0x00000001 82 83 /* PC-card interrupt status register (masked) */ 84 #define PLUM_INT_PCCINTM_REG 0x204 85 /* PC-card interrupt enable register */ 86 #define PLUM_INT_PCCIEN_REG 0x210 87 88 #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 89 #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 90 #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 91 #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 92 #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 93 #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 94 #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 95 #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 96 97 /* PC-card interrupt detection register */ 98 #define PLUM_INT_PCCLKSL_REG 0x220 99 #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 100 101 /* USB interrupt enable register */ 102 #define PLUM_INT_USBINTEN_REG 0x310 103 104 #define PLUM_INT_USBINTEN_WIEN 0x00000002 105 #define PLUM_INT_USBINTEN_IEN 0x00000001 106 107 /* SmartMedia interrupt enable register */ 108 #define PLUM_INT_SMIEN_REG 0x410 109 110 #define PLUM_INT_SMIEN 0x00000001 111
Indexes created Tue Sep 30 07:10:03 GMT 2025