plumicureg.h revision 1.2
1 /* $NetBSD: plumicureg.h,v 1.2 1999/12/07 17:53:04 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * PLUM2 INTERRUPT CONTROLLER UNIT 31 */ 32 #define PLUM_INT_REGBASE 0x8000 33 #define PLUM_INT_REGSIZE 0x1000 34 35 /* 36 * Interrupt status register 37 */ 38 #define PLUM_INT_INTSTA_REG 0x000 39 #define PLUM_INT_INTSTA_EXTINT 0x00000080 40 #define PLUM_INT_INTSTA_SMINT 0x00000040 41 #define PLUM_INT_INTSTA_USBWAKE 0x00000020 42 #define PLUM_INT_INTSTA_USBINT 0x00000010 43 #define PLUM_INT_INTSTA_DISPINT 0x00000008 44 #define PLUM_INT_INTSTA_C2SCINT 0x00000004 45 #define PLUM_INT_INTSTA_C1SCINT 0x00000002 46 #define PLUM_INT_INTSTA_PCCINT 0x00000001 47 48 /* 49 * Interrupt enable register 50 */ 51 #define PLUM_INT_INTIEN_REG 0x010 52 #define PLUM_INT_INTIEN 0x00000001 53 54 /* 55 * External interrupts 56 */ 57 /* outside input interrupt status register */ 58 #define PLUM_INT_EXTINTS_REG 0x100 59 60 #define PLUM_INT_EXTINTS_IO3INT1 0x00000020 61 #define PLUM_INT_EXTINTS_IO3INT0 0x00000010 62 #define PLUM_INT_EXTINTS_IO5INT3 0x00000008 63 #define PLUM_INT_EXTINTS_IO5INT2 0x00000004 64 #define PLUM_INT_EXTINTS_IO5INT1 0x00000002 65 #define PLUM_INT_EXTINTS_IO5INT0 0x00000001 66 67 /* outside input interrupt status register (after the mask) */ 68 #define PLUM_INT_EXTINTM_REG 0x104 69 70 /* interrupt enable register from the outside input */ 71 #define PLUM_INT_EXTIEN_REG 0x110 72 73 #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020 74 #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010 75 #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008 76 #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004 77 #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002 78 #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001 79 80 #define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000 81 #define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000 82 #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800 83 #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400 84 #define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200 85 #define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100 86 87 /* 88 * PC-card interrupts 89 */ 90 /* PC-card interrupt status register */ 91 #define PLUM_INT_PCCINTS_REG 0x200 92 93 #define PLUM_INT_PCCINTS_C2RI 0x00000008 94 #define PLUM_INT_PCCINTS_C2IO 0x00000004 95 #define PLUM_INT_PCCINTS_C1RI 0x00000002 96 #define PLUM_INT_PCCINTS_C1IO 0x00000001 97 98 /* PC-card interrupt status register (masked) */ 99 #define PLUM_INT_PCCINTM_REG 0x204 100 /* PC-card interrupt enable register */ 101 #define PLUM_INT_PCCIEN_REG 0x210 102 103 #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 104 #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 105 #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 106 #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 107 #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 108 #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 109 #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 110 #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 111 112 /* PC-card interrupt detection register */ 113 #define PLUM_INT_PCCLKSL_REG 0x220 114 #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 115 116 /* 117 * USB interrupts 118 */ 119 /* USB interrupt enable register */ 120 #define PLUM_INT_USBINTEN_REG 0x310 121 122 /* master-enables the USB interrupts */ 123 #define PLUM_INT_USBINTEN_IEN 0x00000002 124 /* enbales the clock restart request interrupts */ 125 #define PLUM_INT_USBINTEN_WIEN 0x00000001 126 127 /* 128 * SmartMedia interrupts 129 */ 130 /* SmartMedia interrupt enable register */ 131 #define PLUM_INT_SMIEN_REG 0x410 132 133 #define PLUM_INT_SMIEN 0x00000001 134
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