plumicureg.h revision 1.3
1 /* $NetBSD: plumicureg.h,v 1.3 2001/09/15 12:47:06 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * PLUM2 INTERRUPT CONTROLLER UNIT 41 */ 42 #define PLUM_INT_REGBASE 0x8000 43 #define PLUM_INT_REGSIZE 0x1000 44 45 /* 46 * Interrupt status register 47 */ 48 #define PLUM_INT_INTSTA_REG 0x000 49 #define PLUM_INT_INTSTA_EXTINT 0x00000080 50 #define PLUM_INT_INTSTA_SMINT 0x00000040 51 #define PLUM_INT_INTSTA_USBWAKE 0x00000020 52 #define PLUM_INT_INTSTA_USBINT 0x00000010 53 #define PLUM_INT_INTSTA_DISPINT 0x00000008 54 #define PLUM_INT_INTSTA_C2SCINT 0x00000004 55 #define PLUM_INT_INTSTA_C1SCINT 0x00000002 56 #define PLUM_INT_INTSTA_PCCINT 0x00000001 57 58 /* 59 * Interrupt enable register 60 */ 61 #define PLUM_INT_INTIEN_REG 0x010 62 #define PLUM_INT_INTIEN 0x00000001 63 64 /* 65 * External interrupts 66 */ 67 /* outside input interrupt status register */ 68 #define PLUM_INT_EXTINTS_REG 0x100 69 70 #define PLUM_INT_EXTINTS_IO3INT1 0x00000020 71 #define PLUM_INT_EXTINTS_IO3INT0 0x00000010 72 #define PLUM_INT_EXTINTS_IO5INT3 0x00000008 73 #define PLUM_INT_EXTINTS_IO5INT2 0x00000004 74 #define PLUM_INT_EXTINTS_IO5INT1 0x00000002 75 #define PLUM_INT_EXTINTS_IO5INT0 0x00000001 76 77 /* outside input interrupt status register (after the mask) */ 78 #define PLUM_INT_EXTINTM_REG 0x104 79 80 /* interrupt enable register from the outside input */ 81 #define PLUM_INT_EXTIEN_REG 0x110 82 83 #define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020 84 #define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010 85 #define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008 86 #define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004 87 #define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002 88 #define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001 89 90 #define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000 91 #define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000 92 #define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800 93 #define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400 94 #define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200 95 #define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100 96 97 /* 98 * PC-card interrupts 99 */ 100 /* PC-card interrupt status register */ 101 #define PLUM_INT_PCCINTS_REG 0x200 102 103 #define PLUM_INT_PCCINTS_C2RI 0x00000008 104 #define PLUM_INT_PCCINTS_C2IO 0x00000004 105 #define PLUM_INT_PCCINTS_C1RI 0x00000002 106 #define PLUM_INT_PCCINTS_C1IO 0x00000001 107 108 /* PC-card interrupt status register (masked) */ 109 #define PLUM_INT_PCCINTM_REG 0x204 110 /* PC-card interrupt enable register */ 111 #define PLUM_INT_PCCIEN_REG 0x210 112 113 #define PLUM_INT_PCCIEN_SENC2RI 0x00000800 114 #define PLUM_INT_PCCIEN_SENC2IO 0x00000400 115 #define PLUM_INT_PCCIEN_SENC1RI 0x00000200 116 #define PLUM_INT_PCCIEN_SENC1IO 0x00000100 117 #define PLUM_INT_PCCIEN_IENC2RI 0x00000008 118 #define PLUM_INT_PCCIEN_IENC2IO 0x00000004 119 #define PLUM_INT_PCCIEN_IENC1RI 0x00000002 120 #define PLUM_INT_PCCIEN_IENC1IO 0x00000001 121 122 /* PC-card interrupt detection register */ 123 #define PLUM_INT_PCCLKSL_REG 0x220 124 #define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/ 125 126 /* 127 * USB interrupts 128 */ 129 /* USB interrupt enable register */ 130 #define PLUM_INT_USBINTEN_REG 0x310 131 132 /* master-enables the USB interrupts */ 133 #define PLUM_INT_USBINTEN_IEN 0x00000002 134 /* enbales the clock restart request interrupts */ 135 #define PLUM_INT_USBINTEN_WIEN 0x00000001 136 137 /* 138 * SmartMedia interrupts 139 */ 140 /* SmartMedia interrupt enable register */ 141 #define PLUM_INT_SMIEN_REG 0x410 142 143 #define PLUM_INT_SMIEN 0x00000001 144
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