plumiobusreg.h revision 1.4
1 1.4 andvar /* $NetBSD: plumiobusreg.h,v 1.4 2023/12/08 22:11:15 andvar Exp $ */ 2 1.1 uch 3 1.2 uch /*- 4 1.2 uch * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.2 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.2 uch * by UCHIYAMA Yasushi. 9 1.2 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.2 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 uch * notice, this list of conditions and the following disclaimer in the 17 1.2 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.2 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.2 uch 32 1.1 uch /* (CS3) */ 33 1.1 uch #define PLUM_IOBUS_REGBASE 0x6000 34 1.1 uch #define PLUM_IOBUS_REGSIZE 0x1000 35 1.1 uch 36 1.4 andvar /* I/O bus width setting */ 37 1.1 uch #define PLUM_IOBUS_IOXBSZ_REG 0x000 38 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE5 0x00000020 39 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE4 0x00000010 40 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE3 0x00000008 41 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE2 0x00000004 42 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE1 0x00000002 43 1.1 uch #define PLUM_IOBUS_IOXBSZ_IO5BE0 0x00000001 44 1.1 uch 45 1.1 uch /* I/O bus wait control 1 (# of wait from the access beginning) */ 46 1.1 uch #define PLUM_IOBUS_IOXCCNT_REG 0x004 47 1.1 uch #define PLUM_IOBUS_IOXCCNT_MASK 0x7 48 1.1 uch /* I/O bus wait control 2 (# of wait in access) */ 49 1.1 uch #define PLUM_IOBUS_IOXACNT_REG 0x008 50 1.1 uch #define PLUM_IOBUS_IOXACNT_MASK 0x1f 51 1.1 uch #define PLUM_IOBUS_IOXACNT_SHIFT 5 52 1.1 uch /* I/O bus wait control 3 (# of wait during access) */ 53 1.1 uch #define PLUM_IOBUS_IOXSCNT_REG 0x00c 54 1.1 uch #define PLUM_IOBUS_IOXSCNT_MASK 0x7 55 1.1 uch /* IDE mode setting */ 56 1.1 uch #define PLUM_IOBUS_IDEMODE_REG 0x010 57 1.1 uch #define PLUM_IOBUS_IDEMODE 0x00000001 58 1.1 uch 59 1.1 uch /* (MCS0) */ 60 1.1 uch #define PLUM_IOBUS_IOBASE 0x00410000 61 1.1 uch #define PLUM_IOBUS_IOSIZE 0x6000 62 1.1 uch 63 1.1 uch #define PLUM_IOBUS_IO5CS0BASE 0x0000 64 1.1 uch #define PLUM_IOBUS_IO5CS1BASE 0x1000 65 1.1 uch #define PLUM_IOBUS_IO5CS2BASE 0x2000 66 1.1 uch #define PLUM_IOBUS_IO5CS3BASE 0x3000 67 1.1 uch #define PLUM_IOBUS_IO5CS4BASE 0x4000 68 1.1 uch #define PLUM_IOBUS_IO5CS5BASE 0x5000 69 1.1 uch #define PLUM_IOBUS_IO5SIZE 0x1000 70
Indexes created Thu Oct 02 01:09:59 GMT 2025