plumiobusreg.h revision 1.1
1 /* $NetBSD: plumiobusreg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* (CS3) */ 29 #define PLUM_IOBUS_REGBASE 0x6000 30 #define PLUM_IOBUS_REGSIZE 0x1000 31 32 /* I/O bus width settting */ 33 #define PLUM_IOBUS_IOXBSZ_REG 0x000 34 #define PLUM_IOBUS_IOXBSZ_IO5BE5 0x00000020 35 #define PLUM_IOBUS_IOXBSZ_IO5BE4 0x00000010 36 #define PLUM_IOBUS_IOXBSZ_IO5BE3 0x00000008 37 #define PLUM_IOBUS_IOXBSZ_IO5BE2 0x00000004 38 #define PLUM_IOBUS_IOXBSZ_IO5BE1 0x00000002 39 #define PLUM_IOBUS_IOXBSZ_IO5BE0 0x00000001 40 41 /* I/O bus wait control 1 (# of wait from the access beginning) */ 42 #define PLUM_IOBUS_IOXCCNT_REG 0x004 43 #define PLUM_IOBUS_IOXCCNT_MASK 0x7 44 /* I/O bus wait control 2 (# of wait in access) */ 45 #define PLUM_IOBUS_IOXACNT_REG 0x008 46 #define PLUM_IOBUS_IOXACNT_MASK 0x1f 47 #define PLUM_IOBUS_IOXACNT_SHIFT 5 48 /* I/O bus wait control 3 (# of wait during access) */ 49 #define PLUM_IOBUS_IOXSCNT_REG 0x00c 50 #define PLUM_IOBUS_IOXSCNT_MASK 0x7 51 /* IDE mode setting */ 52 #define PLUM_IOBUS_IDEMODE_REG 0x010 53 #define PLUM_IOBUS_IDEMODE 0x00000001 54 55 /* (MCS0) */ 56 #define PLUM_IOBUS_IOBASE 0x00410000 57 #define PLUM_IOBUS_IOSIZE 0x6000 58 59 #define PLUM_IOBUS_IO5CS0BASE 0x0000 60 #define PLUM_IOBUS_IO5CS1BASE 0x1000 61 #define PLUM_IOBUS_IO5CS2BASE 0x2000 62 #define PLUM_IOBUS_IO5CS3BASE 0x3000 63 #define PLUM_IOBUS_IO5CS4BASE 0x4000 64 #define PLUM_IOBUS_IO5CS5BASE 0x5000 65 #define PLUM_IOBUS_IO5SIZE 0x1000 66
Indexes created Thu Oct 02 07:10:07 GMT 2025