plumiobusreg.h revision 1.2
1 /* $NetBSD: plumiobusreg.h,v 1.2 2001/09/15 12:47:06 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* (CS3) */ 40 #define PLUM_IOBUS_REGBASE 0x6000 41 #define PLUM_IOBUS_REGSIZE 0x1000 42 43 /* I/O bus width settting */ 44 #define PLUM_IOBUS_IOXBSZ_REG 0x000 45 #define PLUM_IOBUS_IOXBSZ_IO5BE5 0x00000020 46 #define PLUM_IOBUS_IOXBSZ_IO5BE4 0x00000010 47 #define PLUM_IOBUS_IOXBSZ_IO5BE3 0x00000008 48 #define PLUM_IOBUS_IOXBSZ_IO5BE2 0x00000004 49 #define PLUM_IOBUS_IOXBSZ_IO5BE1 0x00000002 50 #define PLUM_IOBUS_IOXBSZ_IO5BE0 0x00000001 51 52 /* I/O bus wait control 1 (# of wait from the access beginning) */ 53 #define PLUM_IOBUS_IOXCCNT_REG 0x004 54 #define PLUM_IOBUS_IOXCCNT_MASK 0x7 55 /* I/O bus wait control 2 (# of wait in access) */ 56 #define PLUM_IOBUS_IOXACNT_REG 0x008 57 #define PLUM_IOBUS_IOXACNT_MASK 0x1f 58 #define PLUM_IOBUS_IOXACNT_SHIFT 5 59 /* I/O bus wait control 3 (# of wait during access) */ 60 #define PLUM_IOBUS_IOXSCNT_REG 0x00c 61 #define PLUM_IOBUS_IOXSCNT_MASK 0x7 62 /* IDE mode setting */ 63 #define PLUM_IOBUS_IDEMODE_REG 0x010 64 #define PLUM_IOBUS_IDEMODE 0x00000001 65 66 /* (MCS0) */ 67 #define PLUM_IOBUS_IOBASE 0x00410000 68 #define PLUM_IOBUS_IOSIZE 0x6000 69 70 #define PLUM_IOBUS_IO5CS0BASE 0x0000 71 #define PLUM_IOBUS_IO5CS1BASE 0x1000 72 #define PLUM_IOBUS_IO5CS2BASE 0x2000 73 #define PLUM_IOBUS_IO5CS3BASE 0x3000 74 #define PLUM_IOBUS_IO5CS4BASE 0x4000 75 #define PLUM_IOBUS_IO5CS5BASE 0x5000 76 #define PLUM_IOBUS_IO5SIZE 0x1000 77
Indexes created Thu Oct 02 07:10:07 GMT 2025