plumpcmciareg.h revision 1.2
1 /* $NetBSD: plumpcmciareg.h,v 1.2 2000/09/27 17:32:34 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* (CS3) */ 29 #define PLUM_PCMCIA_REGBASE 0x5000 30 #define PLUM_PCMCIA_REGSIZE 0x1000 31 32 /* (MCS0) */ 33 /* 1MByte */ 34 #define PLUM_PCMCIA_IOBASE1 0x00600000 35 #define PLUM_PCMCIA_IOSIZE1 0x00100000 36 /* 1MByte */ 37 #define PLUM_PCMCIA_IOBASE2 0x00700000 38 #define PLUM_PCMCIA_IOSIZE2 0x00100000 39 /* 8Mbyte */ 40 #define PLUM_PCMCIA_MEMBASE1 0x00800000 41 #define PLUM_PCMCIA_MEMSIZE1 0x00800000 42 /* 16MByte */ 43 #define PLUM_PCMCIA_MEMBASE2 0x01000000 44 #define PLUM_PCMCIA_MEMSIZE2 0x01000000 45 /* 32MByte */ 46 #define PLUM_PCMCIA_MEMBASE3 0x02000000 47 #define PLUM_PCMCIA_MEMSIZE3 0x02000000 48 /* (MCS1) */ 49 /* 64MByte */ 50 #define PLUM_PCMCIA_MEMBASE4 0x04000000 51 #define PLUM_PCMCIA_MEMSIZE4 0x04000000 52 53 /* 54 * # of slots 55 */ 56 #define PLUMPCMCIA_NSLOTS 2 57 /* 58 * Control registers. 59 */ 60 #define PLUM_PCMCIA_REGSPACE_SLOT0 0 61 #define PLUM_PCMCIA_REGSPACE_SLOT1 0x800 62 #define PLUM_PCMCIA_REGSPACE_SIZE 0x800 63 64 #define PLUM_PCMCIA_IDENT 0x000 65 #define PLUM_PCMCIA_STATUS 0x004 66 #define PLUM_PCMCIA_STATUS_BVD1 0x01 67 #define PLUM_PCMCIA_STATUS_BVD2 0x02 68 #define PLUM_PCMCIA_STATUS_CD1 0x04 69 #define PLUM_PCMCIA_STATUS_CD2 0x08 70 #define PLUM_PCMCIA_STATUS_WRITEPROTECT 0x10 71 #define PLUM_PCMCIA_STATUS_READY 0x20 /* really READY/!BUSY */ 72 #define PLUM_PCMCIA_STATUS_PWROK 0x40 73 74 #define PLUM_PCMCIA_PWRCTRL 0x008 75 #define PLUM_PCMCIA_PWRCTRL_OE 0x80 /* output enable */ 76 #define PLUM_PCMCIA_PWRCTRL_DISABLE_RESETDRV 0x40 77 #define PLUM_PCMCIA_PWRCTRL_AUTOSWITCH_ENABLE 0x20 78 #define PLUM_PCMCIA_PWRCTRL_PWR_ENABLE 0x10 79 #define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT1 0x08 80 #define PLUM_PCMCIA_PWRCTRL_VCC_CTRLBIT0 0x04 81 #define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT1 0x02 82 #define PLUM_PCMCIA_PWRCTRL_VPP1_CTRLBIT0 0x01 83 84 #define PLUM_PCMCIA_GENCTRL 0x00c 85 #define PLUM_PCMCIA_GENCTRL_RESET 0x40 /* active low (zero) */ 86 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_MASK 0x20 87 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_IO 0x20 88 #define PLUM_PCMCIA_GENCTRL_CARDTYPE_MEM 0x00 89 90 #define PLUM_PCMCIA_CSCINT_STAT 0x010 91 #define PLUM_PCMCIA_CSCINT 0x014 92 #define PLUM_PCMCIA_CSCINT_BATTERY_DEAD 0x01 93 #define PLUM_PCMCIA_CSCINT_BATTERY_WARNING 0x02 94 #define PLUM_PCMCIA_CSCINT_READY 0x04 95 #define PLUM_PCMCIA_CSCINT_CARD_DETECT 0x08 96 97 #define PLUM_PCMCIA_WINEN 0x018 98 #define PLUM_PCMCIA_WINEN_IO1 0x00000080 99 #define PLUM_PCMCIA_WINEN_IO0 0x00000040 100 #define PLUM_PCMCIA_WINEN_MEM4 0x00000010 101 #define PLUM_PCMCIA_WINEN_MEM3 0x00000008 102 #define PLUM_PCMCIA_WINEN_MEM2 0x00000004 103 #define PLUM_PCMCIA_WINEN_MEM1 0x00000002 104 #define PLUM_PCMCIA_WINEN_MEM0 0x00000001 105 #define PLUM_PCMCIA_WINEN_MEM(x) (1 << (x)) 106 107 #define PLUM_PCMCIA_MEM_WINS 5 108 #define PLUM_PCMCIA_MEM_SHIFT 12 109 #define PLUM_PCMCIA_MEM_PAGESIZE (1<<PLUM_PCMCIA_MEM_SHIFT) 110 111 #define PLUM_PCMCIA_IO_WINS 2 112 113 #define PLUM_PCMCIA_IOWINCTRL 0x01c 114 #define PLUM_PCMCIA_IOWINCTRL_WINMASK 0x0000000f 115 #define PLUM_PCMCIA_IOWINCTRL_WIN0SHIFT 0 116 #define PLUM_PCMCIA_IOWINCTRL_WIN1SHIFT 4 117 #define PLUM_PCMCIA_IOWINCTRL_DATASIZE16 0x00000001 118 #define PLUM_PCMCIA_IOWINCTRL_IOCS16SRC 0x00000002 119 #define PLUM_PCMCIA_IOWINCTRL_ZEROWAIT 0x00000004 120 #define PLUM_PCMCIA_IOWINCTRL_WAITSTATE 0x00000008 121 122 #define PLUM_PCMCIA_IOWIN0STARTADDR 0x020 123 #define PLUM_PCMCIA_IOWIN1STARTADDR 0x030 124 #define PLUM_PCMCIA_IOWINSTARTADDR(x) \ 125 ((x) * 0x10 + PLUM_PCMCIA_IOWIN0STARTADDR) 126 127 #define PLUM_PCMCIA_IOWIN0STOPADDR 0x024 128 #define PLUM_PCMCIA_IOWIN1STOPADDR 0x034 129 #define PLUM_PCMCIA_IOWINSTOPADDR(x) \ 130 ((x) * 0x10 + PLUM_PCMCIA_IOWIN0STOPADDR) 131 132 #define PLUM_PCMCIA_IOWIN0ADDRCTRL 0x028 133 #define PLUM_PCMCIA_IOWIN1ADDRCTRL 0x038 134 #define PLUM_PCMCIA_IOWINADDRCTRL(x) \ 135 ((x) * 0x10 + PLUM_PCMCIA_IOWIN0ADDRCTRL) 136 137 #define PLUM_PCMCIA_IOWINADDRCTRL_AREA1 0x00000000 138 #define PLUM_PCMCIA_IOWINADDRCTRL_AREA2 0x00000001 139 140 #define PLUM_PCMCIA_MEMWIN0STARTADDR 0x040 141 #define PLUM_PCMCIA_MEMWIN1STARTADDR 0x060 142 #define PLUM_PCMCIA_MEMWIN2STARTADDR 0x080 143 #define PLUM_PCMCIA_MEMWIN3STARTADDR 0x0a0 144 #define PLUM_PCMCIA_MEMWIN4STARTADDR 0x0c0 145 #define PLUM_PCMCIA_MEMWINSTARTADDR(x) \ 146 ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STARTADDR) 147 148 #define PLUM_PCMCIA_MEMWIN0STOPADDR 0x044 149 #define PLUM_PCMCIA_MEMWIN1STOPADDR 0x064 150 #define PLUM_PCMCIA_MEMWIN2STOPADDR 0x084 151 #define PLUM_PCMCIA_MEMWIN3STOPADDR 0x0a4 152 #define PLUM_PCMCIA_MEMWIN4STOPADDR 0x0c4 153 #define PLUM_PCMCIA_MEMWINSTOPADDR(x) \ 154 ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0STOPADDR) 155 156 #define PLUM_PCMCIA_MEMWIN0OFSADDR 0x048 157 #define PLUM_PCMCIA_MEMWIN1OFSADDR 0x068 158 #define PLUM_PCMCIA_MEMWIN2OFSADDR 0x088 159 #define PLUM_PCMCIA_MEMWIN3OFSADDR 0x0a8 160 #define PLUM_PCMCIA_MEMWIN4OFSADDR 0x0c8 161 #define PLUM_PCMCIA_MEMWINOFSADDR(x) \ 162 ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0OFSADDR) 163 164 #define PLUM_PCMCIA_MEMWIN0CTRL 0x04c 165 #define PLUM_PCMCIA_MEMWIN1CTRL 0x06c 166 #define PLUM_PCMCIA_MEMWIN2CTRL 0x08c 167 #define PLUM_PCMCIA_MEMWIN3CTRL 0x0ac 168 #define PLUM_PCMCIA_MEMWIN4CTRL 0x0cc 169 #define PLUM_PCMCIA_MEMWINCTRL(x) \ 170 ((x) * 0x20 + PLUM_PCMCIA_MEMWIN0CTRL) 171 172 #define PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT 24 173 #define PLUM_PCMCIA_MEMWINCTRL_MAP_MASK 0x3 174 #define PLUM_PCMCIA_MEMWINCTRL_MAP(cr) \ 175 (((cr) >> PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) & \ 176 PLUM_PCMCIA_MEMWINCTRL_MAP_MASK) 177 #define PLUM_PCMCIA_MEMWINCTRL_MAP_SET(cr, val) \ 178 ((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT) & \ 179 (PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT))) 180 #define PLUM_PCMCIA_MEMWINCTRL_MAP_CLEAR(cr) \ 181 ((cr) &= ~(PLUM_PCMCIA_MEMWINCTRL_MAP_MASK << PLUM_PCMCIA_MEMWINCTRL_MAP_SHIFT)) 182 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA1 0x0 183 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA2 0x1 184 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA3 0x2 185 #define PLUM_PCMCIA_MEMWINCTRL_MAP_AREA4 0x3 186 187 #define PLUM_PCMCIA_MEMWINCTRL_WRPROTECT 0x00800000 188 #define PLUM_PCMCIA_MEMWINCTRL_REGACTIVE 0x00400000 189 #define PLUM_PCMCIA_MEMWINCTRL_DATASIZE16 0x00000080 190 #define PLUM_PCMCIA_MEMWINCTRL_ZERO_WS 0x00000040 191 192 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT 14 193 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK 0x3 194 #define PLUM_PCMCIA_MEMWINCTRL_TIMING(cr) \ 195 (((cr) >> PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) & \ 196 PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK) 197 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_SET(cr, val) \ 198 ((cr) | (((val) << PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT) & \ 199 (PLUM_PCMCIA_MEMWINCTRL_TIMING_MASK << PLUM_PCMCIA_MEMWINCTRL_TIMING_SHIFT))) 200 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_STD 0x0 201 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_1WAIT 0x1 202 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_2WAIT 0x2 203 #define PLUM_PCMCIA_MEMWINCTRL_TIMING_3WAIT 0x3 204 205 #define PLUM_PCMCIA_MEMWINCTRL_DATASIZE_16BIT 0x00000080 /* else 8bit */ 206 #define PLUM_PCMCIA_MEMWINCTRL_ZEROWS 0x00000040 207 208 #define PLUM_PCMCIA_GENCTRL2 0x058 209 #define PLUM_PCMCIA_GENCTRL2_VCC5V 0x000000c0 210 #define PLUM_PCMCIA_GENCTRL2_VCC3V 0x00000080 211 212 #define PLUM_PCMCIA_GLOBALCTRL 0x078 213 #define PLUM_PCMCIA_GLOBALCTRL_EXPLICIT_WB_CSC_INT 0x04 214 215 #define PLUM_PCMCIA_TIMING 0x0ec 216 217 #define PLUM_PCMCIA_FUNCCTRL 0x0f8 218 #define PLUM_PCMCIA_FUNCCTRL_3VSUPPORT 0x00000001 219 #define PLUM_PCMCIA_FUNCCTRL_VSSEN 0x00000002 220 221 #define PLUM_PCMCIA_SPECIALMODE 0x0fc 222 223 #define PLUM_PCMCIA_SLOTCTRL 0x100 224 #define PLUM_PCMCIA_SLOTCTRL_ENABLE 0x00000080 225 226 #define PLUM_PCMCIA_BUFOFF 0x104 227 #define PLUM_PCMCIA_CARDDETECTMODE 0x108 228 #define PLUM_PCMCIA_CARDPWRCTRL 0x10c 229
Indexes created Mon Sep 29 21:09:56 GMT 2025