plumpower.c revision 1.2
1 /* $NetBSD: plumpower.c,v 1.2 1999/12/07 17:21:45 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include "opt_tx39_debug.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 36 #include <machine/bus.h> 37 #include <machine/intr.h> 38 39 #include <hpcmips/tx/tx39var.h> 40 #include <hpcmips/dev/plumvar.h> 41 #include <hpcmips/dev/plumpowervar.h> 42 #include <hpcmips/dev/plumpowerreg.h> 43 44 int plumpower_match __P((struct device*, struct cfdata*, void*)); 45 void plumpower_attach __P((struct device*, struct device*, void*)); 46 47 struct plumpower_softc { 48 struct device sc_dev; 49 plum_chipset_tag_t sc_pc; 50 bus_space_tag_t sc_regt; 51 bus_space_handle_t sc_regh; 52 }; 53 54 struct cfattach plumpower_ca = { 55 sizeof(struct plumpower_softc), plumpower_match, plumpower_attach 56 }; 57 58 void plumpower_dump __P((struct plumpower_softc*)); 59 60 int 61 plumpower_match(parent, cf, aux) 62 struct device *parent; 63 struct cfdata *cf; 64 void *aux; 65 { 66 return 2; /* 1st attach group */ 67 } 68 69 void 70 plumpower_attach(parent, self, aux) 71 struct device *parent; 72 struct device *self; 73 void *aux; 74 { 75 struct plum_attach_args *pa = aux; 76 struct plumpower_softc *sc = (void*)self; 77 78 printf("\n"); 79 sc->sc_pc = pa->pa_pc; 80 sc->sc_regt = pa->pa_regt; 81 82 if (bus_space_map(sc->sc_regt, PLUM_POWER_REGBASE, 83 PLUM_POWER_REGSIZE, 0, &sc->sc_regh)) { 84 printf(": register map failed\n"); 85 return; 86 } 87 plum_conf_register_power(sc->sc_pc, (void*)sc); 88 89 plumpower_dump(sc); 90 91 /* disable all power/clock */ 92 plum_conf_write(sc->sc_regt, sc->sc_regh, 93 PLUM_POWER_PWRCONT_REG, 0); 94 plum_conf_write(sc->sc_regt, sc->sc_regh, 95 PLUM_POWER_CLKCONT_REG, 0); 96 delay(300 * 1000); 97 98 /* enable MCS interface from TX3922 */ 99 plum_conf_write(sc->sc_regt, sc->sc_regh, PLUM_POWER_INPENA_REG, 100 PLUM_POWER_INPENA); 101 plumpower_dump(sc); 102 } 103 104 void 105 plum_power_ioreset(pc) 106 plum_chipset_tag_t pc; 107 { 108 struct plumpower_softc *sc = pc->pc_powert; 109 bus_space_tag_t regt = sc->sc_regt; 110 bus_space_handle_t regh = sc->sc_regh; 111 112 plum_conf_write(regt, regh, PLUM_POWER_RESETC_REG, 113 PLUM_POWER_RESETC_IO5CL1 | 114 PLUM_POWER_RESETC_IO5CL1); 115 delay(100*1000); 116 plum_conf_write(regt, regh, PLUM_POWER_RESETC_REG, 0); 117 delay(100*1000); 118 } 119 120 void* 121 plum_power_establish(pc, src) 122 plum_chipset_tag_t pc; 123 int src; 124 { 125 struct plumpower_softc *sc = pc->pc_powert; 126 bus_space_tag_t regt = sc->sc_regt; 127 bus_space_handle_t regh = sc->sc_regh; 128 plumreg_t pwrreg, clkreg; 129 130 pwrreg = plum_conf_read(regt, regh, PLUM_POWER_PWRCONT_REG); 131 clkreg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG); 132 133 switch(src) { 134 default: 135 panic("plum_power_establish: unknown power source"); 136 case PLUM_PWR_LCD: 137 pwrreg |= PLUM_POWER_PWRCONT_LCDPWR; 138 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 139 pwrreg |= PLUM_POWER_PWRCONT_LCDDSP; 140 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 141 pwrreg |= PLUM_POWER_PWRCONT_LCDOE; 142 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 143 break; 144 case PLUM_PWR_BKL: 145 pwrreg |= PLUM_POWER_PWRCONT_BKLIGHT; 146 break; 147 case PLUM_PWR_IO5: 148 /* reset I/O bus (High/Low) */ 149 plum_power_ioreset(pc); 150 151 /* supply power */ 152 pwrreg |= PLUM_POWER_PWRCONT_IO5PWR; 153 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 154 delay(300*1000); 155 156 /* output enable & supply clock */ 157 pwrreg |= PLUM_POWER_PWRCONT_IO5OE; 158 clkreg |= PLUM_POWER_CLKCONT_IO5CLK; 159 break; 160 case PLUM_PWR_EXTPW0: 161 pwrreg |= PLUM_POWER_PWRCONT_EXTPW0; 162 break; 163 case PLUM_PWR_EXTPW1: 164 pwrreg |= PLUM_POWER_PWRCONT_EXTPW1; 165 break; 166 case PLUM_PWR_EXTPW2: 167 pwrreg |= PLUM_POWER_PWRCONT_EXTPW2; 168 break; 169 case PLUM_PWR_USB: 170 /* output enable */ 171 pwrreg |= PLUM_POWER_PWRCONT_USBEN; 172 /* supply clock to the USB host controller */ 173 clkreg |= PLUM_POWER_CLKCONT_USBCLK1; 174 /* clock supply is adaptively controlled by hardware */ 175 clkreg &= ~PLUM_POWER_CLKCONT_USBCLK2; 176 break; 177 case PLUM_PWR_SM: 178 clkreg |= PLUM_POWER_CLKCONT_SMCLK; 179 break; 180 case PLUM_PWR_PCC1: 181 clkreg |= PLUM_POWER_CLKCONT_PCCCLK1; 182 break; 183 case PLUM_PWR_PCC2: 184 clkreg |= PLUM_POWER_CLKCONT_PCCCLK2; 185 break; 186 } 187 188 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 189 delay(300*1000); 190 191 plum_conf_write(regt, regh, PLUM_POWER_CLKCONT_REG, clkreg); 192 delay(300*1000); 193 194 plumpower_dump(sc); 195 196 return (void*)src; 197 } 198 199 void 200 plum_power_disestablish(pc, ph) 201 plum_chipset_tag_t pc; 202 int ph; 203 { 204 struct plumpower_softc *sc = pc->pc_powert; 205 bus_space_tag_t regt = sc->sc_regt; 206 bus_space_handle_t regh = sc->sc_regh; 207 int src = (int)ph; 208 plumreg_t pwrreg, clkreg; 209 210 pwrreg = plum_conf_read(regt, regh, PLUM_POWER_PWRCONT_REG); 211 clkreg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG); 212 213 switch(src) { 214 default: 215 panic("plum_power_disestablish: unknown power source"); 216 case PLUM_PWR_LCD: 217 pwrreg &= ~(PLUM_POWER_PWRCONT_LCDOE | 218 PLUM_POWER_PWRCONT_LCDPWR | 219 PLUM_POWER_PWRCONT_LCDDSP); 220 break; 221 case PLUM_PWR_BKL: 222 pwrreg &= ~PLUM_POWER_PWRCONT_BKLIGHT; 223 break; 224 case PLUM_PWR_IO5: 225 pwrreg &= ~(PLUM_POWER_PWRCONT_IO5PWR | 226 PLUM_POWER_PWRCONT_IO5OE); 227 clkreg &= ~PLUM_POWER_CLKCONT_IO5CLK; 228 break; 229 case PLUM_PWR_EXTPW0: 230 pwrreg &= ~PLUM_POWER_PWRCONT_EXTPW0; 231 break; 232 case PLUM_PWR_EXTPW1: 233 pwrreg &= ~PLUM_POWER_PWRCONT_EXTPW1; 234 break; 235 case PLUM_PWR_EXTPW2: 236 pwrreg &= ~PLUM_POWER_PWRCONT_EXTPW2; 237 break; 238 case PLUM_PWR_USB: 239 pwrreg &= ~PLUM_POWER_PWRCONT_USBEN; 240 clkreg &= ~(PLUM_POWER_CLKCONT_USBCLK1 | 241 PLUM_POWER_CLKCONT_USBCLK2); 242 break; 243 case PLUM_PWR_SM: 244 clkreg &= ~PLUM_POWER_CLKCONT_SMCLK; 245 break; 246 case PLUM_PWR_PCC1: 247 clkreg &= ~PLUM_POWER_CLKCONT_PCCCLK1; 248 break; 249 case PLUM_PWR_PCC2: 250 clkreg &= ~PLUM_POWER_CLKCONT_PCCCLK2; 251 break; 252 } 253 254 plum_conf_write(regt, regh, PLUM_POWER_PWRCONT_REG, pwrreg); 255 plum_conf_write(regt, regh, PLUM_POWER_CLKCONT_REG, clkreg); 256 257 plumpower_dump(sc); 258 } 259 260 #define ISPOWERSUPPLY(r, m) __is_set_print(r, PLUM_POWER_PWRCONT_##m, #m) 261 #define ISCLOCKSUPPLY(r, m) __is_set_print(r, PLUM_POWER_CLKCONT_##m, #m) 262 263 void 264 plumpower_dump(sc) 265 struct plumpower_softc *sc; 266 { 267 bus_space_tag_t regt = sc->sc_regt; 268 bus_space_handle_t regh = sc->sc_regh; 269 plumreg_t reg; 270 271 reg = plum_conf_read(regt, regh, PLUM_POWER_PWRCONT_REG); 272 printf(" power:"); 273 ISPOWERSUPPLY(reg, USBEN); 274 ISPOWERSUPPLY(reg, IO5OE); 275 ISPOWERSUPPLY(reg, LCDOE); 276 ISPOWERSUPPLY(reg, EXTPW2); 277 ISPOWERSUPPLY(reg, EXTPW1); 278 ISPOWERSUPPLY(reg, EXTPW0); 279 ISPOWERSUPPLY(reg, IO5PWR); 280 ISPOWERSUPPLY(reg, BKLIGHT); 281 ISPOWERSUPPLY(reg, LCDPWR); 282 ISPOWERSUPPLY(reg, LCDDSP); 283 reg = plum_conf_read(regt, regh, PLUM_POWER_CLKCONT_REG); 284 printf("\n clock:"); 285 ISCLOCKSUPPLY(reg, USBCLK2); 286 ISCLOCKSUPPLY(reg, USBCLK1); 287 ISCLOCKSUPPLY(reg, IO5CLK); 288 ISCLOCKSUPPLY(reg, SMCLK); 289 ISCLOCKSUPPLY(reg, PCCCLK2); 290 ISCLOCKSUPPLY(reg, PCCCLK1); 291 reg = plum_conf_read(regt, regh, PLUM_POWER_INPENA_REG); 292 printf("\n MCS interface %sebled", 293 reg & PLUM_POWER_INPENA ? "en" : "dis"); 294 reg = plum_conf_read(regt, regh, PLUM_POWER_RESETC_REG); 295 printf("\n IO5 reset:%s %s", 296 reg & PLUM_POWER_RESETC_IO5CL0 ? "CLRL" : "", 297 reg & PLUM_POWER_RESETC_IO5CL1 ? "CLRH" : ""); 298 printf("\n"); 299 } 300 301 302
Indexes created Wed Sep 24 02:09:48 GMT 2025