plumvideo.c revision 1.18.2.3
1 /* $NetBSD: plumvideo.c,v 1.18.2.3 2002/01/10 19:43:54 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #undef PLUMVIDEODEBUG 40 #include "opt_tx39_debug.h" 41 #include "plumohci.h" /* Plum2 OHCI shared memory allocated on V-RAM */ 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 47 #include <sys/ioctl.h> 48 #include <sys/buf.h> 49 #include <uvm/uvm_extern.h> 50 51 #include <dev/cons.h> /* consdev */ 52 53 #include <mips/cache.h> 54 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 #include <machine/config_hook.h> 58 59 #include <hpcmips/tx/tx39var.h> 60 #include <hpcmips/dev/plumvar.h> 61 #include <hpcmips/dev/plumicuvar.h> 62 #include <hpcmips/dev/plumpowervar.h> 63 #include <hpcmips/dev/plumvideoreg.h> 64 65 #include <machine/bootinfo.h> 66 67 #include <dev/wscons/wsdisplayvar.h> 68 #include <dev/rasops/rasops.h> 69 #include <dev/hpc/video_subr.h> 70 71 #include <dev/wscons/wsconsio.h> 72 #include <dev/hpc/hpcfbvar.h> 73 #include <dev/hpc/hpcfbio.h> 74 75 #ifdef PLUMVIDEODEBUG 76 int plumvideo_debug = 1; 77 #define DPRINTF(arg) if (plumvideo_debug) printf arg; 78 #define DPRINTFN(n, arg) if (plumvideo_debug > (n)) printf arg; 79 #else 80 #define DPRINTF(arg) 81 #define DPRINTFN(n, arg) 82 #endif 83 84 struct plumvideo_softc { 85 struct device sc_dev; 86 tx_chipset_tag_t sc_tc; 87 plum_chipset_tag_t sc_pc; 88 89 void *sc_powerhook; /* power management hook */ 90 int sc_console; 91 92 /* control register */ 93 bus_space_tag_t sc_regt; 94 bus_space_handle_t sc_regh; 95 /* frame buffer */ 96 bus_space_tag_t sc_fbiot; 97 bus_space_handle_t sc_fbioh; 98 /* clut buffer (8bpp only) */ 99 bus_space_tag_t sc_clutiot; 100 bus_space_handle_t sc_clutioh; 101 /* bitblt */ 102 bus_space_tag_t sc_bitbltt; 103 bus_space_handle_t sc_bitblth; 104 105 struct video_chip sc_chip; 106 struct hpcfb_fbconf sc_fbconf; 107 struct hpcfb_dspconf sc_dspconf; 108 }; 109 110 int plumvideo_match(struct device*, struct cfdata*, void*); 111 void plumvideo_attach(struct device*, struct device*, void*); 112 113 int plumvideo_ioctl(void *, u_long, caddr_t, int, struct proc *); 114 paddr_t plumvideo_mmap(void *, off_t, int); 115 116 struct cfattach plumvideo_ca = { 117 sizeof(struct plumvideo_softc), plumvideo_match, plumvideo_attach 118 }; 119 120 struct hpcfb_accessops plumvideo_ha = { 121 plumvideo_ioctl, plumvideo_mmap 122 }; 123 124 int plumvideo_power(void *, int, long, void *); 125 126 int plumvideo_init(struct plumvideo_softc *, int *); 127 void plumvideo_hpcfbinit(struct plumvideo_softc *, int); 128 129 void plumvideo_clut_default(struct plumvideo_softc *); 130 void plumvideo_clut_set(struct plumvideo_softc *, u_int32_t *, int, int); 131 void plumvideo_clut_get(struct plumvideo_softc *, u_int32_t *, int, int); 132 void __plumvideo_clut_access(struct plumvideo_softc *, 133 void (*)(bus_space_tag_t, bus_space_handle_t)); 134 static void _flush_cache(void) __attribute__((__unused__)); /* !!! */ 135 136 #ifdef PLUMVIDEODEBUG 137 void plumvideo_dump(struct plumvideo_softc*); 138 #endif 139 140 #define ON 1 141 #define OFF 0 142 143 int 144 plumvideo_match(struct device *parent, struct cfdata *cf, void *aux) 145 { 146 /* 147 * VRAM area also uses as UHOSTC shared RAM. 148 */ 149 return (2); /* 1st attach group */ 150 } 151 152 void 153 plumvideo_attach(struct device *parent, struct device *self, void *aux) 154 { 155 struct plum_attach_args *pa = aux; 156 struct plumvideo_softc *sc = (void*)self; 157 struct hpcfb_attach_args ha; 158 int console, reverse_flag; 159 160 sc->sc_console = console = cn_tab ? 0 : 1; 161 sc->sc_pc = pa->pa_pc; 162 sc->sc_regt = pa->pa_regt; 163 sc->sc_fbiot = sc->sc_clutiot = sc->sc_bitbltt = pa->pa_iot; 164 165 printf(": "); 166 167 /* map register area */ 168 if (bus_space_map(sc->sc_regt, PLUM_VIDEO_REGBASE, 169 PLUM_VIDEO_REGSIZE, 0, &sc->sc_regh)) { 170 printf("register map failed\n"); 171 return; 172 } 173 174 /* power control */ 175 plumvideo_power(sc, 0, 0, 176 (void *)(console ? PWR_RESUME : PWR_SUSPEND)); 177 /* Add a hard power hook to power saving */ 178 sc->sc_powerhook = config_hook(CONFIG_HOOK_PMEVENT, 179 CONFIG_HOOK_PMEVENT_HARDPOWER, 180 CONFIG_HOOK_SHARE, 181 plumvideo_power, sc); 182 if (sc->sc_powerhook == 0) 183 printf("WARNING unable to establish hard power hook"); 184 185 /* 186 * Initialize LCD controller 187 * map V-RAM area. 188 * reinstall bootinfo structure. 189 * some OHCI shared-buffer hack. XXX 190 */ 191 if (plumvideo_init(sc, &reverse_flag) != 0) 192 return; 193 194 printf("\n"); 195 196 /* Attach frame buffer device */ 197 plumvideo_hpcfbinit(sc, reverse_flag); 198 199 #ifdef PLUMVIDEODEBUG 200 if (plumvideo_debug > 0) 201 plumvideo_dump(sc); 202 /* attach debug draw routine (debugging use) */ 203 video_attach_drawfunc(&sc->sc_chip); 204 tx_conf_register_video(sc->sc_pc->pc_tc, &sc->sc_chip); 205 #endif /* PLUMVIDEODEBUG */ 206 207 if(console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 208 panic("plumvideo_attach: can't init fb console"); 209 } 210 211 ha.ha_console = console; 212 ha.ha_accessops = &plumvideo_ha; 213 ha.ha_accessctx = sc; 214 ha.ha_curfbconf = 0; 215 ha.ha_nfbconf = 1; 216 ha.ha_fbconflist = &sc->sc_fbconf; 217 ha.ha_curdspconf = 0; 218 ha.ha_ndspconf = 1; 219 ha.ha_dspconflist = &sc->sc_dspconf; 220 221 config_found(self, &ha, hpcfbprint); 222 } 223 224 void 225 plumvideo_hpcfbinit(struct plumvideo_softc *sc, int reverse_flag) 226 { 227 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 228 struct video_chip *chip = &sc->sc_chip; 229 vaddr_t fbvaddr = (vaddr_t)sc->sc_fbioh; 230 int height = chip->vc_fbheight; 231 int width = chip->vc_fbwidth; 232 int depth = chip->vc_fbdepth; 233 234 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 235 236 fb->hf_conf_index = 0; /* configuration index */ 237 fb->hf_nconfs = 1; /* how many configurations */ 238 strncpy(fb->hf_name, "PLUM built-in video", HPCFB_MAXNAMELEN); 239 /* frame buffer name */ 240 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 241 /* configuration name */ 242 fb->hf_height = height; 243 fb->hf_width = width; 244 fb->hf_baseaddr = (u_long)fbvaddr; 245 fb->hf_offset = (u_long)fbvaddr - mips_ptob(mips_btop(fbvaddr)); 246 /* frame buffer start offset */ 247 fb->hf_bytes_per_line = (width * depth) / NBBY; 248 fb->hf_nplanes = 1; 249 fb->hf_bytes_per_plane = height * fb->hf_bytes_per_line; 250 251 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 252 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 253 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 254 if (reverse_flag) 255 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 256 257 switch (depth) { 258 default: 259 panic("plumvideo_hpcfbinit: not supported color depth\n"); 260 /* NOTREACHED */ 261 case 16: 262 fb->hf_class = HPCFB_CLASS_RGBCOLOR; 263 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 264 fb->hf_order_flags = HPCFB_REVORDER_BYTE; 265 fb->hf_pack_width = 16; 266 fb->hf_pixels_per_pack = 1; 267 fb->hf_pixel_width = 16; 268 269 fb->hf_class_data_length = sizeof(struct hf_rgb_tag); 270 /* reserved for future use */ 271 fb->hf_u.hf_rgb.hf_flags = 0; 272 273 fb->hf_u.hf_rgb.hf_red_width = 5; 274 fb->hf_u.hf_rgb.hf_red_shift = 11; 275 fb->hf_u.hf_rgb.hf_green_width = 6; 276 fb->hf_u.hf_rgb.hf_green_shift = 5; 277 fb->hf_u.hf_rgb.hf_blue_width = 5; 278 fb->hf_u.hf_rgb.hf_blue_shift = 0; 279 fb->hf_u.hf_rgb.hf_alpha_width = 0; 280 fb->hf_u.hf_rgb.hf_alpha_shift = 0; 281 break; 282 283 case 8: 284 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 285 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 286 fb->hf_pack_width = 8; 287 fb->hf_pixels_per_pack = 1; 288 fb->hf_pixel_width = 8; 289 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 290 /* reserved for future use */ 291 fb->hf_u.hf_indexed.hf_flags = 0; 292 break; 293 } 294 } 295 296 int 297 plumvideo_init(struct plumvideo_softc *sc, int *reverse) 298 { 299 struct video_chip *chip = &sc->sc_chip; 300 bus_space_tag_t regt = sc->sc_regt; 301 bus_space_handle_t regh = sc->sc_regh; 302 plumreg_t reg; 303 size_t vram_size; 304 int bpp, width, height, vram_pitch; 305 306 *reverse = video_reverse_color(); 307 chip->vc_v = sc->sc_pc->pc_tc; 308 #if notyet 309 /* map BitBlt area */ 310 if (bus_space_map(sc->sc_bitbltt, 311 PLUM_VIDEO_BITBLT_IOBASE, 312 PLUM_VIDEO_BITBLT_IOSIZE, 0, 313 &sc->sc_bitblth)) { 314 printf(": BitBlt map failed\n"); 315 return (1); 316 } 317 #endif 318 reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG); 319 320 switch (reg & PLUM_VIDEO_PLGMD_GMODE_MASK) { 321 case PLUM_VIDEO_PLGMD_16BPP: 322 #if NPLUMOHCI > 0 /* reserve V-RAM area for USB OHCI */ 323 /* FALLTHROUGH */ 324 #else 325 bpp = 16; 326 break; 327 #endif 328 default: 329 bootinfo->fb_type = *reverse ? BIFB_D8_FF : BIFB_D8_00; 330 reg &= ~PLUM_VIDEO_PLGMD_GMODE_MASK; 331 plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg); 332 reg |= PLUM_VIDEO_PLGMD_8BPP; 333 plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg); 334 #if notyet 335 /* change BitBlt color depth */ 336 plum_conf_write(sc->sc_bitbltt, sc->sc_bitblth, 0x8, 0); 337 #endif 338 /* FALLTHROUGH */ 339 case PLUM_VIDEO_PLGMD_8BPP: 340 bpp = 8; 341 break; 342 } 343 chip->vc_fbdepth = bpp; 344 345 /* 346 * Get display size from WindowsCE setted. 347 */ 348 chip->vc_fbwidth = width = bootinfo->fb_width = 349 plum_conf_read(regt, regh, PLUM_VIDEO_PLHPX_REG) + 1; 350 chip->vc_fbheight = height = bootinfo->fb_height = 351 plum_conf_read(regt, regh, PLUM_VIDEO_PLVT_REG) - 352 plum_conf_read(regt, regh, PLUM_VIDEO_PLVDS_REG); 353 354 /* 355 * set line byte length to bootinfo and LCD controller. 356 */ 357 vram_pitch = bootinfo->fb_line_bytes = (width * bpp) / NBBY; 358 plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT1_REG, vram_pitch); 359 plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT2_REG, 360 vram_pitch & PLUM_VIDEO_PLPIT2_MASK); 361 plum_conf_write(regt, regh, PLUM_VIDEO_PLOFS_REG, vram_pitch); 362 363 /* 364 * boot messages and map CLUT(if any). 365 */ 366 printf("display mode: "); 367 switch (bpp) { 368 default: 369 printf("disabled "); 370 break; 371 case 8: 372 printf("8bpp "); 373 /* map CLUT area */ 374 if (bus_space_map(sc->sc_clutiot, 375 PLUM_VIDEO_CLUT_LCD_IOBASE, 376 PLUM_VIDEO_CLUT_LCD_IOSIZE, 0, 377 &sc->sc_clutioh)) { 378 printf(": CLUT map failed\n"); 379 return (1); 380 } 381 /* install default CLUT */ 382 plumvideo_clut_default(sc); 383 break; 384 case 16: 385 printf("16bpp "); 386 break; 387 } 388 389 /* 390 * calcurate frame buffer size. 391 */ 392 reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG); 393 vram_size = (width * height * bpp) / NBBY; 394 vram_size = mips_round_page(vram_size); 395 chip->vc_fbsize = vram_size; 396 397 /* 398 * map V-RAM area. 399 */ 400 if (bus_space_map(sc->sc_fbiot, PLUM_VIDEO_VRAM_IOBASE, 401 vram_size, 0, &sc->sc_fbioh)) { 402 printf(": V-RAM map failed\n"); 403 return (1); 404 } 405 406 bootinfo->fb_addr = (unsigned char *)sc->sc_fbioh; 407 chip->vc_fbvaddr = (vaddr_t)sc->sc_fbioh; 408 chip->vc_fbpaddr = PLUM_VIDEO_VRAM_IOBASE_PHYSICAL; 409 410 return (0); 411 } 412 413 int 414 plumvideo_ioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 415 { 416 struct plumvideo_softc *sc = (struct plumvideo_softc *)v; 417 struct hpcfb_fbconf *fbconf; 418 struct hpcfb_dspconf *dspconf; 419 struct wsdisplay_cmap *cmap; 420 u_int8_t *r, *g, *b; 421 u_int32_t *rgb; 422 int idx, error; 423 size_t cnt; 424 425 switch (cmd) { 426 case WSDISPLAYIO_GETCMAP: 427 cmap = (struct wsdisplay_cmap*)data; 428 cnt = cmap->count; 429 idx = cmap->index; 430 431 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 432 sc->sc_fbconf.hf_pack_width != 8 || 433 !LEGAL_CLUT_INDEX(idx) || 434 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 435 return (EINVAL); 436 } 437 438 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 439 !uvm_useracc(cmap->green, cnt, B_WRITE) || 440 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 441 return (EFAULT); 442 } 443 444 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 445 if (error != 0) { 446 cmap_work_free(r, g, b, rgb); 447 return (ENOMEM); 448 } 449 plumvideo_clut_get(sc, rgb, idx, cnt); 450 rgb24_decompose(rgb, r, g, b, cnt); 451 452 copyout(r, cmap->red, cnt); 453 copyout(g, cmap->green,cnt); 454 copyout(b, cmap->blue, cnt); 455 456 cmap_work_free(r, g, b, rgb); 457 458 return (0); 459 460 case WSDISPLAYIO_PUTCMAP: 461 cmap = (struct wsdisplay_cmap*)data; 462 cnt = cmap->count; 463 idx = cmap->index; 464 465 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 466 sc->sc_fbconf.hf_pack_width != 8 || 467 !LEGAL_CLUT_INDEX(idx) || 468 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 469 return (EINVAL); 470 } 471 472 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 473 !uvm_useracc(cmap->green, cnt, B_WRITE) || 474 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 475 return (EFAULT); 476 } 477 478 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 479 if (error != 0) { 480 cmap_work_free(r, g, b, rgb); 481 return (ENOMEM); 482 } 483 copyin(cmap->red, r, cnt); 484 copyin(cmap->green, g, cnt); 485 copyin(cmap->blue, b, cnt); 486 rgb24_compose(rgb, r, g, b, cnt); 487 plumvideo_clut_set(sc, rgb, idx, cnt); 488 489 cmap_work_free(r, g, b, rgb); 490 491 return (0); 492 493 case HPCFBIO_GCONF: 494 fbconf = (struct hpcfb_fbconf *)data; 495 if (fbconf->hf_conf_index != 0 && 496 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 497 return (EINVAL); 498 } 499 *fbconf = sc->sc_fbconf; /* structure assignment */ 500 return (0); 501 502 case HPCFBIO_SCONF: 503 fbconf = (struct hpcfb_fbconf *)data; 504 if (fbconf->hf_conf_index != 0 && 505 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 506 return (EINVAL); 507 } 508 /* 509 * nothing to do because we have only one configration 510 */ 511 return (0); 512 513 case HPCFBIO_GDSPCONF: 514 dspconf = (struct hpcfb_dspconf *)data; 515 if ((dspconf->hd_unit_index != 0 && 516 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 517 (dspconf->hd_conf_index != 0 && 518 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 519 return (EINVAL); 520 } 521 *dspconf = sc->sc_dspconf; /* structure assignment */ 522 return (0); 523 524 case HPCFBIO_SDSPCONF: 525 dspconf = (struct hpcfb_dspconf *)data; 526 if ((dspconf->hd_unit_index != 0 && 527 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 528 (dspconf->hd_conf_index != 0 && 529 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 530 return (EINVAL); 531 } 532 /* 533 * nothing to do 534 * because we have only one unit and one configration 535 */ 536 return (0); 537 538 case HPCFBIO_GOP: 539 case HPCFBIO_SOP: 540 /* XXX not implemented yet */ 541 return (EINVAL); 542 } 543 544 return (ENOTTY); 545 } 546 547 paddr_t 548 plumvideo_mmap(void *ctx, off_t offset, int prot) 549 { 550 struct plumvideo_softc *sc = (struct plumvideo_softc *)ctx; 551 552 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 553 sc->sc_fbconf.hf_offset) < offset) { 554 return (-1); 555 } 556 557 return (mips_btop(PLUM_VIDEO_VRAM_IOBASE_PHYSICAL + offset)); 558 } 559 560 void 561 plumvideo_clut_get(struct plumvideo_softc *sc, u_int32_t *rgb, int beg, 562 int cnt) 563 { 564 static void __plumvideo_clut_get(bus_space_tag_t, 565 bus_space_handle_t); 566 static void __plumvideo_clut_get(iot, ioh) 567 bus_space_tag_t iot; 568 bus_space_handle_t ioh; 569 { 570 int i; 571 572 for (i = 0, beg *= 4; i < cnt; i++, beg += 4) { 573 *rgb++ = bus_space_read_4(iot, ioh, beg) & 574 0x00ffffff; 575 } 576 } 577 578 KASSERT(rgb); 579 KASSERT(LEGAL_CLUT_INDEX(beg)); 580 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 581 __plumvideo_clut_access(sc, __plumvideo_clut_get); 582 } 583 584 void 585 plumvideo_clut_set(struct plumvideo_softc *sc, u_int32_t *rgb, int beg, 586 int cnt) 587 { 588 static void __plumvideo_clut_set(bus_space_tag_t, 589 bus_space_handle_t); 590 static void __plumvideo_clut_set(iot, ioh) 591 bus_space_tag_t iot; 592 bus_space_handle_t ioh; 593 { 594 int i; 595 596 for (i = 0, beg *= 4; i < cnt; i++, beg +=4) { 597 bus_space_write_4(iot, ioh, beg, 598 *rgb++ & 0x00ffffff); 599 } 600 } 601 602 KASSERT(rgb); 603 KASSERT(LEGAL_CLUT_INDEX(beg)); 604 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 605 __plumvideo_clut_access(sc, __plumvideo_clut_set); 606 } 607 608 void 609 plumvideo_clut_default(struct plumvideo_softc *sc) 610 { 611 static void __plumvideo_clut_default(bus_space_tag_t, 612 bus_space_handle_t); 613 static void __plumvideo_clut_default(iot, ioh) 614 bus_space_tag_t iot; 615 bus_space_handle_t ioh; 616 { 617 const u_int8_t compo6[6] = { 0, 51, 102, 153, 204, 255 }; 618 const u_int32_t ansi_color[16] = { 619 0x000000, 0xff0000, 0x00ff00, 0xffff00, 620 0x0000ff, 0xff00ff, 0x00ffff, 0xffffff, 621 0x000000, 0x800000, 0x008000, 0x808000, 622 0x000080, 0x800080, 0x008080, 0x808080, 623 }; 624 int i, r, g, b; 625 626 /* ANSI escape sequence */ 627 for (i = 0; i < 16; i++) { 628 bus_space_write_4(iot, ioh, i << 2, ansi_color[i]); 629 } 630 /* 16 - 31, gray scale */ 631 for ( ; i < 32; i++) { 632 int j = (i - 16) * 17; 633 bus_space_write_4(iot, ioh, i << 2, RGB24(j, j, j)); 634 } 635 /* 32 - 247, RGB color */ 636 for (r = 0; r < 6; r++) { 637 for (g = 0; g < 6; g++) { 638 for (b = 0; b < 6; b++) { 639 bus_space_write_4(iot, ioh, i << 2, 640 RGB24(compo6[r], 641 compo6[g], 642 compo6[b])); 643 i++; 644 } 645 } 646 } 647 /* 248 - 245, just white */ 648 for ( ; i < 256; i++) { 649 bus_space_write_4(iot, ioh, i << 2, 0xffffff); 650 } 651 } 652 653 __plumvideo_clut_access(sc, __plumvideo_clut_default); 654 } 655 656 void 657 __plumvideo_clut_access(struct plumvideo_softc *sc, void (*palette_func) 658 (bus_space_tag_t, bus_space_handle_t)) 659 { 660 bus_space_tag_t regt = sc->sc_regt; 661 bus_space_handle_t regh = sc->sc_regh; 662 plumreg_t val, gmode; 663 664 /* display off */ 665 val = bus_space_read_4(regt, regh, PLUM_VIDEO_PLGMD_REG); 666 gmode = val & PLUM_VIDEO_PLGMD_GMODE_MASK; 667 val &= ~PLUM_VIDEO_PLGMD_GMODE_MASK; 668 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 669 670 /* palette access disable */ 671 val &= ~PLUM_VIDEO_PLGMD_PALETTE_ENABLE; 672 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 673 674 /* change palette mode to CPU */ 675 val &= ~PLUM_VIDEO_PLGMD_MODE_DISPLAY; 676 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 677 678 /* palette access */ 679 (*palette_func) (sc->sc_clutiot, sc->sc_clutioh); 680 681 /* change palette mode to Display */ 682 val |= PLUM_VIDEO_PLGMD_MODE_DISPLAY; 683 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 684 685 /* palette access enable */ 686 val |= PLUM_VIDEO_PLGMD_PALETTE_ENABLE; 687 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 688 689 /* display on */ 690 val |= gmode; 691 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 692 } 693 694 /* !!! */ 695 static void 696 _flush_cache() 697 { 698 mips_dcache_wbinv_all(); 699 mips_icache_sync_all(); 700 } 701 702 int 703 plumvideo_power(void *ctx, int type, long id, void *msg) 704 { 705 struct plumvideo_softc *sc = ctx; 706 plum_chipset_tag_t pc = sc->sc_pc; 707 bus_space_tag_t regt = sc->sc_regt; 708 bus_space_handle_t regh = sc->sc_regh; 709 int why = (int)msg; 710 711 switch (why) { 712 case PWR_RESUME: 713 if (!sc->sc_console) 714 return (0); /* serial console */ 715 716 DPRINTF(("%s: ON\n", sc->sc_dev.dv_xname)); 717 /* power on */ 718 /* LCD power on and display on */ 719 plum_power_establish(pc, PLUM_PWR_LCD); 720 /* back-light on */ 721 plum_power_establish(pc, PLUM_PWR_BKL); 722 plum_conf_write(regt, regh, PLUM_VIDEO_PLLUM_REG, 723 PLUM_VIDEO_PLLUM_MAX); 724 break; 725 case PWR_SUSPEND: 726 /* FALLTHROUGH */ 727 case PWR_STANDBY: 728 DPRINTF(("%s: OFF\n", sc->sc_dev.dv_xname)); 729 /* back-light off */ 730 plum_conf_write(regt, regh, PLUM_VIDEO_PLLUM_REG, 731 PLUM_VIDEO_PLLUM_MIN); 732 plum_power_disestablish(pc, PLUM_PWR_BKL); 733 /* power down */ 734 plum_power_disestablish(pc, PLUM_PWR_LCD); 735 break; 736 } 737 738 return (0); 739 } 740 741 #ifdef PLUMVIDEODEBUG 742 void 743 plumvideo_dump(struct plumvideo_softc *sc) 744 { 745 bus_space_tag_t regt = sc->sc_regt; 746 bus_space_handle_t regh = sc->sc_regh; 747 748 plumreg_t reg; 749 int i; 750 751 for (i = 0; i < 0x160; i += 4) { 752 reg = plum_conf_read(regt, regh, i); 753 printf("0x%03x %08x", i, reg); 754 bitdisp(reg); 755 } 756 } 757 #endif /* PLUMVIDEODEBUG */ 758
Indexes created Sun Oct 19 16:10:00 GMT 2025