plumvideo.c revision 1.8
1 /* $NetBSD: plumvideo.c,v 1.8 2000/05/08 21:57:56 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_tx39_debug.h" 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 35 #include <sys/ioctl.h> 36 #include <sys/buf.h> 37 #include <vm/vm.h> 38 39 #include <dev/cons.h> /* consdev */ 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #include <hpcmips/tx/tx39var.h> 45 #include <hpcmips/dev/plumvar.h> 46 #include <hpcmips/dev/plumicuvar.h> 47 #include <hpcmips/dev/plumpowervar.h> 48 #include <hpcmips/dev/plumvideoreg.h> 49 50 #include <machine/bootinfo.h> 51 52 #include <dev/wscons/wsdisplayvar.h> 53 #include <dev/rasops/rasops.h> 54 #include <arch/hpcmips/dev/video_subr.h> 55 56 #include <dev/wscons/wsconsio.h> 57 #include <arch/hpcmips/dev/hpcfbvar.h> 58 #include <arch/hpcmips/dev/hpcfbio.h> 59 60 61 #ifdef PLUMVIDEODEBUG 62 int plumvideo_debug = 1; 63 #define DPRINTF(arg) if (plumvideo_debug) printf arg; 64 #define DPRINTFN(n, arg) if (plumvideo_debug > (n)) printf arg; 65 #else 66 #define DPRINTF(arg) 67 #define DPRINTFN(n, arg) 68 #endif 69 70 struct plumvideo_softc { 71 struct device sc_dev; 72 73 plum_chipset_tag_t sc_pc; 74 /* control register */ 75 bus_space_tag_t sc_regt; 76 bus_space_handle_t sc_regh; 77 /* frame buffer */ 78 bus_space_tag_t sc_fbiot; 79 bus_space_handle_t sc_fbioh; 80 /* clut buffer (8bpp only) */ 81 bus_space_tag_t sc_clutiot; 82 bus_space_handle_t sc_clutioh; 83 /* bitblt */ 84 bus_space_tag_t sc_bitbltt; 85 bus_space_handle_t sc_bitblth; 86 87 int sc_width; 88 int sc_height; 89 int sc_depth; 90 91 struct hpcfb_fbconf sc_fbconf; 92 struct hpcfb_dspconf sc_dspconf; 93 }; 94 95 int plumvideo_match __P((struct device*, struct cfdata*, void*)); 96 void plumvideo_attach __P((struct device*, struct device*, void*)); 97 98 int plumvideo_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 99 int plumvideo_mmap __P((void *, off_t, int)); 100 101 struct cfattach plumvideo_ca = { 102 sizeof(struct plumvideo_softc), plumvideo_match, plumvideo_attach 103 }; 104 105 struct hpcfb_accessops plumvideo_ha = { 106 plumvideo_ioctl, plumvideo_mmap 107 }; 108 109 int plumvideo_init __P((struct plumvideo_softc*)); 110 void plumvideo_hpcfbinit __P((struct plumvideo_softc *)); 111 112 void plumvideo_clut_default __P((struct plumvideo_softc *)); 113 void plumvideo_clut_set __P((struct plumvideo_softc *, u_int32_t *, int, 114 int)); 115 void plumvideo_clut_get __P((struct plumvideo_softc *, u_int32_t *, int, 116 int)); 117 void __plumvideo_clut_access __P((struct plumvideo_softc *, 118 void (*) __P((bus_space_tag_t, 119 bus_space_handle_t)))); 120 static void _flush_cache __P((void)) __attribute__((__unused__)); /* !!! */ 121 122 #ifdef PLUMVIDEODEBUG 123 void plumvideo_dump __P((struct plumvideo_softc*)); 124 #endif 125 126 int 127 plumvideo_match(parent, cf, aux) 128 struct device *parent; 129 struct cfdata *cf; 130 void *aux; 131 { 132 /* 133 * VRAM area also uses as UHOSTC shared RAM. 134 */ 135 return (2); /* 1st attach group */ 136 } 137 138 void 139 plumvideo_attach(parent, self, aux) 140 struct device *parent; 141 struct device *self; 142 void *aux; 143 { 144 struct plum_attach_args *pa = aux; 145 struct plumvideo_softc *sc = (void*)self; 146 struct hpcfb_attach_args ha; 147 int console; 148 149 sc->sc_pc = pa->pa_pc; 150 sc->sc_regt = pa->pa_regt; 151 sc->sc_fbiot = sc->sc_clutiot = sc->sc_bitbltt = pa->pa_iot; 152 153 printf(": "); 154 /* 155 * map register area 156 */ 157 if (bus_space_map(sc->sc_regt, PLUM_VIDEO_REGBASE, 158 PLUM_VIDEO_REGSIZE, 0, &sc->sc_regh)) { 159 printf(": register map failed\n"); 160 return; 161 } 162 163 /* 164 * Power control 165 */ 166 #ifndef PLUMVIDEODEBUG 167 if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) { 168 /* LCD power on and display off */ 169 plum_power_disestablish(sc->sc_pc, PLUM_PWR_LCD); 170 /* power off V-RAM */ 171 plum_power_disestablish(sc->sc_pc, PLUM_PWR_EXTPW2); 172 /* power off LCD */ 173 plum_power_disestablish(sc->sc_pc, PLUM_PWR_EXTPW1); 174 /* power off RAMDAC */ 175 plum_power_disestablish(sc->sc_pc, PLUM_PWR_EXTPW0); 176 /* back-light off */ 177 plum_power_disestablish(sc->sc_pc, PLUM_PWR_BKL); 178 } else 179 #endif 180 { 181 /* LCD power on and display on */ 182 plum_power_establish(sc->sc_pc, PLUM_PWR_LCD); 183 /* supply power to V-RAM */ 184 plum_power_establish(sc->sc_pc, PLUM_PWR_EXTPW2); 185 /* supply power to LCD */ 186 plum_power_establish(sc->sc_pc, PLUM_PWR_EXTPW1); 187 /* back-light on */ 188 plum_power_establish(sc->sc_pc, PLUM_PWR_BKL); 189 } 190 191 /* 192 * Initialize LCD controller 193 * map V-RAM area. 194 * reinstall bootinfo structure. 195 * some OHCI shared-buffer hack. XXX 196 */ 197 if (plumvideo_init(sc) != 0) 198 return; 199 200 printf("\n"); 201 202 #ifdef PLUMVIDEODEBUG 203 if (plumvideo_debug) 204 plumvideo_dump(sc); 205 #endif 206 /* Attach frame buffer device */ 207 plumvideo_hpcfbinit(sc); 208 209 console = cn_tab ? 0 : 1; 210 if(console && hpcfb_cnattach(&sc->sc_fbconf) != 0) { 211 panic("plumvideo_attach: can't init fb console"); 212 } 213 214 ha.ha_console = console; 215 ha.ha_accessops = &plumvideo_ha; 216 ha.ha_accessctx = sc; 217 ha.ha_curfbconf = 0; 218 ha.ha_nfbconf = 1; 219 ha.ha_fbconflist = &sc->sc_fbconf; 220 ha.ha_curdspconf = 0; 221 ha.ha_ndspconf = 1; 222 ha.ha_dspconflist = &sc->sc_dspconf; 223 224 config_found(self, &ha, hpcfbprint); 225 } 226 227 void 228 plumvideo_hpcfbinit(sc) 229 struct plumvideo_softc *sc; 230 { 231 struct hpcfb_fbconf *fb = &sc->sc_fbconf; 232 vaddr_t fbvaddr = (vaddr_t)sc->sc_fbioh; 233 234 memset(fb, 0, sizeof(struct hpcfb_fbconf)); 235 236 fb->hf_conf_index = 0; /* configuration index */ 237 fb->hf_nconfs = 1; /* how many configurations */ 238 strncpy(fb->hf_name, "PLUM built-in video", HPCFB_MAXNAMELEN); 239 /* frame buffer name */ 240 strncpy(fb->hf_conf_name, "LCD", HPCFB_MAXNAMELEN); 241 /* configuration name */ 242 fb->hf_height = sc->sc_height; 243 fb->hf_width = sc->sc_width; 244 fb->hf_baseaddr = mips_ptob(mips_btop(fbvaddr)); 245 fb->hf_offset = (u_long)fbvaddr - fb->hf_baseaddr; 246 /* frame buffer start offset */ 247 fb->hf_bytes_per_line = (sc->sc_width * sc->sc_depth) / NBBY; 248 fb->hf_nplanes = 1; 249 fb->hf_bytes_per_plane = sc->sc_height * fb->hf_bytes_per_line; 250 251 fb->hf_access_flags |= HPCFB_ACCESS_BYTE; 252 fb->hf_access_flags |= HPCFB_ACCESS_WORD; 253 fb->hf_access_flags |= HPCFB_ACCESS_DWORD; 254 255 fb->hf_access_flags |= HPCFB_ACCESS_REVERSE; 256 switch (sc->sc_depth) { 257 default: 258 panic("plumvideo_hpcfbinit: not supported color depth\n"); 259 /* NOTREACHED */ 260 case 16: 261 fb->hf_class = HPCFB_CLASS_RGBCOLOR; 262 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 263 fb->hf_pack_width = 16; 264 fb->hf_pixels_per_pack = 1; 265 fb->hf_pixel_width = 16; 266 267 fb->hf_class_data_length = sizeof(struct hf_rgb_tag); 268 /* reserved for future use */ 269 fb->hf_u.hf_rgb.hf_flags = 0; 270 271 fb->hf_u.hf_rgb.hf_red_width = 5; 272 fb->hf_u.hf_rgb.hf_red_shift = 11; 273 fb->hf_u.hf_rgb.hf_green_width = 6; 274 fb->hf_u.hf_rgb.hf_green_shift = 5; 275 fb->hf_u.hf_rgb.hf_blue_width = 5; 276 fb->hf_u.hf_rgb.hf_blue_shift = 0; 277 fb->hf_u.hf_rgb.hf_alpha_width = 0; 278 fb->hf_u.hf_rgb.hf_alpha_shift = 0; 279 break; 280 281 case 8: 282 fb->hf_class = HPCFB_CLASS_INDEXCOLOR; 283 fb->hf_access_flags |= HPCFB_ACCESS_STATIC; 284 fb->hf_pack_width = 8; 285 fb->hf_pixels_per_pack = 1; 286 fb->hf_pixel_width = 8; 287 fb->hf_class_data_length = sizeof(struct hf_indexed_tag); 288 /* reserved for future use */ 289 fb->hf_u.hf_indexed.hf_flags = 0; 290 break; 291 } 292 } 293 294 int 295 plumvideo_init(sc) 296 struct plumvideo_softc *sc; 297 { 298 bus_space_tag_t regt = sc->sc_regt; 299 bus_space_handle_t regh = sc->sc_regh; 300 plumreg_t reg; 301 size_t vram_size; 302 int bpp, vram_pitch; 303 #if notyet 304 /* map BitBlt area */ 305 if (bus_space_map(sc->sc_bitbltt, 306 PLUM_VIDEO_BITBLT_IOBASE, 307 PLUM_VIDEO_BITBLT_IOSIZE, 0, 308 &sc->sc_bitblth)) { 309 printf(": BitBlt map failed\n"); 310 return (1); 311 } 312 #endif 313 reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG); 314 switch (reg & PLUM_VIDEO_PLGMD_GMODE_MASK) { 315 case PLUM_VIDEO_PLGMD_16BPP: 316 #ifdef PLUM_BIG_OHCI_BUFFER 317 printf("(16bpp disabled) "); 318 /* FALLTHROUGH */ 319 #else /* PLUM_BIG_OHCI_BUFFER */ 320 bpp = 16; 321 break; 322 #endif /* PLUM_BIG_OHCI_BUFFER */ 323 default: 324 bootinfo->fb_type = BIFB_D8_FF; /* over ride */ 325 reg &= ~PLUM_VIDEO_PLGMD_GMODE_MASK; 326 plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg); 327 reg |= PLUM_VIDEO_PLGMD_8BPP; 328 plum_conf_write(regt, regh, PLUM_VIDEO_PLGMD_REG, reg); 329 #if notyet 330 /* change BitBlt color depth */ 331 plum_conf_write(sc->sc_bitbltt, sc->sc_bitblth, 0x8, 0); 332 #endif 333 /* FALLTHROUGH */ 334 case PLUM_VIDEO_PLGMD_8BPP: 335 bpp = 8; 336 break; 337 } 338 sc->sc_depth = bpp; 339 sc->sc_width = bootinfo->fb_width; 340 sc->sc_height = bootinfo->fb_height; 341 342 /* 343 * set line byte length to bootinfo and LCD controller. 344 */ 345 bootinfo->fb_line_bytes = (sc->sc_width * bpp) / NBBY; 346 347 vram_pitch = sc->sc_width / (8 / bpp); 348 plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT1_REG, vram_pitch); 349 plum_conf_write(regt, regh, PLUM_VIDEO_PLPIT2_REG, 350 vram_pitch & PLUM_VIDEO_PLPIT2_MASK); 351 plum_conf_write(regt, regh, PLUM_VIDEO_PLOFS_REG, vram_pitch); 352 353 /* 354 * boot messages and map CLUT(if any). 355 */ 356 printf("display mode: "); 357 switch (bpp) { 358 default: 359 printf("disabled "); 360 break; 361 case 8: 362 printf("8bpp "); 363 /* map CLUT area */ 364 if (bus_space_map(sc->sc_clutiot, 365 PLUM_VIDEO_CLUT_LCD_IOBASE, 366 PLUM_VIDEO_CLUT_LCD_IOSIZE, 0, 367 &sc->sc_clutioh)) { 368 printf(": CLUT map failed\n"); 369 return (1); 370 } 371 /* install default CLUT */ 372 plumvideo_clut_default(sc); 373 break; 374 case 16: 375 printf("16bpp "); 376 break; 377 } 378 379 /* 380 * calcurate frame buffer size. 381 */ 382 reg = plum_conf_read(regt, regh, PLUM_VIDEO_PLGMD_REG); 383 vram_size = (sc->sc_width * sc->sc_height * bpp) / NBBY; 384 vram_size = mips_round_page(vram_size); 385 386 /* 387 * map V-RAM area. 388 */ 389 if (bus_space_map(sc->sc_fbiot, PLUM_VIDEO_VRAM_IOBASE, 390 vram_size, 0, &sc->sc_fbioh)) { 391 printf(": V-RAM map failed\n"); 392 return (1); 393 } 394 395 bootinfo->fb_addr = (unsigned char *)sc->sc_fbioh; 396 397 return (0); 398 } 399 400 int 401 plumvideo_ioctl(v, cmd, data, flag, p) 402 void *v; 403 u_long cmd; 404 caddr_t data; 405 int flag; 406 struct proc *p; 407 { 408 struct plumvideo_softc *sc = (struct plumvideo_softc *)v; 409 struct hpcfb_fbconf *fbconf; 410 struct hpcfb_dspconf *dspconf; 411 struct wsdisplay_cmap *cmap; 412 u_int8_t *r, *g, *b; 413 u_int32_t *rgb; 414 int idx, cnt, error; 415 416 switch (cmd) { 417 case WSDISPLAYIO_GETCMAP: 418 cmap = (struct wsdisplay_cmap*)data; 419 cnt = cmap->count; 420 idx = cmap->index; 421 422 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 423 sc->sc_fbconf.hf_pack_width != 8 || 424 !LEGAL_CLUT_INDEX(idx) || 425 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 426 return (EINVAL); 427 } 428 429 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 430 !uvm_useracc(cmap->green, cnt, B_WRITE) || 431 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 432 return (EFAULT); 433 } 434 435 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 436 if (error != 0) { 437 cmap_work_free(r, g, b, rgb); 438 return (ENOMEM); 439 } 440 plumvideo_clut_get(sc, rgb, idx, cnt); 441 rgb24_decompose(rgb, r, g, b, cnt); 442 443 copyout(r, cmap->red, cnt); 444 copyout(g, cmap->green,cnt); 445 copyout(b, cmap->blue, cnt); 446 447 cmap_work_free(r, g, b, rgb); 448 449 return (0); 450 451 case WSDISPLAYIO_PUTCMAP: 452 cmap = (struct wsdisplay_cmap*)data; 453 cnt = cmap->count; 454 idx = cmap->index; 455 456 if (sc->sc_fbconf.hf_class != HPCFB_CLASS_INDEXCOLOR || 457 sc->sc_fbconf.hf_pack_width != 8 || 458 !LEGAL_CLUT_INDEX(idx) || 459 !LEGAL_CLUT_INDEX(idx + cnt -1)) { 460 return (EINVAL); 461 } 462 463 if (!uvm_useracc(cmap->red, cnt, B_WRITE) || 464 !uvm_useracc(cmap->green, cnt, B_WRITE) || 465 !uvm_useracc(cmap->blue, cnt, B_WRITE)) { 466 return (EFAULT); 467 } 468 469 error = cmap_work_alloc(&r, &g, &b, &rgb, cnt); 470 if (error != 0) { 471 cmap_work_free(r, g, b, rgb); 472 return (ENOMEM); 473 } 474 rgb24_compose(rgb, r, g, b, cnt); 475 plumvideo_clut_set(sc, rgb, idx, cnt); 476 477 cmap_work_free(r, g, b, rgb); 478 479 return (EINVAL); 480 481 case HPCFBIO_GCONF: 482 fbconf = (struct hpcfb_fbconf *)data; 483 if (fbconf->hf_conf_index != 0 && 484 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 485 return (EINVAL); 486 } 487 *fbconf = sc->sc_fbconf; /* structure assignment */ 488 return (0); 489 490 case HPCFBIO_SCONF: 491 fbconf = (struct hpcfb_fbconf *)data; 492 if (fbconf->hf_conf_index != 0 && 493 fbconf->hf_conf_index != HPCFB_CURRENT_CONFIG) { 494 return (EINVAL); 495 } 496 /* 497 * nothing to do because we have only one configration 498 */ 499 return (0); 500 501 case HPCFBIO_GDSPCONF: 502 dspconf = (struct hpcfb_dspconf *)data; 503 if ((dspconf->hd_unit_index != 0 && 504 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 505 (dspconf->hd_conf_index != 0 && 506 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 507 return (EINVAL); 508 } 509 *dspconf = sc->sc_dspconf; /* structure assignment */ 510 return (0); 511 512 case HPCFBIO_SDSPCONF: 513 dspconf = (struct hpcfb_dspconf *)data; 514 if ((dspconf->hd_unit_index != 0 && 515 dspconf->hd_unit_index != HPCFB_CURRENT_UNIT) || 516 (dspconf->hd_conf_index != 0 && 517 dspconf->hd_conf_index != HPCFB_CURRENT_CONFIG)) { 518 return (EINVAL); 519 } 520 /* 521 * nothing to do 522 * because we have only one unit and one configration 523 */ 524 return (0); 525 526 case HPCFBIO_GOP: 527 case HPCFBIO_SOP: 528 /* XXX not implemented yet */ 529 return (EINVAL); 530 } 531 532 return (ENOTTY); 533 } 534 535 int 536 plumvideo_mmap(ctx, offset, prot) 537 void *ctx; 538 off_t offset; 539 int prot; 540 { 541 struct plumvideo_softc *sc = (struct plumvideo_softc *)ctx; 542 543 if (offset < 0 || (sc->sc_fbconf.hf_bytes_per_plane + 544 sc->sc_fbconf.hf_offset) < offset) { 545 return (-1); 546 } 547 548 return (mips_btop(PLUM_VIDEO_VRAM_IOBASE_PHYSICAL + offset)); 549 } 550 551 void 552 plumvideo_clut_get(sc, rgb, beg, cnt) 553 struct plumvideo_softc *sc; 554 u_int32_t *rgb; 555 int beg, cnt; 556 { 557 static void __plumvideo_clut_get __P((bus_space_tag_t, 558 bus_space_handle_t)); 559 static void __plumvideo_clut_get(iot, ioh) 560 bus_space_tag_t iot; 561 bus_space_handle_t ioh; 562 { 563 int i; 564 565 for (i = 0, beg *= 4; i < cnt; i++, beg += 4) { 566 *rgb++ = bus_space_read_4(iot, ioh, beg) & 567 0x00ffffff; 568 } 569 } 570 571 KASSERT(rgb); 572 KASSERT(LEGAL_CLUT_INDEX(beg)); 573 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 574 __plumvideo_clut_access(sc, __plumvideo_clut_get); 575 } 576 577 void 578 plumvideo_clut_set(sc, rgb, beg, cnt) 579 struct plumvideo_softc *sc; 580 u_int32_t *rgb; 581 int beg, cnt; 582 { 583 static void __plumvideo_clut_set __P((bus_space_tag_t, 584 bus_space_handle_t)); 585 static void __plumvideo_clut_set(iot, ioh) 586 bus_space_tag_t iot; 587 bus_space_handle_t ioh; 588 { 589 int i; 590 591 for (i = 0, beg *= 4; i < cnt; i++, beg +=4) { 592 bus_space_write_4(iot, ioh, beg, 593 *rgb++ & 0x00ffffff); 594 } 595 } 596 597 KASSERT(rgb); 598 KASSERT(LEGAL_CLUT_INDEX(beg)); 599 KASSERT(LEGAL_CLUT_INDEX(beg + cnt - 1)); 600 __plumvideo_clut_access(sc, __plumvideo_clut_set); 601 } 602 603 void 604 plumvideo_clut_default(sc) 605 struct plumvideo_softc *sc; 606 { 607 static void __plumvideo_clut_default __P((bus_space_tag_t, 608 bus_space_handle_t)); 609 static void __plumvideo_clut_default(iot, ioh) 610 bus_space_tag_t iot; 611 bus_space_handle_t ioh; 612 { 613 const u_int8_t compo6[6] = { 0, 51, 102, 153, 204, 255 }; 614 const u_int32_t ansi_color[16] = { 615 0x000000, 0xff0000, 0x00ff00, 0xffff00, 616 0x0000ff, 0xff00ff, 0x00ffff, 0xffffff, 617 0x000000, 0x800000, 0x008000, 0x808000, 618 0x000080, 0x800080, 0x008080, 0x808080, 619 }; 620 int i, r, g, b; 621 622 /* ANSI escape sequence */ 623 for (i = 0; i < 16; i++) { 624 bus_space_write_4(iot, ioh, i << 2, ansi_color[i]); 625 } 626 /* 16 - 31, gray scale */ 627 for ( ; i < 32; i++) { 628 int j = (i - 16) * 17; 629 bus_space_write_4(iot, ioh, i << 2, RGB24(j, j, j)); 630 } 631 /* 32 - 247, RGB color */ 632 for (r = 0; r < 6; r++) { 633 for (g = 0; g < 6; g++) { 634 for (b = 0; b < 6; b++) { 635 bus_space_write_4(iot, ioh, i << 2, 636 RGB24(compo6[r], 637 compo6[g], 638 compo6[b])); 639 i++; 640 } 641 } 642 } 643 /* 248 - 245, just white */ 644 for ( ; i < 256; i++) { 645 bus_space_write_4(iot, ioh, i << 2, 0xffffff); 646 } 647 } 648 649 __plumvideo_clut_access(sc, __plumvideo_clut_default); 650 } 651 652 void 653 __plumvideo_clut_access(sc, palette_func) 654 struct plumvideo_softc *sc; 655 void (*palette_func) __P((bus_space_tag_t, bus_space_handle_t)); 656 { 657 bus_space_tag_t regt = sc->sc_regt; 658 bus_space_handle_t regh = sc->sc_regh; 659 plumreg_t val, gmode; 660 661 /* display off */ 662 val = bus_space_read_4(regt, regh, PLUM_VIDEO_PLGMD_REG); 663 gmode = val & PLUM_VIDEO_PLGMD_GMODE_MASK; 664 val &= ~PLUM_VIDEO_PLGMD_GMODE_MASK; 665 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 666 667 /* palette access disable */ 668 val &= ~PLUM_VIDEO_PLGMD_PALETTE_ENABLE; 669 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 670 671 /* change palette mode to CPU */ 672 val &= ~PLUM_VIDEO_PLGMD_MODE_DISPLAY; 673 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 674 675 /* palette access */ 676 (*palette_func) (sc->sc_clutiot, sc->sc_clutioh); 677 678 /* change palette mode to Display */ 679 val |= PLUM_VIDEO_PLGMD_MODE_DISPLAY; 680 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 681 /* palette access enable */ 682 val |= PLUM_VIDEO_PLGMD_PALETTE_ENABLE; 683 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 684 685 /* display on */ 686 val |= gmode; 687 bus_space_write_4(regt, regh, PLUM_VIDEO_PLGMD_REG, val); 688 } 689 690 /* !!! */ 691 static void 692 _flush_cache() 693 { 694 MachFlushCache(); 695 } 696 697 #ifdef PLUMVIDEODEBUG 698 void 699 plumvideo_dump(sc) 700 struct plumvideo_softc *sc; 701 { 702 bus_space_tag_t regt = sc->sc_regt; 703 bus_space_handle_t regh = sc->sc_regh; 704 705 plumreg_t reg; 706 int i; 707 708 for (i = 0; i < 0x160; i += 4) { 709 reg = plum_conf_read(regt, regh, i); 710 printf("0x%03x %08x", i, reg); 711 bitdisp(reg); 712 } 713 } 714 #endif /* PLUMVIDEODEBUG */ 715
Indexes created Sat Sep 27 14:09:57 GMT 2025