plumvideoreg.h revision 1.2
1 /* $NetBSD: plumvideoreg.h,v 1.2 2000/03/25 15:08:26 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 /* (CS3) */ 29 #define PLUM_VIDEO_REGBASE 0x1000 30 #define PLUM_VIDEO_REGSIZE 0x200 31 32 /* (MCS0) */ 33 /* VRAM 4MByte */ 34 #define PLUM_VIDEO_VRAM_IOBASE 0x00000000 35 #define PLUM_VIDEO_VRAM_IOSIZE 0x00400000 36 /* Color palette LCD 4KByte */ 37 #define PLUM_VIDEO_CLUT_LCD_IOBASE 0x00400000 38 #define PLUM_VIDEO_CLUT_LCD_IOSIZE 0x00001000 39 /* Color palette CRT 4KByte */ 40 #define PLUM_VIDEO_CLUT_CRT_IOBASE 0x00401000 41 #define PLUM_VIDEO_CLUT_CRT_IOSIZE 0x00001000 42 /* BitBlt 4KByte */ 43 #define PLUM_VIDEO_BITBLT_IOBASE 0x00402000 44 #define PLUM_VIDEO_BITBLT_IOSIZE 0x00401000 45 46 /* 47 * Common Control Register 48 */ 49 /* Interrupt Status enable and IRQ line enable */ 50 #define PLUM_VIDEO_POSENIEN_REG 0x000 51 /* Interrupt Status */ 52 #define PLUM_VIDEO_POIST_REG 0x004 53 /* Buffer Control */ 54 #define PLUM_VIDEO_POBFC_REG 0x008 55 /* VRAM Control */ 56 #define PLUM_VIDEO_PORAM_REG 0x00c 57 /* VRAM Refresh Control */ 58 #define PLUM_VIDEO_POREF_REG 0x010 59 /* LCD Clock Source select and control */ 60 #define PLUM_VIDEO_POCKL_REG 0x014 61 /* CRT Clock Source select and control */ 62 #define PLUM_VIDEO_POCKC_REG 0x018 63 /* PLL Clock Source select and control */ 64 #define PLUM_VIDEO_POPLL_REG 0x01c 65 66 /* 67 * LCD Panel Control Register 68 */ 69 /* LCD Control */ 70 #define PLUM_VIDEO_PLCNT_REG 0x040 71 /* STN Control */ 72 #define PLUM_VIDEO_PLSTN_REG 0x044 73 /* LCD Level control */ 74 #define PLUM_VIDEO_PLLEV_REG 0x048 75 /* LCD Luminance control */ 76 #define PLUM_VIDEO_PLLUM_REG 0x04c 77 /* DSTN Dither Pattern base address */ 78 #define PLUM_VIDEO_PLDPA_REG 0x050 79 /* DSTN VRAM Offscreen buffer address */ 80 #define PLUM_VIDEO_PLOSA_REG 0x054 81 82 /* 83 * CRT Control Register 84 */ 85 /* DAC Control */ 86 #define PLUM_VIDEO_PCDAC_REG 0x060 87 /* CRT Border Color */ 88 #define PLUM_VIDEO_PCBOC_REG 0x064 89 /* Palette snoop */ 90 #define PLUM_VIDEO_PCSNP_REG 0x068 91 92 /* 93 * LCD Timing Register 94 */ 95 /* Horizontanl Total */ 96 #define PLUM_VIDEO_PLHT_REG 0x080 97 /* Horizontal Display Start */ 98 #define PLUM_VIDEO_PLHDS_REG 0x084 99 /* H-Sync Start/End */ 100 #define PLUM_VIDEO_PLHSEHSS_REG 0x088 101 /* H-Blanking Start/End */ 102 #define PLUM_VIDEO_PLHBEHSS_REG 0x08c 103 /* Horizontal # of pixel */ 104 #define PLUM_VIDEO_PLHPX_REG 0x090 105 /* Vertical Total */ 106 #define PLUM_VIDEO_PLVT_REG 0x094 107 /* Vertical Display Start */ 108 #define PLUM_VIDEO_PLVDS_REG 0x098 109 /* V-Sync Start/End */ 110 #define PLUM_VIDEO_PLVSEVSS_REG 0x09c 111 /* V-Blankng Start/End */ 112 #define PLUM_VIDEO_PLVBEVBS_REG 0x0a0 113 /* Current Line # */ 114 #define PLUM_VIDEO_PLCLN_REG 0x0a8 115 /* Interrupt Line # */ 116 #define PLUM_VIDEO_PLILN_REG 0x0ac 117 /* Mode */ 118 #define PLUM_VIDEO_PLMOD_REG 0x0b0 119 /* LCD controller test */ 120 #define PLUM_VIDEO_PLTST_REG 0x0bc 121 122 /* 123 * LCD Graphics Register 124 */ 125 /* Double Buffer Select */ 126 #define PLUM_VIDEO_PLBSL_REG 0x0c0 127 /* Graphics Display Start Address */ 128 #define PLUM_VIDEO_PLDSA0_REG 0x0c4 129 #define PLUM_VIDEO_PLDSA1_REG 0x0c8 130 /* VRAM Pitch 1 */ 131 #define PLUM_VIDEO_PLPIT1_REG 0x0cc 132 /* VRAM Pitch 2 */ 133 #define PLUM_VIDEO_PLPIT2_REG 0x0d0 134 #define PLUM_VIDEO_PLPIT2_MASK 0xffffffe0 135 /* VRAM Offset */ 136 #define PLUM_VIDEO_PLOFS_REG 0x0d4 137 /* VRAM Lower Screen Address offset */ 138 #define PLUM_VIDEO_PLLSA_REG 0x0d8 139 /* Graphics Mode */ 140 #define PLUM_VIDEO_PLGMD_REG 0x0dc 141 142 #define PLUM_VIDEO_PLGMD_MASK 0x3 143 #define PLUM_VIDEO_PLGMD_DISABLE 0x0 144 #define PLUM_VIDEO_PLGMD_8BPP 0x1 145 #define PLUM_VIDEO_PLGMD_16BPP 0x2 146 /* 147 * CRT Timing Register 148 */ 149 /* notyet */ 150 /* 151 * CRT Graphics Register 152 */ 153 /* notyet */ 154
Indexes created Tue Sep 30 10:09:55 GMT 2025