plumvideoreg.h revision 1.4
1 /* $NetBSD: plumvideoreg.h,v 1.4 2000/05/08 21:57:57 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 UCHIYAMA Yasushi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* (CS3) */ 30 #define PLUM_VIDEO_REGBASE 0x1000 31 #define PLUM_VIDEO_REGSIZE 0x200 32 33 /* (MCS0) */ 34 /* VRAM 4MByte */ 35 #define PLUM_VIDEO_VRAM_IOBASE_PHYSICAL 0x6c000000 36 #define PLUM_VIDEO_VRAM_IOBASE 0x00000000 37 #define PLUM_VIDEO_VRAM_IOSIZE 0x00400000 38 /* Color palette LCD 4KByte */ 39 #define PLUM_VIDEO_CLUT_LCD_IOBASE 0x00400000 40 #define PLUM_VIDEO_CLUT_LCD_IOSIZE 0x00001000 41 /* Color palette CRT 4KByte */ 42 #define PLUM_VIDEO_CLUT_CRT_IOBASE 0x00401000 43 #define PLUM_VIDEO_CLUT_CRT_IOSIZE 0x00001000 44 /* BitBlt 4KByte */ 45 #define PLUM_VIDEO_BITBLT_IOBASE 0x00402000 46 #define PLUM_VIDEO_BITBLT_IOSIZE 0x00401000 47 48 /* 49 * Common Control Register 50 */ 51 /* Interrupt Status enable and IRQ line enable */ 52 #define PLUM_VIDEO_POSENIEN_REG 0x000 53 /* Interrupt Status */ 54 #define PLUM_VIDEO_POIST_REG 0x004 55 /* Buffer Control */ 56 #define PLUM_VIDEO_POBFC_REG 0x008 57 /* VRAM Control */ 58 #define PLUM_VIDEO_PORAM_REG 0x00c 59 /* VRAM Refresh Control */ 60 #define PLUM_VIDEO_POREF_REG 0x010 61 /* LCD Clock Source select and control */ 62 #define PLUM_VIDEO_POCKL_REG 0x014 63 /* CRT Clock Source select and control */ 64 #define PLUM_VIDEO_POCKC_REG 0x018 65 /* PLL Clock Source select and control */ 66 #define PLUM_VIDEO_POPLL_REG 0x01c 67 68 /* 69 * LCD Panel Control Register 70 */ 71 /* LCD Control */ 72 #define PLUM_VIDEO_PLCNT_REG 0x040 73 /* STN Control */ 74 #define PLUM_VIDEO_PLSTN_REG 0x044 75 /* LCD Level control */ 76 #define PLUM_VIDEO_PLLEV_REG 0x048 77 /* LCD Luminance control */ 78 #define PLUM_VIDEO_PLLUM_REG 0x04c 79 /* DSTN Dither Pattern base address */ 80 #define PLUM_VIDEO_PLDPA_REG 0x050 81 /* DSTN VRAM Offscreen buffer address */ 82 #define PLUM_VIDEO_PLOSA_REG 0x054 83 84 /* 85 * CRT Control Register 86 */ 87 /* DAC Control */ 88 #define PLUM_VIDEO_PCDAC_REG 0x060 89 /* CRT Border Color */ 90 #define PLUM_VIDEO_PCBOC_REG 0x064 91 /* Palette snoop */ 92 #define PLUM_VIDEO_PCSNP_REG 0x068 93 94 /* 95 * LCD Timing Register 96 */ 97 /* Horizontanl Total */ 98 #define PLUM_VIDEO_PLHT_REG 0x080 99 /* Horizontal Display Start */ 100 #define PLUM_VIDEO_PLHDS_REG 0x084 101 /* H-Sync Start/End */ 102 #define PLUM_VIDEO_PLHSEHSS_REG 0x088 103 /* H-Blanking Start/End */ 104 #define PLUM_VIDEO_PLHBEHSS_REG 0x08c 105 /* Horizontal # of pixel */ 106 #define PLUM_VIDEO_PLHPX_REG 0x090 107 /* Vertical Total */ 108 #define PLUM_VIDEO_PLVT_REG 0x094 109 /* Vertical Display Start */ 110 #define PLUM_VIDEO_PLVDS_REG 0x098 111 /* V-Sync Start/End */ 112 #define PLUM_VIDEO_PLVSEVSS_REG 0x09c 113 /* V-Blankng Start/End */ 114 #define PLUM_VIDEO_PLVBEVBS_REG 0x0a0 115 /* Current Line # */ 116 #define PLUM_VIDEO_PLCLN_REG 0x0a8 117 /* Interrupt Line # */ 118 #define PLUM_VIDEO_PLILN_REG 0x0ac 119 /* Mode */ 120 #define PLUM_VIDEO_PLMOD_REG 0x0b0 121 /* LCD controller test */ 122 #define PLUM_VIDEO_PLTST_REG 0x0bc 123 124 /* 125 * LCD Graphics Register 126 */ 127 /* Double Buffer Select */ 128 #define PLUM_VIDEO_PLBSL_REG 0x0c0 129 /* Graphics Display Start Address */ 130 #define PLUM_VIDEO_PLDSA0_REG 0x0c4 131 #define PLUM_VIDEO_PLDSA1_REG 0x0c8 132 /* VRAM Pitch 1 */ 133 #define PLUM_VIDEO_PLPIT1_REG 0x0cc 134 /* VRAM Pitch 2 */ 135 #define PLUM_VIDEO_PLPIT2_REG 0x0d0 136 #define PLUM_VIDEO_PLPIT2_MASK 0xffffffe0 137 /* VRAM Offset */ 138 #define PLUM_VIDEO_PLOFS_REG 0x0d4 139 /* VRAM Lower Screen Address offset */ 140 #define PLUM_VIDEO_PLLSA_REG 0x0d8 141 /* Graphics Mode */ 142 #define PLUM_VIDEO_PLGMD_REG 0x0dc 143 144 #define PLUM_VIDEO_PLGMD_GMODE_MASK 0x3 145 #define PLUM_VIDEO_PLGMD_DISABLE 0x0 146 #define PLUM_VIDEO_PLGMD_8BPP 0x1 147 #define PLUM_VIDEO_PLGMD_16BPP 0x2 148 149 #define PLUM_VIDEO_PLGMD_MODE_DISPLAY 0x4 150 #define PLUM_VIDEO_PLGMD_PALETTE_ENABLE 0x8 151 152 /* 153 * CRT Timing Register 154 */ 155 /* notyet */ 156 /* 157 * CRT Graphics Register 158 */ 159 /* notyet */ 160
Indexes created Tue Sep 30 11:09:46 GMT 2025