plumvideoreg.h revision 1.5
1 /* $NetBSD: plumvideoreg.h,v 1.5 2000/10/04 13:53:55 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* (CS3) */ 40 #define PLUM_VIDEO_REGBASE 0x1000 41 #define PLUM_VIDEO_REGSIZE 0x200 42 43 /* (MCS0) */ 44 /* VRAM 4MByte */ 45 #define PLUM_VIDEO_VRAM_IOBASE_PHYSICAL 0x6c000000 46 #define PLUM_VIDEO_VRAM_IOBASE 0x00000000 47 #define PLUM_VIDEO_VRAM_IOSIZE 0x00400000 48 /* Color palette LCD 4KByte */ 49 #define PLUM_VIDEO_CLUT_LCD_IOBASE 0x00400000 50 #define PLUM_VIDEO_CLUT_LCD_IOSIZE 0x00001000 51 /* Color palette CRT 4KByte */ 52 #define PLUM_VIDEO_CLUT_CRT_IOBASE 0x00401000 53 #define PLUM_VIDEO_CLUT_CRT_IOSIZE 0x00001000 54 /* BitBlt 4KByte */ 55 #define PLUM_VIDEO_BITBLT_IOBASE 0x00402000 56 #define PLUM_VIDEO_BITBLT_IOSIZE 0x00401000 57 58 /* 59 * Common Control Register 60 */ 61 /* Interrupt Status enable and IRQ line enable */ 62 #define PLUM_VIDEO_POSENIEN_REG 0x000 63 /* Interrupt Status */ 64 #define PLUM_VIDEO_POIST_REG 0x004 65 /* Buffer Control */ 66 #define PLUM_VIDEO_POBFC_REG 0x008 67 /* VRAM Control */ 68 #define PLUM_VIDEO_PORAM_REG 0x00c 69 /* VRAM Refresh Control */ 70 #define PLUM_VIDEO_POREF_REG 0x010 71 /* LCD Clock Source select and control */ 72 #define PLUM_VIDEO_POCKL_REG 0x014 73 /* CRT Clock Source select and control */ 74 #define PLUM_VIDEO_POCKC_REG 0x018 75 /* PLL Clock Source select and control */ 76 #define PLUM_VIDEO_POPLL_REG 0x01c 77 78 /* 79 * LCD Panel Control Register 80 */ 81 /* LCD Control */ 82 #define PLUM_VIDEO_PLCNT_REG 0x040 83 /* STN Control */ 84 #define PLUM_VIDEO_PLSTN_REG 0x044 85 /* LCD Level control */ 86 #define PLUM_VIDEO_PLLEV_REG 0x048 87 /* LCD Luminance control */ 88 #define PLUM_VIDEO_PLLUM_REG 0x04c 89 #define PLUM_VIDEO_PLLUM_MAX 0x3 90 #define PLUM_VIDEO_PLLUM_MIN 0x0 91 /* DSTN Dither Pattern base address */ 92 #define PLUM_VIDEO_PLDPA_REG 0x050 93 /* DSTN VRAM Offscreen buffer address */ 94 #define PLUM_VIDEO_PLOSA_REG 0x054 95 96 /* 97 * CRT Control Register 98 */ 99 /* DAC Control */ 100 #define PLUM_VIDEO_PCDAC_REG 0x060 101 /* CRT Border Color */ 102 #define PLUM_VIDEO_PCBOC_REG 0x064 103 /* Palette snoop */ 104 #define PLUM_VIDEO_PCSNP_REG 0x068 105 106 /* 107 * LCD Timing Register 108 */ 109 /* Horizontanl Total */ 110 #define PLUM_VIDEO_PLHT_REG 0x080 111 /* Horizontal Display Start */ 112 #define PLUM_VIDEO_PLHDS_REG 0x084 113 /* H-Sync Start/End */ 114 #define PLUM_VIDEO_PLHSEHSS_REG 0x088 115 /* H-Blanking Start/End */ 116 #define PLUM_VIDEO_PLHBEHSS_REG 0x08c 117 /* Horizontal # of pixel */ 118 #define PLUM_VIDEO_PLHPX_REG 0x090 119 /* Vertical Total */ 120 #define PLUM_VIDEO_PLVT_REG 0x094 121 /* Vertical Display Start */ 122 #define PLUM_VIDEO_PLVDS_REG 0x098 123 /* V-Sync Start/End */ 124 #define PLUM_VIDEO_PLVSEVSS_REG 0x09c 125 /* V-Blankng Start/End */ 126 #define PLUM_VIDEO_PLVBEVBS_REG 0x0a0 127 /* Current Line # */ 128 #define PLUM_VIDEO_PLCLN_REG 0x0a8 129 /* Interrupt Line # */ 130 #define PLUM_VIDEO_PLILN_REG 0x0ac 131 /* Mode */ 132 #define PLUM_VIDEO_PLMOD_REG 0x0b0 133 /* LCD controller test */ 134 #define PLUM_VIDEO_PLTST_REG 0x0bc 135 136 /* 137 * LCD Graphics Register 138 */ 139 /* Double Buffer Select */ 140 #define PLUM_VIDEO_PLBSL_REG 0x0c0 141 /* Graphics Display Start Address */ 142 #define PLUM_VIDEO_PLDSA0_REG 0x0c4 143 #define PLUM_VIDEO_PLDSA1_REG 0x0c8 144 /* VRAM Pitch 1 */ 145 #define PLUM_VIDEO_PLPIT1_REG 0x0cc 146 /* VRAM Pitch 2 */ 147 #define PLUM_VIDEO_PLPIT2_REG 0x0d0 148 #define PLUM_VIDEO_PLPIT2_MASK 0xffffffe0 149 /* VRAM Offset */ 150 #define PLUM_VIDEO_PLOFS_REG 0x0d4 151 /* VRAM Lower Screen Address offset */ 152 #define PLUM_VIDEO_PLLSA_REG 0x0d8 153 /* Graphics Mode */ 154 #define PLUM_VIDEO_PLGMD_REG 0x0dc 155 156 #define PLUM_VIDEO_PLGMD_GMODE_MASK 0x3 157 #define PLUM_VIDEO_PLGMD_DISABLE 0x0 158 #define PLUM_VIDEO_PLGMD_8BPP 0x1 159 #define PLUM_VIDEO_PLGMD_16BPP 0x2 160 161 #define PLUM_VIDEO_PLGMD_MODE_DISPLAY 0x4 162 #define PLUM_VIDEO_PLGMD_PALETTE_ENABLE 0x8 163 164 /* 165 * CRT Timing Register 166 */ 167 /* notyet */ 168 /* 169 * CRT Graphics Register 170 */ 171 /* notyet */ 172
Indexes created Tue Sep 30 11:09:46 GMT 2025