ucb1200reg.h revision 1.3
1 /* $NetBSD: ucb1200reg.h,v 1.3 2000/02/27 16:37:51 uch Exp $ */ 2 3 /* 4 * Copyright (c) 2000, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * PHILIPS UCB1200 Advanced modem/audio analog front-end 31 */ 32 33 /* Internal register. access via SIB */ 34 #define UCB1200_IO_DATA_REG 0 35 #define UCB1200_IO_DIR_REG 1 36 #define UCB1200_POSINTEN_REG 2 37 #define UCB1200_NEGINTEN_REG 3 38 #define UCB1200_INTSTAT_REG 4 39 #define UCB1200_TELECOMCTRLA_REG 5 40 #define UCB1200_TELECOMCTRLB_REG 6 41 #define UCB1200_AUDIOCTRLA_REG 7 42 #define UCB1200_AUDIOCTRLB_REG 8 43 #define UCB1200_TSCTRL_REG 9 44 #define UCB1200_ADCCTRL_REG 10 45 #define UCB1200_ADCDATA_REG 11 46 #define UCB1200_ID_REG 12 47 #define UCB1200_MODE_REG 13 48 #define UCB1200_RESERVED_REG 14 49 #define UCB1200_NULL_REG 15 /* always returns 0xffff */ 50 51 /* 52 * I/O port data register 53 */ 54 #define UCB1200_IOPORT_MAX 10 55 #define UCB1200_IO_DATA_SPEAKER 0x100 /* XXX general? */ 56 57 /* 58 * Telecom control register A 59 */ 60 #define UCB1200_TELECOMCTRLA_DIV_MIN 16 61 #define UCB1200_TELECOMCTRLA_DIV_MAX 127 62 #define UCB1200_TELECOMCTRLA_DIV_SHIFT 0 63 #define UCB1200_TELECOMCTRLA_DIV_MASK 0x7f 64 #define UCB1200_TELECOMCTRLA_DIV(cr) \ 65 (((cr) >> UCB1200_TELECOMCTRLA_DIV_SHIFT) & \ 66 UCB1200_TELECOMCTRLA_DIV_MASK) 67 #define UCB1200_TELECOMCTRLA_DIV_SET(cr, val) \ 68 ((cr) | (((val) << UCB1200_TELECOMCTRLA_DIV_SHIFT) & \ 69 (UCB1200_TELECOMCTRLA_DIV_MASK << UCB1200_TELECOMCTRLA_DIV_SHIFT))) 70 71 #define UCB1200_TELECOMCTRLA_LOOP 0x0080 72 73 /* 74 * Telecom control register B 75 */ 76 #define UCB1200_TELECOMCTRLB_VBF 0x0008 77 #define UCB1200_TELECOMCTRLB_CLIPSTATCLR 0x0010 78 #define UCB1200_TELECOMCTRLB_ATT 0x0040 79 #define UCB1200_TELECOMCTRLB_STS 0x0800 80 #define UCB1200_TELECOMCTRLB_MUTE 0x2000 81 #define UCB1200_TELECOMCTRLB_INEN 0x4000 82 #define UCB1200_TELECOMCTRLB_OUTEN 0x8000 83 84 /* 85 * Audio control register A 86 */ 87 #define UCB1200_AUDIOCTRLA_DIV_MIN 6 88 #define UCB1200_AUDIOCTRLA_DIV_MAX 127 89 #define UCB1200_AUDIOCTRLA_DIV_SHIFT 0 90 #define UCB1200_AUDIOCTRLA_DIV_MASK 0x7f 91 #define UCB1200_AUDIOCTRLA_DIV(cr) \ 92 (((cr) >> UCB1200_AUDIOCTRLA_DIV_SHIFT) & \ 93 UCB1200_AUDIOCTRLA_DIV_MASK) 94 #define UCB1200_AUDIOCTRLA_DIV_SET(cr, val) \ 95 ((cr) | (((val) << UCB1200_AUDIOCTRLA_DIV_SHIFT) & \ 96 (UCB1200_AUDIOCTRLA_DIV_MASK << UCB1200_AUDIOCTRLA_DIV_SHIFT))) 97 98 #define UCB1200_AUDIOCTRLA_GAIN_SHIFT 7 99 #define UCB1200_AUDIOCTRLA_GAIN_MASK 0x1f 100 #define UCB1200_AUDIOCTRLA_GAIN(cr) \ 101 (((cr) >> UCB1200_AUDIOCTRLA_GAIN_SHIFT) & \ 102 UCB1200_AUDIOCTRLA_GAIN_MASK) 103 #define UCB1200_AUDIOCTRLA_GAIN_SET(cr, val) \ 104 ((cr) | (((val) << UCB1200_AUDIOCTRLA_GAIN_SHIFT) & \ 105 (UCB1200_AUDIOCTRLA_GAIN_MASK << UCB1200_AUDIOCTRLA_GAIN_SHIFT))) 106 107 /* 108 * Audio control register B 109 */ 110 #define UCB1200_AUDIOCTRLB_ATT_MIN 0 111 #define UCB1200_AUDIOCTRLB_ATT_MAX 0x1f 112 #define UCB1200_AUDIOCTRLB_ATT_SHIFT 0 113 #define UCB1200_AUDIOCTRLB_ATT_MASK 0x1f 114 #define UCB1200_AUDIOCTRLB_ATT(cr) \ 115 (((cr) >> UCB1200_AUDIOCTRLB_ATT_SHIFT) & \ 116 UCB1200_AUDIOCTRLB_ATT_MASK) 117 #define UCB1200_AUDIOCTRLB_ATT_SET(cr, val) \ 118 ((cr) | (((val) << UCB1200_AUDIOCTRLB_ATT_SHIFT) & \ 119 (UCB1200_AUDIOCTRLB_ATT_MASK << UCB1200_AUDIOCTRLB_ATT_SHIFT))) 120 121 #define UCB1200_AUDIOCTRLB_CLIPSTATCLR 0x0040 122 #define UCB1200_AUDIOCTRLB_LOOP 0x0100 123 #define UCB1200_AUDIOCTRLB_MUTE 0x2000 124 #define UCB1200_AUDIOCTRLB_INEN 0x4000 125 #define UCB1200_AUDIOCTRLB_OUTEN 0x8000 126 127 /* 128 * Touch screen control register 129 */ 130 #define UCB1200_TSCTRL_MXLOW 0x00002000 131 #define UCB1200_TSCTRL_PXLOW 0x00001000 132 #define UCB1200_TSCTRL_BIAS 0x00000800 133 134 #define UCB1200_TSCTRL_MODE_SHIFT 8 135 #define UCB1200_TSCTRL_MODE_MASK 0x7f 136 #define UCB1200_TSCTRL_MODE(cr) \ 137 (((cr) >> UCB1200_TSCTRL_MODE_SHIFT) & \ 138 UCB1200_TSCTRL_MODE_MASK) 139 #define UCB1200_TSCTRL_MODE_INTERRUPT 0 140 #define UCB1200_TSCTRL_MODE_PRESSURE (1 << UCB1200_TSCTRL_MODE_SHIFT) 141 #define UCB1200_TSCTRL_MODE_POSITION0 (2 << UCB1200_TSCTRL_MODE_SHIFT) 142 #define UCB1200_TSCTRL_MODE_POSITION1 (3 << UCB1200_TSCTRL_MODE_SHIFT) 143 144 #define UCB1200_TSCTRL_PYGND 0x00000080 145 #define UCB1200_TSCTRL_MYGND 0x00000040 146 #define UCB1200_TSCTRL_PXGND 0x00000020 147 #define UCB1200_TSCTRL_MXGND 0x00000010 148 #define UCB1200_TSCTRL_PYPWR 0x00000008 149 #define UCB1200_TSCTRL_MYPWR 0x00000004 150 #define UCB1200_TSCTRL_PXPWR 0x00000002 151 #define UCB1200_TSCTRL_MXPWR 0x00000001 152 153 /* touch screen modes */ 154 #define UCB1200_TSCTRL_YPOSITION \ 155 (UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXGND | \ 156 UCB1200_TSCTRL_MODE_POSITION0 | UCB1200_TSCTRL_BIAS) 157 #define UCB1200_TSCTRL_XPOSITION \ 158 (UCB1200_TSCTRL_PYPWR | UCB1200_TSCTRL_MYGND | \ 159 UCB1200_TSCTRL_MODE_POSITION0 | UCB1200_TSCTRL_BIAS) 160 #define UCB1200_TSCTRL_PRESSURE \ 161 (UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXPWR | \ 162 UCB1200_TSCTRL_PYGND | UCB1200_TSCTRL_MYGND | \ 163 UCB1200_TSCTRL_MODE_PRESSURE | UCB1200_TSCTRL_BIAS) 164 #define UCB1200_TSCTRL_INTERRUPT \ 165 (UCB1200_TSCTRL_PXPWR | UCB1200_TSCTRL_MXPWR | \ 166 UCB1200_TSCTRL_PYGND | UCB1200_TSCTRL_MYGND | \ 167 UCB1200_TSCTRL_MODE_INTERRUPT) 168 169 #define UCB1200_TSCTRL_PRESSURE1 170 #define UCB1200_TSCTRL_PRESSURE2 171 #define UCB1200_TSCTRL_PRESSURE3 172 #define UCB1200_TSCTRL_PRESSURE4 173 #define UCB1200_TSCTRL_PRESSURE5 174 #define UCB1200_TSCTRL_XRESISTANCE 175 #define UCB1200_TSCTRL_YRESISTANCE 176 177 /* 178 * ADC control register 179 */ 180 #define UCB1200_ADCCTRL_ENABLE 0x8000 181 #define UCB1200_ADCCTRL_START 0x0080 182 #define UCB1200_ADCCTRL_EXTREF 0x0020 183 184 #define UCB1200_ADCCTRL_INPUT_SHIFT 2 185 #define UCB1200_ADCCTRL_INPUT_MASK 0x7 186 #define UCB1200_ADCCTRL_INPUT_SET(cr, val) \ 187 ((cr) | (((val) << UCB1200_ADCCTRL_INPUT_SHIFT) & \ 188 (UCB1200_ADCCTRL_INPUT_MASK << UCB1200_ADCCTRL_INPUT_SHIFT))) 189 #define UCB1200_ADCCTRL_INPUT_TSPX 0x0 190 #define UCB1200_ADCCTRL_INPUT_TSMX 0x1 191 #define UCB1200_ADCCTRL_INPUT_TSPY 0x2 192 #define UCB1200_ADCCTRL_INPUT_TSMY 0x3 193 #define UCB1200_ADCCTRL_INPUT_AD0 0x4 194 #define UCB1200_ADCCTRL_INPUT_AD1 0x5 195 #define UCB1200_ADCCTRL_INPUT_AD2 0x6 196 #define UCB1200_ADCCTRL_INPUT_AD3 0x7 197 198 #define UCB1200_ADCCTRL_VREFBYP 0x0002 199 #define UCB1200_ADCCTRL_SYNCMODE 0x0001 200 201 /* 202 * ADC data register 203 */ 204 #define UCB1200_ADCDATA_INPROGRESS 0x8000 205 206 #define UCB1200_ADCDATA_SHIFT 5 207 #define UCB1200_ADCDATA_MASK 0x3ff 208 #define UCB1200_ADCDATA(cr) \ 209 (((cr) >> UCB1200_ADCDATA_SHIFT) & \ 210 UCB1200_ADCDATA_MASK) 211 212 /* 213 * ID register 214 */ 215 /* Version 4, Device 0, Supplier 1 */ 216 #define UCB1200_ID 0x1004 217 /* TOSHIBA TC35413F */ 218 #define TC35413F_ID 0x9712 219
Indexes created Mon Sep 29 03:10:08 GMT 2025