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intr.h revision 1.1 
      1 /*	$NetBSD: intr.h,v 1.1 1999/09/16 12:23:22 takemura Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Jonathan Stone for
     17  *      the NetBSD Project.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #ifndef _HPCMIPS_INTR_H_
     34 #define _HPCMIPS_INTR_H_
     35 
     36 #define	IPL_NONE	0	/* disable only this interrupt */
     37 #define	IPL_BIO		1	/* disable block I/O interrupts */
     38 #define	IPL_NET		2	/* disable network interrupts */
     39 #define	IPL_TTY		3	/* disable terminal interrupts */
     40 #define	IPL_CLOCK	4	/* disable clock interrupts */
     41 #define	IPL_STATCLOCK	5	/* disable profiling interrupts */
     42 #if 0 /* XXX */
     43 #define	IPL_SERIAL	6	/* disable serial hardware interrupts */
     44 #endif
     45 #define	IPL_DMA		7	/* disable DMA reload interrupts */
     46 #define	IPL_HIGH	8	/* disable all interrupts */
     47 
     48 /* Interrupt sharing types. */
     49 #define	IST_NONE	0	/* none */
     50 #define	IST_PULSE	1	/* pulsed */
     51 #define	IST_EDGE	2	/* edge-triggered */
     52 #define	IST_LEVEL	3	/* level-triggered */
     53 
     54 #ifdef _KERNEL
     55 #ifndef _LOCORE
     56 
     57 #include <mips/cpuregs.h>
     58 
     59 extern int _splraise __P((int));
     60 extern int _spllower __P((int));
     61 extern int _splset __P((int));
     62 extern int _splget __P((void));
     63 extern void _splnone __P((void));
     64 extern void _setsoftintr __P((int));
     65 extern void _clrsoftintr __P((int));
     66 
     67 #define setsoftclock()	_setsoftintr(MIPS_SOFT_INT_MASK_0)
     68 #define setsoftnet()	_setsoftintr(MIPS_SOFT_INT_MASK_1)
     69 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0)
     70 #define clearsoftnet()	 _clrsoftintr(MIPS_SOFT_INT_MASK_1)
     71 
     72 #define splhigh()	_splraise(MIPS_INT_MASK)
     73 #define spl0()		(void)_spllower(0)
     74 #define splx(s)		(void)_splset(s)
     75 #define splbio()	(_splraise(splvec.splbio))
     76 #define splnet()	(_splraise(splvec.splnet))
     77 #define spltty()	(_splraise(splvec.spltty))
     78 #define splimp()	(_splraise(splvec.splimp))
     79 #define splpmap()	(_splraise(splvec.splimp))
     80 #define splclock()	(_splraise(splvec.splclock))
     81 #define splstatclock()	(_splraise(splvec.splstatclock))
     82 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0)
     83 #define splsoftclock()	_splraise(MIPS_SOFT_INT_MASK_0)
     84 #define splsoftnet()	_splraise(MIPS_SOFT_INT_MASK_1)
     85 
     86 struct splvec {
     87 	int	splbio;
     88 	int	splnet;
     89 	int	spltty;
     90 	int	splimp;
     91 	int	splclock;
     92 	int	splstatclock;
     93 };
     94 extern struct splvec splvec;
     95 
     96 /* Conventionals ... */
     97 
     98 #define MIPS_SPLHIGH (MIPS_INT_MASK)
     99 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
    100 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
    101 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1)
    102 #define MIPS_SPL_0_1	 (MIPS_INT_MASK_1|MIPS_SPL0)
    103 #define MIPS_SPL_0_1_2	 (MIPS_INT_MASK_2|MIPS_SPL_0_1)
    104 #define MIPS_SPL_0_1_3	 (MIPS_INT_MASK_3|MIPS_SPL_0_1)
    105 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2)
    106 
    107 /*
    108  * Index into intrcnt[], which is defined in locore
    109  */
    110 extern u_long intrcnt[];
    111 
    112 #define	SOFTCLOCK_INTR	0
    113 #define	SOFTNET_INTR	1
    114 #define	SERIAL0_INTR	2
    115 #define	SERIAL1_INTR	3
    116 #define	SERIAL2_INTR	4
    117 #define	LANCE_INTR	5
    118 #define	SCSI_INTR	6
    119 #define	ERROR_INTR	7
    120 #define	HARDCLOCK	8
    121 #define	FPU_INTR	9
    122 #define	SLOT0_INTR	10
    123 #define	SLOT1_INTR	11
    124 #define	SLOT2_INTR	12
    125 #define	DTOP_INTR	13
    126 #define	ISDN_INTR	14
    127 #define	FLOPPY_INTR	15
    128 #define	STRAY_INTR	16
    129 
    130 /* handle i/o device interrupts */
    131 extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned));
    132 
    133 #endif /* !_LOCORE */
    134 #endif /* _KERNEL */
    135 
    136 #endif /* !_HPCMIPS_INTR_H_ */
    137