intr.h revision 1.12
1 /* $NetBSD: intr.h,v 1.12 2001/09/15 15:04:45 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPCMIPS_INTR_H_ 34 #define _HPCMIPS_INTR_H_ 35 36 #include <sys/device.h> 37 #include <sys/lock.h> 38 #include <sys/queue.h> 39 40 #define IPL_NONE 0 /* disable only this interrupt */ 41 42 #define IPL_SOFT 1 /* generic software interrupts (SI 0) */ 43 #define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */ 44 #define IPL_SOFTNET 3 /* network software interrupts (SI 1) */ 45 #define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */ 46 47 #define IPL_BIO 5 /* disable block I/O interrupts */ 48 #define IPL_NET 6 /* disable network interrupts */ 49 #define IPL_TTY 7 /* disable terminal interrupts */ 50 #define IPL_SERIAL 7 /* disable serial hardware interrupts */ 51 #define IPL_CLOCK 8 /* disable clock interrupts */ 52 #define IPL_STATCLOCK 8 /* disable profiling interrupts */ 53 #define IPL_HIGH 8 /* disable all interrupts */ 54 55 #define _IPL_NSOFT 4 56 #define _IPL_N 9 57 58 #define _IPL_SI0_FIRST IPL_SOFT 59 #define _IPL_SI0_LAST IPL_SOFTCLOCK 60 61 #define _IPL_SI1_FIRST IPL_SOFTNET 62 #define _IPL_SI1_LAST IPL_SOFTSERIAL 63 64 #define IPL_SOFTNAMES { \ 65 "misc", \ 66 "clock", \ 67 "net", \ 68 "serial", \ 69 } 70 71 /* Interrupt sharing types. */ 72 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 73 #define IST_NONE 0 /* none */ 74 #define IST_PULSE 1 /* pulsed */ 75 #define IST_EDGE 2 /* edge-triggered */ 76 #define IST_LEVEL 3 /* level-triggered */ 77 78 #ifdef _KERNEL 79 #ifndef _LOCORE 80 81 #include <mips/cpuregs.h> 82 83 extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT]; 84 85 int _splraise(int); 86 int _spllower(int); 87 int _splset(int); 88 int _splget(void); 89 void _splnone(void); 90 void _setsoftintr(int); 91 void _clrsoftintr(int); 92 93 #define splhigh() _splraise(MIPS_INT_MASK) 94 #define spl0() (void)_spllower(0) 95 #define splx(s) (void)_splset(s) 96 #define splbio() (_splraise(splvec.splbio)) 97 #define splnet() (_splraise(splvec.splnet)) 98 #define spltty() (_splraise(splvec.spltty)) 99 #define splserial() spltty() 100 #define splvm() (_splraise(splvec.splvm)) 101 #define splclock() (_splraise(splvec.splclock)) 102 #define splstatclock() (_splraise(splvec.splstatclock)) 103 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0) 104 #define splsoft() _splraise(MIPS_SOFT_INT_MASK_0) 105 #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) 106 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 107 #define splsoftserial() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 108 109 #define splsched() splhigh() 110 #define spllock() splhigh() 111 112 struct splvec { 113 int splbio; 114 int splnet; 115 int spltty; 116 int splvm; 117 int splclock; 118 int splstatclock; 119 }; 120 extern struct splvec splvec; 121 122 /* Conventionals ... */ 123 124 #define MIPS_SPLHIGH (MIPS_INT_MASK) 125 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 126 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 127 #define MIPS_SPL2 (MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 128 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 129 #define MIPS_SPL4 (MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 130 #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0) 131 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1) 132 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1) 133 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2) 134 #define MIPS_SPL_2_4 (MIPS_INT_MASK_4|MIPS_SPL2) 135 136 /* 137 * Index into intrcnt[], which is defined in locore 138 */ 139 extern u_long intrcnt[]; 140 141 #define SOFTCLOCK_INTR 0 142 #define SOFTNET_INTR 1 143 #define SERIAL0_INTR 2 144 #define SERIAL1_INTR 3 145 #define SERIAL2_INTR 4 146 #define LANCE_INTR 5 147 #define SCSI_INTR 6 148 #define ERROR_INTR 7 149 #define HARDCLOCK 8 150 #define FPU_INTR 9 151 #define SLOT0_INTR 10 152 #define SLOT1_INTR 11 153 #define SLOT2_INTR 12 154 #define DTOP_INTR 13 155 #define ISDN_INTR 14 156 #define FLOPPY_INTR 15 157 #define STRAY_INTR 16 158 159 /* 160 * software simulated interrupt 161 */ 162 #define setsoft(x) \ 163 do { \ 164 _setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \ 165 } while (0) 166 167 struct hpcmips_soft_intrhand { 168 TAILQ_ENTRY(hpcmips_soft_intrhand) 169 sih_q; 170 struct hpcmips_soft_intr *sih_intrhead; 171 void (*sih_fn)(void *); 172 void *sih_arg; 173 int sih_pending; 174 }; 175 176 struct hpcmips_soft_intr { 177 TAILQ_HEAD(, hpcmips_soft_intrhand) 178 softintr_q; 179 struct evcnt softintr_evcnt; 180 struct simplelock softintr_slock; 181 unsigned long softintr_ipl; 182 }; 183 184 void *softintr_establish(int, void (*)(void *), void *); 185 void softintr_disestablish(void *); 186 void softintr_init(void); 187 void softintr_dispatch(void); 188 189 #define softintr_schedule(arg) \ 190 do { \ 191 struct hpcmips_soft_intrhand *__sih = (arg); \ 192 struct hpcmips_soft_intr *__si = __sih->sih_intrhead; \ 193 int __s; \ 194 \ 195 __s = splhigh(); \ 196 simple_lock(&__si->softintr_slock); \ 197 if (__sih->sih_pending == 0) { \ 198 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 199 __sih->sih_pending = 1; \ 200 setsoft(__si->softintr_ipl); \ 201 } \ 202 simple_unlock(&__si->softintr_slock); \ 203 splx(__s); \ 204 } while (0) 205 206 /* XXX For legacy software interrupts. */ 207 extern struct hpcmips_soft_intrhand *softnet_intrhand; 208 209 #define setsoftnet() softintr_schedule(softnet_intrhand) 210 211 #endif /* !_LOCORE */ 212 #endif /* _KERNEL */ 213 214 #endif /* !_HPCMIPS_INTR_H_ */ 215
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