intr.h revision 1.16.58.1
1 /* $NetBSD: intr.h,v 1.16.58.1 2006/09/21 14:30:50 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPCMIPS_INTR_H_ 34 #define _HPCMIPS_INTR_H_ 35 36 #include <sys/device.h> 37 #include <sys/lock.h> 38 #include <sys/queue.h> 39 40 #define IPL_NONE 0 /* disable only this interrupt */ 41 42 #define IPL_SOFT 1 /* generic software interrupts (SI 0) */ 43 #define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */ 44 #define IPL_SOFTNET 3 /* network software interrupts (SI 1) */ 45 #define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */ 46 47 #define IPL_BIO 5 /* disable block I/O interrupts */ 48 #define IPL_NET 6 /* disable network interrupts */ 49 #define IPL_TTY 7 /* disable terminal interrupts */ 50 #define IPL_LPT IPL_TTY 51 #define IPL_VM IPL_TTY 52 #define IPL_SERIAL 7 /* disable serial hardware interrupts */ 53 #define IPL_CLOCK 8 /* disable clock interrupts */ 54 #define IPL_STATCLOCK IPL_CLOCK 55 #define IPL_SCHED IPL_CLOCK 56 #define IPL_HIGH 8 /* disable all interrupts */ 57 #define IPL_LOCK IPL_HIGH 58 59 #define _IPL_NSOFT 4 60 #define _IPL_N 9 61 62 #define _IPL_SI0_FIRST IPL_SOFT 63 #define _IPL_SI0_LAST IPL_SOFTCLOCK 64 65 #define _IPL_SI1_FIRST IPL_SOFTNET 66 #define _IPL_SI1_LAST IPL_SOFTSERIAL 67 68 #define IPL_SOFTNAMES { \ 69 "misc", \ 70 "clock", \ 71 "net", \ 72 "serial", \ 73 } 74 75 /* Interrupt sharing types. */ 76 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 77 #define IST_NONE 0 /* none */ 78 #define IST_PULSE 1 /* pulsed */ 79 #define IST_EDGE 2 /* edge-triggered */ 80 #define IST_LEVEL 3 /* level-triggered */ 81 82 #ifdef _KERNEL 83 #ifndef _LOCORE 84 #include <mips/cpuregs.h> 85 86 extern const u_int32_t *ipl_sr_bits; 87 extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT]; 88 89 void intr_init(void); 90 int _splraise(int); 91 int _spllower(int); 92 int _splset(int); 93 int _splget(void); 94 void _splnone(void); 95 void _setsoftintr(int); 96 void _clrsoftintr(int); 97 98 #define spl0() (void) _spllower(0) 99 #define splx(s) (void) _splset(s) 100 101 #define splsoft() _splraise(ipl_sr_bits[IPL_SOFT]) 102 103 #define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK]) 104 105 typedef int ipl_t; 106 typedef struct { 107 ipl_t _sr; 108 } ipl_cookie_t; 109 110 static inline ipl_cookie_t 111 makeiplcookie(ipl_t ipl) 112 { 113 114 return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]}; 115 } 116 117 static inline int 118 splraiseipl(ipl_cookie_t icookie) 119 { 120 121 return _splraise(icookie._sr); 122 } 123 124 #include <sys/spl.h> 125 126 /* 127 * software simulated interrupt 128 */ 129 #define setsoft(x) \ 130 do { \ 131 _setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \ 132 } while (0) 133 134 struct hpcmips_soft_intrhand { 135 TAILQ_ENTRY(hpcmips_soft_intrhand) 136 sih_q; 137 struct hpcmips_soft_intr *sih_intrhead; 138 void (*sih_fn)(void *); 139 void *sih_arg; 140 int sih_pending; 141 }; 142 143 struct hpcmips_soft_intr { 144 TAILQ_HEAD(, hpcmips_soft_intrhand) 145 softintr_q; 146 struct evcnt softintr_evcnt; 147 struct simplelock softintr_slock; 148 unsigned long softintr_ipl; 149 }; 150 151 void softintr_init(void); 152 void softintr(u_int32_t); 153 void *softintr_establish(int, void (*)(void *), void *); 154 void softintr_disestablish(void *); 155 void softintr_dispatch(void); 156 157 #define softintr_schedule(arg) \ 158 do { \ 159 struct hpcmips_soft_intrhand *__sih = (arg); \ 160 struct hpcmips_soft_intr *__si = __sih->sih_intrhead; \ 161 int __s; \ 162 \ 163 __s = splhigh(); \ 164 simple_lock(&__si->softintr_slock); \ 165 if (__sih->sih_pending == 0) { \ 166 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 167 __sih->sih_pending = 1; \ 168 setsoft(__si->softintr_ipl); \ 169 } \ 170 simple_unlock(&__si->softintr_slock); \ 171 splx(__s); \ 172 } while (0) 173 174 /* XXX For legacy software interrupts. */ 175 extern struct hpcmips_soft_intrhand *softnet_intrhand; 176 177 #define setsoftnet() softintr_schedule(softnet_intrhand) 178 179 #endif /* !_LOCORE */ 180 #endif /* _KERNEL */ 181 182 #endif /* !_HPCMIPS_INTR_H_ */ 183
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