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intr.h revision 1.19
      1 /*	$NetBSD: intr.h,v 1.19 2007/06/17 06:04:28 tsutsui Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1998 Jonathan Stone.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Jonathan Stone for
     17  *      the NetBSD Project.
     18  * 4. The name of the author may not be used to endorse or promote products
     19  *    derived from this software without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     31  */
     32 
     33 #ifndef _HPCMIPS_INTR_H_
     34 #define _HPCMIPS_INTR_H_
     35 
     36 #include <sys/device.h>
     37 #include <sys/lock.h>
     38 #include <sys/queue.h>
     39 
     40 #define	IPL_NONE	0	/* disable only this interrupt */
     41 #define	IPL_SOFT	1	/* generic software interrupts (SI 0) */
     42 #define	IPL_SOFTCLOCK	2	/* clock software interrupts (SI 0) */
     43 #define	IPL_SOFTNET	3	/* network software interrupts (SI 1) */
     44 #define	IPL_SOFTSERIAL	4	/* serial software interrupts (SI 1) */
     45 #define	IPL_BIO		5	/* disable block I/O interrupts */
     46 #define	IPL_NET		6	/* disable network interrupts */
     47 #define	IPL_TTY		7	/* disable terminal interrupts */
     48 #define	IPL_LPT		IPL_TTY
     49 #define	IPL_VM		IPL_TTY
     50 #define	IPL_SERIAL	7	/* disable serial hardware interrupts */
     51 #define	IPL_CLOCK	8	/* disable clock interrupts */
     52 #define	IPL_STATCLOCK	IPL_CLOCK
     53 #define	IPL_SCHED	IPL_CLOCK
     54 #define	IPL_HIGH	8	/* disable all interrupts */
     55 #define	IPL_LOCK	IPL_HIGH
     56 
     57 #define	_IPL_N		9
     58 
     59 #define	_IPL_SI0_FIRST	IPL_SOFT
     60 #define	_IPL_SI0_LAST	IPL_SOFTCLOCK
     61 
     62 #define	_IPL_SI1_FIRST	IPL_SOFTNET
     63 #define	_IPL_SI1_LAST	IPL_SOFTSERIAL
     64 
     65 #define	SI_SOFT		0
     66 #define	SI_SOFTCLOCK	1
     67 #define	SI_SOFTNET	2
     68 #define	SI_SOFTSERIAL	3
     69 
     70 #define	SI_NQUEUES	4
     71 
     72 #define	SI_QUEUENAMES {							\
     73 	"misc",								\
     74 	"clock",							\
     75 	"net",								\
     76 	"serial",							\
     77 }
     78 
     79 /* Interrupt sharing types. */
     80 #define	IST_UNUSABLE	-1	/* interrupt cannot be used */
     81 #define	IST_NONE	0	/* none */
     82 #define	IST_PULSE	1	/* pulsed */
     83 #define	IST_EDGE	2	/* edge-triggered */
     84 #define	IST_LEVEL	3	/* level-triggered */
     85 
     86 #ifdef _KERNEL
     87 #ifndef _LOCORE
     88 #include <mips/cpuregs.h>
     89 #include <mips/locore.h>
     90 
     91 extern const u_int32_t *ipl_sr_bits;
     92 extern const u_int32_t ipl_si_to_sr[SI_NQUEUES];
     93 
     94 void	intr_init(void);
     95 
     96 #define	spl0()		(void) _spllower(0)
     97 #define	splx(s)		(void) _splset(s)
     98 
     99 #define	splsoft()	_splraise(ipl_sr_bits[IPL_SOFT])
    100 
    101 typedef int ipl_t;
    102 typedef struct {
    103 	ipl_t _sr;
    104 } ipl_cookie_t;
    105 
    106 static inline ipl_cookie_t
    107 makeiplcookie(ipl_t ipl)
    108 {
    109 
    110 	return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
    111 }
    112 
    113 static inline int
    114 splraiseipl(ipl_cookie_t icookie)
    115 {
    116 
    117 	return _splraise(icookie._sr);
    118 }
    119 
    120 #include <sys/spl.h>
    121 
    122 /*
    123  * software simulated interrupt
    124  */
    125 #define	setsoft(x)							\
    126 do {									\
    127 	_setsoftintr(ipl_si_to_sr[(x)]);				\
    128 } while (0)
    129 
    130 struct hpcmips_soft_intrhand {
    131 	TAILQ_ENTRY(hpcmips_soft_intrhand)
    132 		sih_q;
    133 	struct hpcmips_soft_intr *sih_intrhead;
    134 	void	(*sih_fn)(void *);
    135 	void	*sih_arg;
    136 	int	sih_pending;
    137 };
    138 
    139 struct hpcmips_soft_intr {
    140 	TAILQ_HEAD(, hpcmips_soft_intrhand)
    141 		softintr_q;
    142 	struct evcnt softintr_evcnt;
    143 	struct simplelock softintr_slock;
    144 	unsigned long softintr_siq;
    145 };
    146 
    147 void	softintr_init(void);
    148 void	softintr(u_int32_t);
    149 void	*softintr_establish(int, void (*)(void *), void *);
    150 void	softintr_disestablish(void *);
    151 void	softintr_dispatch(void);
    152 
    153 #define	softintr_schedule(arg)						\
    154 do {									\
    155 	struct hpcmips_soft_intrhand *__sih = (arg);			\
    156 	struct hpcmips_soft_intr *__si = __sih->sih_intrhead;		\
    157 	int __s;							\
    158 									\
    159 	__s = splhigh();						\
    160 	simple_lock(&__si->softintr_slock);				\
    161 	if (__sih->sih_pending == 0) {					\
    162 		TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q);	\
    163 		__sih->sih_pending = 1;					\
    164 		setsoft(__si->softintr_siq);				\
    165 	}								\
    166 	simple_unlock(&__si->softintr_slock);				\
    167 	splx(__s);							\
    168 } while (0)
    169 
    170 /* XXX For legacy software interrupts. */
    171 extern struct hpcmips_soft_intrhand *softnet_intrhand;
    172 
    173 #define	setsoftnet()	softintr_schedule(softnet_intrhand)
    174 
    175 #endif /* !_LOCORE */
    176 #endif /* _KERNEL */
    177 
    178 #endif /* !_HPCMIPS_INTR_H_ */
    179