intr.h revision 1.3
1 /* $NetBSD: intr.h,v 1.3 2000/04/03 03:37:25 sato Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPCMIPS_INTR_H_ 34 #define _HPCMIPS_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_BIO 1 /* disable block I/O interrupts */ 38 #define IPL_NET 2 /* disable network interrupts */ 39 #define IPL_TTY 3 /* disable terminal interrupts */ 40 #define IPL_CLOCK 4 /* disable clock interrupts */ 41 #define IPL_STATCLOCK 5 /* disable profiling interrupts */ 42 #if 0 /* XXX */ 43 #define IPL_SERIAL 6 /* disable serial hardware interrupts */ 44 #endif 45 #define IPL_DMA 7 /* disable DMA reload interrupts */ 46 #define IPL_HIGH 8 /* disable all interrupts */ 47 48 /* Interrupt sharing types. */ 49 #define IST_NONE 0 /* none */ 50 #define IST_PULSE 1 /* pulsed */ 51 #define IST_EDGE 2 /* edge-triggered */ 52 #define IST_LEVEL 3 /* level-triggered */ 53 54 #ifdef _KERNEL 55 #ifndef _LOCORE 56 57 #include <mips/cpuregs.h> 58 #include <mips/intr.h> 59 60 int _splraise __P((int)); 61 int _spllower __P((int)); 62 int _splset __P((int)); 63 int _splget __P((void)); 64 void _splnone __P((void)); 65 void _setsoftintr __P((int)); 66 void _clrsoftintr __P((int)); 67 68 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 69 #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1) 70 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0) 71 #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1) 72 73 #define splhigh() _splraise(MIPS_INT_MASK) 74 #define spl0() (void)_spllower(0) 75 #define splx(s) (void)_splset(s) 76 #define splbio() (_splraise(splvec.splbio)) 77 #define splnet() (_splraise(splvec.splnet)) 78 #define spltty() (_splraise(splvec.spltty)) 79 #define splimp() (_splraise(splvec.splimp)) 80 #define splpmap() (_splraise(splvec.splimp)) 81 #define splclock() (_splraise(splvec.splclock)) 82 #define splstatclock() (_splraise(splvec.splstatclock)) 83 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0) 84 #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) 85 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1) 86 87 struct splvec { 88 int splbio; 89 int splnet; 90 int spltty; 91 int splimp; 92 int splclock; 93 int splstatclock; 94 }; 95 extern struct splvec splvec; 96 97 /* Conventionals ... */ 98 99 #define MIPS_SPLHIGH (MIPS_INT_MASK) 100 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 101 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 102 #define MIPS_SPL2 (MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 103 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 104 #define MIPS_SPL4 (MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 105 #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0) 106 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1) 107 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1) 108 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2) 109 #define MIPS_SPL_2_4 (MIPS_INT_MASK_4|MIPS_SPL2) 110 111 /* 112 * Index into intrcnt[], which is defined in locore 113 */ 114 extern u_long intrcnt[]; 115 116 #define SOFTCLOCK_INTR 0 117 #define SOFTNET_INTR 1 118 #define SERIAL0_INTR 2 119 #define SERIAL1_INTR 3 120 #define SERIAL2_INTR 4 121 #define LANCE_INTR 5 122 #define SCSI_INTR 6 123 #define ERROR_INTR 7 124 #define HARDCLOCK 8 125 #define FPU_INTR 9 126 #define SLOT0_INTR 10 127 #define SLOT1_INTR 11 128 #define SLOT2_INTR 12 129 #define DTOP_INTR 13 130 #define ISDN_INTR 14 131 #define FLOPPY_INTR 15 132 #define STRAY_INTR 16 133 134 #endif /* !_LOCORE */ 135 #endif /* _KERNEL */ 136 137 #endif /* !_HPCMIPS_INTR_H_ */ 138
Indexes created Thu Sep 25 16:09:42 GMT 2025