intr.h revision 1.5
1 /* $NetBSD: intr.h,v 1.5 2000/04/11 17:57:43 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPCMIPS_INTR_H_ 34 #define _HPCMIPS_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_BIO 1 /* disable block I/O interrupts */ 38 #define IPL_NET 2 /* disable network interrupts */ 39 #define IPL_TTY 3 /* disable terminal interrupts */ 40 #define IPL_CLOCK 4 /* disable clock interrupts */ 41 #define IPL_STATCLOCK 5 /* disable profiling interrupts */ 42 #if 0 /* XXX */ 43 #define IPL_SERIAL 6 /* disable serial hardware interrupts */ 44 #endif 45 #define IPL_DMA 7 /* disable DMA reload interrupts */ 46 #define IPL_HIGH 8 /* disable all interrupts */ 47 48 /* Interrupt sharing types. */ 49 #define IST_NONE 0 /* none */ 50 #define IST_PULSE 1 /* pulsed */ 51 #define IST_EDGE 2 /* edge-triggered */ 52 #define IST_LEVEL 3 /* level-triggered */ 53 54 #ifdef _KERNEL 55 #ifndef _LOCORE 56 57 #include <mips/cpuregs.h> 58 59 int _splraise __P((int)); 60 int _spllower __P((int)); 61 int _splset __P((int)); 62 int _splget __P((void)); 63 void _splnone __P((void)); 64 void _setsoftintr __P((int)); 65 void _clrsoftintr __P((int)); 66 67 #define splhigh() _splraise(MIPS_INT_MASK) 68 #define spl0() (void)_spllower(0) 69 #define splx(s) (void)_splset(s) 70 #define splbio() (_splraise(splvec.splbio)) 71 #define splnet() (_splraise(splvec.splnet)) 72 #define spltty() (_splraise(splvec.spltty)) 73 #define splimp() (_splraise(splvec.splimp)) 74 #define splpmap() (_splraise(splvec.splimp)) 75 #define splclock() (_splraise(splvec.splclock)) 76 #define splstatclock() (_splraise(splvec.splstatclock)) 77 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0) 78 #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) 79 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 80 81 struct splvec { 82 int splbio; 83 int splnet; 84 int spltty; 85 int splimp; 86 int splclock; 87 int splstatclock; 88 }; 89 extern struct splvec splvec; 90 91 /* Conventionals ... */ 92 93 #define MIPS_SPLHIGH (MIPS_INT_MASK) 94 #define MIPS_SPL0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 95 #define MIPS_SPL1 (MIPS_INT_MASK_1|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 96 #define MIPS_SPL2 (MIPS_INT_MASK_2|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 97 #define MIPS_SPL3 (MIPS_INT_MASK_3|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 98 #define MIPS_SPL4 (MIPS_INT_MASK_4|MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 99 #define MIPS_SPL_0_1 (MIPS_INT_MASK_1|MIPS_SPL0) 100 #define MIPS_SPL_0_1_2 (MIPS_INT_MASK_2|MIPS_SPL_0_1) 101 #define MIPS_SPL_0_1_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1) 102 #define MIPS_SPL_0_1_2_3 (MIPS_INT_MASK_3|MIPS_SPL_0_1_2) 103 #define MIPS_SPL_2_4 (MIPS_INT_MASK_4|MIPS_SPL2) 104 105 /* 106 * Index into intrcnt[], which is defined in locore 107 */ 108 extern u_long intrcnt[]; 109 110 #define SOFTCLOCK_INTR 0 111 #define SOFTNET_INTR 1 112 #define SERIAL0_INTR 2 113 #define SERIAL1_INTR 3 114 #define SERIAL2_INTR 4 115 #define LANCE_INTR 5 116 #define SCSI_INTR 6 117 #define ERROR_INTR 7 118 #define HARDCLOCK 8 119 #define FPU_INTR 9 120 #define SLOT0_INTR 10 121 #define SLOT1_INTR 11 122 #define SLOT2_INTR 12 123 #define DTOP_INTR 13 124 #define ISDN_INTR 14 125 #define FLOPPY_INTR 15 126 #define STRAY_INTR 16 127 128 /* 129 * software simulated interrupt 130 */ 131 extern unsigned ssir; 132 133 #define SIR_NET 0x1 134 135 #define setsoftnet() setsoft(SIR_NET) 136 #define setsoft(x) \ 137 do { ssir |= (x); _setsoftintr(MIPS_SOFT_INT_MASK_1); } while (0) 138 139 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 140 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0) 141 #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1) 142 143 #endif /* !_LOCORE */ 144 #endif /* _KERNEL */ 145 146 #endif /* !_HPCMIPS_INTR_H_ */ 147
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