11.42Sandvar/* $NetBSD: isa_machdep.c,v 1.42 2022/09/25 12:41:46 andvar Exp $ */ 21.1Stakemura 31.16Such/*- 41.16Such * Copyright (c) 1999 The NetBSD Foundation, Inc. 51.1Stakemura * All rights reserved. 61.1Stakemura * 71.16Such * This code is derived from software contributed to The NetBSD Foundation 81.16Such * by UCHIYAMA Yasushi. 91.16Such * 101.1Stakemura * Redistribution and use in source and binary forms, with or without 111.1Stakemura * modification, are permitted provided that the following conditions 121.1Stakemura * are met: 131.1Stakemura * 1. Redistributions of source code must retain the above copyright 141.1Stakemura * notice, this list of conditions and the following disclaimer. 151.16Such * 2. Redistributions in binary form must reproduce the above copyright 161.16Such * notice, this list of conditions and the following disclaimer in the 171.16Such * documentation and/or other materials provided with the distribution. 181.1Stakemura * 191.16Such * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 201.16Such * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 211.16Such * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 221.16Such * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 231.16Such * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241.16Such * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251.16Such * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261.16Such * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271.16Such * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281.16Such * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291.16Such * POSSIBILITY OF SUCH DAMAGE. 301.1Stakemura */ 311.28Slukem 321.28Slukem#include <sys/cdefs.h> 331.42Sandvar__KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.42 2022/09/25 12:41:46 andvar Exp $"); 341.16Such 351.16Such#include "opt_vr41xx.h" 361.16Such 371.1Stakemura#include <sys/param.h> 381.1Stakemura#include <sys/systm.h> 391.10Ssato#include <sys/reboot.h> 401.33Sad#include <sys/device.h> 411.1Stakemura 421.1Stakemura#include <dev/isa/isavar.h> 431.1Stakemura#include <dev/isa/isareg.h> 441.1Stakemura 451.1Stakemura#include <machine/platid.h> 461.1Stakemura#include <machine/platid_mask.h> 471.18Stakemura#include <machine/bus.h> 481.18Stakemura#include <machine/bus_space_hpcmips.h> 491.23Such#include <machine/debug.h> 501.1Stakemura 511.13Stakemura#include <dev/hpc/hpciovar.h> 521.13Stakemura 531.22Stakemura#include <hpcmips/vr/vripif.h> 541.1Stakemura 551.1Stakemura#include "locators.h" 561.1Stakemura 571.4Ssato#define VRISADEBUG 581.4Ssato 591.4Ssato#ifdef VRISADEBUG 601.4Ssato#ifndef VRISADEBUG_CONF 611.4Ssato#define VRISADEBUG_CONF 0 621.4Ssato#endif /* VRISADEBUG_CONF */ 631.4Ssatoint vrisa_debug = VRISADEBUG_CONF; 641.4Ssato#define DPRINTF(arg) if (vrisa_debug) printf arg; 651.23Such#define DBITDISP(mask) if (vrisa_debug) dbg_bit_print(mask); 661.8Sjdolecek#define VPRINTF(arg) if (bootverbose || vrisa_debug) printf arg; 671.4Ssato#else /* VRISADEBUG */ 681.4Ssato#define DPRINTF(arg) 691.23Such#define DBITDISP(mask) 701.8Sjdolecek#define VPRINTF(arg) if (bootverbose) printf arg; 711.4Ssato#endif /* VRISADEBUG */ 721.4Ssato 731.13Stakemura/* 741.42Sandvar * interrupt no. encoding: 751.13Stakemura * 761.13Stakemura * 0x0000000f ISA IRQ# 771.13Stakemura * 0x00ff0000 GPIO port# 781.13Stakemura * 0x01000000 interrupt signal hold/through (1:hold/0:though) 791.13Stakemura * 0x02000000 interrupt detection level (1:low /0:high ) 801.13Stakemura * 0x04000000 interrupt detection trigger (1:edge/0:level ) 811.13Stakemura */ 821.13Stakemura#define INTR_IRQ(i) (((i)>> 0) & 0x0f) 831.13Stakemura#define INTR_PORT(i) (((i)>>16) & 0xff) 841.13Stakemura#define INTR_MODE(i) (((i)>>24) & 0x07) 851.13Stakemura#define INTR_NIRQS 16 861.13Stakemura 871.16Suchint vrisabprint(void *, const char *); 881.39Schsint vrisabmatch(device_t, cfdata_t, void *); 891.39Schsvoid vrisabattach(device_t, device_t, void *); 901.1Stakemura 911.1Stakemurastruct vrisab_softc { 921.13Stakemura hpcio_chip_t sc_hc; 931.42Sandvar int sc_intr_map[INTR_NIRQS]; /* ISA <-> GIU interrupt line mapping */ 941.3Stakemura struct hpcmips_isa_chipset sc_isa_ic; 951.1Stakemura}; 961.1Stakemura 971.39SchsCFATTACH_DECL_NEW(vrisab, sizeof(struct vrisab_softc), 981.27Sthorpej vrisabmatch, vrisabattach, NULL, NULL); 991.1Stakemura 1001.1Stakemura#ifdef DEBUG_FIND_PCIC 1011.1Stakemura#include <mips/cpuregs.h> 1021.1Stakemura#warning DEBUG_FIND_PCIC 1031.16Suchstatic void __find_pcic(void); 1041.1Stakemura#endif 1051.1Stakemura 1061.11Ssato#ifdef DEBUG_FIND_COMPORT 1071.11Ssato#include <mips/cpuregs.h> 1081.11Ssato#include <dev/ic/ns16550reg.h> 1091.11Ssato#include <dev/ic/comreg.h> 1101.11Ssato#warning DEBUG_FIND_COMPORT 1111.16Suchstatic void __find_comport(void); 1121.11Ssato#endif 1131.11Ssato 1141.1Stakemuraint 1151.39Schsvrisabmatch(device_t parent, cfdata_t match, void *aux) 1161.1Stakemura{ 1171.13Stakemura struct hpcio_attach_args *haa = aux; 1181.1Stakemura platid_mask_t mask; 1191.20Stakemura int n; 1201.20Stakemura 1211.25Sthorpej if (strcmp(haa->haa_busname, match->cf_name)) 1221.16Such return (0); 1231.16Such 1241.13Stakemura if (match->cf_loc[HPCIOIFCF_PLATFORM] == HPCIOIFCF_PLATFORM_DEFAULT) 1251.16Such return (1); 1261.16Such 1271.13Stakemura mask = PLATID_DEREF(match->cf_loc[HPCIOIFCF_PLATFORM]); 1281.20Stakemura if ((n = platid_match(&platid, &mask)) != 0) 1291.20Stakemura return (n + 2); 1301.16Such 1311.16Such return (0); 1321.1Stakemura} 1331.1Stakemura 1341.1Stakemuravoid 1351.39Schsvrisabattach(device_t parent, device_t self, void *aux) 1361.1Stakemura{ 1371.13Stakemura struct hpcio_attach_args *haa = aux; 1381.39Schs struct vrisab_softc *sc = device_private(self); 1391.1Stakemura struct isabus_attach_args iba; 1401.18Stakemura struct bus_space_tag_hpcmips *iot, *memt; 1411.1Stakemura bus_addr_t offset; 1421.1Stakemura int i; 1431.1Stakemura 1441.13Stakemura sc->sc_hc = (*haa->haa_getchip)(haa->haa_sc, VRIP_IOCHIP_VRGIU); 1451.3Stakemura sc->sc_isa_ic.ic_sc = sc; 1461.1Stakemura 1471.3Stakemura iba.iba_ic = &sc->sc_isa_ic; 1481.1Stakemura iba.iba_dmat = 0; /* XXX not yet */ 1491.1Stakemura 1501.1Stakemura /* Allocate ISA memory space */ 1511.19Stakemura memt = hpcmips_alloc_bus_space_tag(); 1521.39Schs offset = device_cfdata(self)->cf_loc[VRISABIFCF_ISAMEMOFFSET]; 1531.19Stakemura hpcmips_init_bus_space(memt, 1541.19Stakemura (struct bus_space_tag_hpcmips *)haa->haa_iot, "ISA mem", 1551.18Stakemura VR_ISA_MEM_BASE + offset, VR_ISA_MEM_SIZE - offset); 1561.19Stakemura iba.iba_memt = &memt->bst; 1571.1Stakemura 1581.1Stakemura /* Allocate ISA port space */ 1591.19Stakemura iot = hpcmips_alloc_bus_space_tag(); 1601.39Schs offset = device_cfdata(self)->cf_loc[VRISABIFCF_ISAPORTOFFSET]; 1611.19Stakemura hpcmips_init_bus_space(iot, 1621.19Stakemura (struct bus_space_tag_hpcmips *)haa->haa_iot, "ISA port", 1631.18Stakemura VR_ISA_PORT_BASE + offset, VR_ISA_PORT_SIZE - offset); 1641.19Stakemura iba.iba_iot = &iot->bst; 1651.1Stakemura 1661.1Stakemura#ifdef DEBUG_FIND_PCIC 1671.1Stakemura#warning DEBUG_FIND_PCIC 1681.1Stakemura __find_pcic(); 1691.1Stakemura#else 1701.1Stakemura /* Initialize ISA IRQ <-> GPIO mapping */ 1711.13Stakemura for (i = 0; i < INTR_NIRQS; i++) 1721.1Stakemura sc->sc_intr_map[i] = -1; 1731.15Senami printf(": ISA port %#x-%#x mem %#x-%#x\n", 1741.18Stakemura iot->base, iot->base + iot->size, 1751.18Stakemura memt->base, memt->base + memt->size); 1761.41Sthorpej config_found(self, &iba, vrisabprint, CFARGS_NONE); 1771.1Stakemura#endif 1781.11Ssato 1791.11Ssato#ifdef DEBUG_FIND_COMPORT 1801.11Ssato#warning DEBUG_FIND_COMPORT 1811.11Ssato __find_comport(); 1821.11Ssato#endif 1831.1Stakemura} 1841.1Stakemura 1851.1Stakemuraint 1861.16Suchvrisabprint(void *aux, const char *pnp) 1871.1Stakemura{ 1881.1Stakemura if (pnp) 1891.1Stakemura return (QUIET); 1901.16Such 1911.1Stakemura return (UNCONF); 1921.1Stakemura} 1931.1Stakemura 1941.1Stakemuravoid 1951.39Schsisa_attach_hook(device_t parent, device_t self, 1961.16Such struct isabus_attach_args *iba) 1971.1Stakemura{ 1981.16Such 1991.6Scgd} 2001.6Scgd 2011.37Sdyoungvoid 2021.38Sdyoungisa_detach_hook(isa_chipset_tag_t ic, device_t self) 2031.37Sdyoung{ 2041.37Sdyoung} 2051.37Sdyoung 2061.6Scgdconst struct evcnt * 2071.6Scgdisa_intr_evcnt(isa_chipset_tag_t ic, int irq) 2081.6Scgd{ 2091.6Scgd 2101.6Scgd /* XXX for now, no evcnt parent reported */ 2111.16Such return (NULL); 2121.1Stakemura} 2131.1Stakemura 2141.1Stakemuravoid * 2151.16Suchisa_intr_establish(isa_chipset_tag_t ic, int intr, int type, int level, 2161.16Such int (*ih_fun)(void*), void *ih_arg) 2171.1Stakemura{ 2181.3Stakemura struct vrisab_softc *sc = ic->ic_sc; 2191.3Stakemura int port, irq, mode; 2201.2Stakemura 2211.2Stakemura static int intr_modes[8] = { 2221.13Stakemura HPCIO_INTR_LEVEL_HIGH_THROUGH, 2231.13Stakemura HPCIO_INTR_LEVEL_HIGH_HOLD, 2241.13Stakemura HPCIO_INTR_LEVEL_LOW_THROUGH, 2251.13Stakemura HPCIO_INTR_LEVEL_LOW_HOLD, 2261.13Stakemura HPCIO_INTR_EDGE_THROUGH, 2271.13Stakemura HPCIO_INTR_EDGE_HOLD, 2281.13Stakemura HPCIO_INTR_EDGE_THROUGH, 2291.13Stakemura HPCIO_INTR_EDGE_HOLD, 2301.2Stakemura }; 2311.4Ssato#ifdef VRISADEBUG 2321.30She static const char* intr_mode_names[8] = { 2331.2Stakemura "level high through", 2341.2Stakemura "level high hold", 2351.2Stakemura "level low through", 2361.2Stakemura "level low hold", 2371.2Stakemura "edge through", 2381.2Stakemura "edge hold", 2391.2Stakemura "edge through", 2401.2Stakemura "edge hold", 2411.2Stakemura }; 2421.4Ssato#endif /* VRISADEBUG */ 2431.1Stakemura /* 2441.1Stakemura * ISA IRQ <-> GPIO port mapping 2451.1Stakemura */ 2461.2Stakemura irq = INTR_IRQ(intr); 2471.3Stakemura if (sc->sc_intr_map[irq] != -1) { 2481.3Stakemura /* already mapped */ 2491.3Stakemura intr = sc->sc_intr_map[irq]; 2501.2Stakemura } else { 2511.3Stakemura /* not mapped yet */ 2521.3Stakemura sc->sc_intr_map[irq] = intr; /* Register it */ 2531.1Stakemura } 2541.3Stakemura mode = INTR_MODE(intr); 2551.3Stakemura port = INTR_PORT(intr); 2561.3Stakemura 2571.14Stakemura VPRINTF(("ISA IRQ %d -> %s port %d, %s\n", 2581.16Such irq, sc->sc_hc->hc_name, port, intr_mode_names[mode])); 2591.3Stakemura 2601.1Stakemura /* Call Vr routine */ 2611.16Such return (hpcio_intr_establish(sc->sc_hc, port, intr_modes[mode], 2621.16Such ih_fun, ih_arg)); 2631.1Stakemura} 2641.1Stakemura 2651.1Stakemuravoid 2661.35Sdslisa_intr_disestablish(isa_chipset_tag_t ic, void *arg) 2671.1Stakemura{ 2681.3Stakemura struct vrisab_softc *sc = ic->ic_sc; 2691.1Stakemura /* Call Vr routine */ 2701.13Stakemura hpcio_intr_disestablish(sc->sc_hc, arg); 2711.1Stakemura} 2721.1Stakemura 2731.1Stakemuraint 2741.16Suchisa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq) 2751.1Stakemura{ 2761.1Stakemura /* XXX not coded yet. this is temporary XXX */ 2771.4Ssato DPRINTF(("isa_intr_alloc:")); 2781.23Such DBITDISP(mask); 2791.3Stakemura *irq = (ffs(mask) -1); /* XXX */ 2801.16Such 2811.16Such return (0); 2821.1Stakemura} 2831.1Stakemura 2841.1Stakemura#ifdef DEBUG_FIND_PCIC 2851.1Stakemura#warning DEBUG_FIND_PCIC 2861.1Stakemurastatic void 2871.1Stakemura__find_pcic(void) 2881.1Stakemura{ 2891.1Stakemura int i, j, step, found; 2901.1Stakemura u_int32_t addr; 2911.1Stakemura u_int8_t reg; 2921.1Stakemura int __read_revid (u_int32_t port) 2931.16Such { 2941.16Such addr = MIPS_PHYS_TO_KSEG1(i + port); 2951.16Such printf("%#x\r", i); 2961.16Such for (found = 0, j = 0; j < 0x100; j += 0x40) { 2971.16Such *((volatile u_int8_t *)addr) = j; 2981.16Such reg = *((volatile u_int8_t *)(addr + 1)); 2991.1Stakemura#ifdef DEBUG_FIND_PCIC_I82365SL_ONLY 3001.16Such if (reg == 0x82 || reg == 0x83) { 3011.1Stakemura#else 3021.17Sshin if ((reg & 0xc0) == 0x80) { 3031.1Stakemura#endif 3041.16Such found++; 3051.16Such } 3061.16Such if (found) 3071.16Such printf("\nfound %d socket at %#x" 3081.16Such "(base from %#x)\n", found, addr, 3091.16Such i + port - VR_ISA_PORT_BASE); 3101.17Sshin } 3111.16Such } 3121.1Stakemura step = 0x1000000; 3131.1Stakemura printf("\nFinding PCIC. Trying ISA port %#x-%#x step %#x\n", 3141.16Such VR_ISA_PORT_BASE, VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE, step); 3151.16Such for (i = VR_ISA_PORT_BASE; i < VR_ISA_PORT_BASE+VR_ISA_PORT_SIZE; 3161.16Such i+= step) { 3171.1Stakemura __read_revid (0x3e0); 3181.1Stakemura __read_revid (0x3e2); 3191.11Ssato } 3201.11Ssato} 3211.16Such#endif /* DEBUG_FIND_PCIC */ 3221.11Ssato 3231.11Ssato 3241.11Ssato#ifdef DEBUG_FIND_COMPORT 3251.11Ssato#warning DEBUG_FIND_COMPORT 3261.11Ssato 3271.16Suchstatic int probe_com(u_int32_t); 3281.11Ssato 3291.16Suchstatic int 3301.16Suchprobe_com(u_int32_t port_addr) 3311.11Ssato{ 3321.16Such u_int32_t addr; 3331.16Such u_int8_t ubtmp1, ubtmp2; 3341.11Ssato 3351.16Such addr = MIPS_PHYS_TO_KSEG1(port_addr); 3361.11Ssato 3371.16Such *((volatile u_int8_t *)(addr + com_cfcr)) = LCR_8BITS; 3381.16Such *((volatile u_int8_t *)(addr + com_iir)) = 0; 3391.11Ssato 3401.16Such ubtmp1 = *((volatile u_int8_t *)(addr + com_cfcr)); 3411.16Such ubtmp2 = *((volatile u_int8_t *)(addr + com_iir)); 3421.11Ssato 3431.16Such if ((ubtmp1 != LCR_8BITS) || ((ubtmp2 & 0x38) != 0)) { 3441.16Such return (0); 3451.11Ssato } 3461.11Ssato 3471.16Such return (1); 3481.11Ssato} 3491.11Ssato 3501.11Ssatostatic void 3511.36Scegger__find_comport(void) 3521.11Ssato{ 3531.16Such int found; 3541.16Such u_int32_t port, step; 3551.11Ssato 3561.11Ssato found = 0; 3571.11Ssato step = 0x08; 3581.11Ssato 3591.11Ssato printf("Searching COM port. Trying ISA port %#x-%#x step %#x\n", 3601.16Such VR_ISA_PORT_BASE, VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE - 1, step ); 3611.11Ssato 3621.16Such for (port = VR_ISA_PORT_BASE; 3631.16Such port < (VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE); port += step){ 3641.16Such if (probe_com(port)) { 3651.11Ssato found++; 3661.16Such printf("found %d at %#x\n", found, port); 3671.11Ssato } 3681.1Stakemura } 3691.1Stakemura} 3701.16Such#endif /* DEBUG_FIND_COMPORT */ 371