isa_machdep.c revision 1.3
1/* $NetBSD: isa_machdep.c,v 1.3 2000/03/05 04:34:07 takemura Exp $ */ 2 3/* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28#include <sys/param.h> 29#include <sys/systm.h> 30#include <sys/device.h> 31 32#include <machine/bus.h> 33 34#include <dev/isa/isavar.h> 35#include <dev/isa/isareg.h> 36 37#include <machine/platid.h> 38#include <machine/platid_mask.h> 39 40#include <hpcmips/vr/vripreg.h> 41#include <hpcmips/vr/vripvar.h> 42#include <hpcmips/vr/vrgiureg.h> 43 44#include "locators.h" 45 46int vrisabprint __P((void*, const char*)); 47int vrisabmatch __P((struct device*, struct cfdata*, void*)); 48void vrisabattach __P((struct device*, struct device*, void*)); 49 50struct vrisab_softc { 51 struct device sc_dev; 52 vrgiu_chipset_tag_t sc_gc; 53 vrgiu_function_tag_t sc_gf; 54 int sc_intr_map[MAX_GPIO_INOUT]; /* ISA <-> GIU inerrupt line mapping */ 55 struct hpcmips_isa_chipset sc_isa_ic; 56}; 57 58struct cfattach vrisab_ca = { 59 sizeof(struct vrisab_softc), vrisabmatch, vrisabattach 60}; 61 62#ifdef DEBUG_FIND_PCIC 63#include <mips/cpuregs.h> 64#warning DEBUG_FIND_PCIC 65static void __find_pcic __P((void)); 66#endif 67 68int 69vrisabmatch(parent, match, aux) 70 struct device *parent; 71 struct cfdata *match; 72 void *aux; 73{ 74 struct gpbus_attach_args *gpa = aux; 75 platid_mask_t mask; 76 77 if (strcmp(gpa->gpa_busname, match->cf_driver->cd_name)) 78 return 0; 79 if (match->cf_loc[VRISABIFCF_PLATFORM] == VRISABIFCF_PLATFORM_DEFAULT) 80 return 1; 81 mask = PLATID_DEREF(match->cf_loc[VRISABIFCF_PLATFORM]); 82 if (platid_match(&platid, &mask)) 83 return 2; 84 return 0; 85} 86 87void 88vrisabattach(parent, self, aux) 89 struct device *parent; 90 struct device *self; 91 void *aux; 92{ 93 struct gpbus_attach_args *gpa = aux; 94 struct vrgiu_softc *chipset; 95 struct vrisab_softc *sc = (void*)self; 96 struct isabus_attach_args iba; 97 bus_addr_t offset; 98 int i; 99 100 sc->sc_gc = chipset = gpa->gpa_gc; 101 sc->sc_gf = gpa->gpa_gf; 102 sc->sc_isa_ic.ic_sc = sc; 103 104 iba.iba_busname = "isa"; 105 iba.iba_ic = &sc->sc_isa_ic; 106 iba.iba_dmat = 0; /* XXX not yet */ 107 108 /* Allocate ISA memory space */ 109 iba.iba_memt = hpcmips_alloc_bus_space_tag(); 110 strcpy(iba.iba_memt->t_name, "ISA mem"); 111 offset = sc->sc_dev.dv_cfdata->cf_loc[VRISABIFCF_ISAMEMOFFSET]; 112 iba.iba_memt->t_base = VR_ISA_MEM_BASE + offset; 113 iba.iba_memt->t_size = VR_ISA_MEM_SIZE - offset; 114 hpcmips_init_bus_space_extent(iba.iba_memt); 115 116 /* Allocate ISA port space */ 117 iba.iba_iot = hpcmips_alloc_bus_space_tag(); 118 strcpy(iba.iba_iot->t_name, "ISA port"); 119 /* Platform dependent setting. */ 120 offset = sc->sc_dev.dv_cfdata->cf_loc[VRISABIFCF_ISAPORTOFFSET]; 121 iba.iba_iot->t_base = VR_ISA_PORT_BASE + offset; 122 iba.iba_iot->t_size = VR_ISA_PORT_SIZE - offset; 123 124 hpcmips_init_bus_space_extent(iba.iba_iot); 125 126#ifdef DEBUG_FIND_PCIC 127#warning DEBUG_FIND_PCIC 128 __find_pcic(); 129#else 130 /* Initialize ISA IRQ <-> GPIO mapping */ 131 for (i = 0; i < MAX_GPIO_INOUT; i++) 132 sc->sc_intr_map[i] = -1; 133 printf (":ISA port %#x-%#x mem %#x-%#x\n", 134 iba.iba_iot->t_base, iba.iba_iot->t_base + iba.iba_iot->t_size, 135 iba.iba_memt->t_base, iba.iba_memt->t_base + iba.iba_memt->t_base); 136 config_found(self, &iba, vrisabprint); 137#endif 138} 139 140int 141vrisabprint(aux, pnp) 142 void *aux; 143 const char *pnp; 144{ 145 if (pnp) 146 return (QUIET); 147 return (UNCONF); 148} 149 150void 151isa_attach_hook(parent, self, iba) 152 struct device *parent, *self; 153 struct isabus_attach_args *iba; 154{ 155} 156 157void * 158isa_intr_establish(ic, intr, type, level, ih_fun, ih_arg) 159 isa_chipset_tag_t ic; 160 int intr; 161 int type; /* XXX not yet */ 162 int level; /* XXX not yet */ 163 int (*ih_fun) __P((void*)); 164 void *ih_arg; 165{ 166 struct vrisab_softc *sc = ic->ic_sc; 167 int port, irq, mode; 168 169 /* 170 * 'intr' encoding: 171 * 172 * 0x0000000f ISA IRQ# 173 * 0x00ff0000 GPIO port# 174 * 0x01000000 interrupt signal hold/through (1:hold/0:though) 175 * 0x02000000 interrupt detection level (1:low /0:high ) 176 * 0x04000000 interrupt detection trigger (1:edge/0:level ) 177 */ 178#define INTR_IRQ(i) (((i)>> 0) & 0x0f) 179#define INTR_PORT(i) (((i)>>16) & 0xff) 180#define INTR_MODE(i) (((i)>>24) & 0x07) 181 static int intr_modes[8] = { 182 VRGIU_INTR_LEVEL_HIGH_THROUGH, 183 VRGIU_INTR_LEVEL_HIGH_HOLD, 184 VRGIU_INTR_LEVEL_LOW_THROUGH, 185 VRGIU_INTR_LEVEL_LOW_HOLD, 186 VRGIU_INTR_EDGE_THROUGH, 187 VRGIU_INTR_EDGE_HOLD, 188 VRGIU_INTR_EDGE_THROUGH, 189 VRGIU_INTR_EDGE_HOLD, 190 }; 191 static char* intr_mode_names[8] = { 192 "level high through", 193 "level high hold", 194 "level low through", 195 "level low hold", 196 "edge through", 197 "edge hold", 198 "edge through", 199 "edge hold", 200 }; 201 202 /* 203 * ISA IRQ <-> GPIO port mapping 204 */ 205 irq = INTR_IRQ(intr); 206 if (sc->sc_intr_map[irq] != -1) { 207 /* already mapped */ 208 intr = sc->sc_intr_map[irq]; 209 } else { 210 /* not mapped yet */ 211 sc->sc_intr_map[irq] = intr; /* Register it */ 212 } 213 mode = INTR_MODE(intr); 214 port = INTR_PORT(intr); 215 216 printf("ISA IRQ %d -> GPIO port %d, %s\n", 217 irq, port, intr_mode_names[mode]); 218 219 /* Call Vr routine */ 220 return sc->sc_gf->gf_intr_establish(sc->sc_gc, port, 221 intr_modes[mode], 222 level, ih_fun, ih_arg); 223} 224 225void 226isa_intr_disestablish(ic, arg) 227 isa_chipset_tag_t ic; 228 void *arg; 229{ 230 struct vrisab_softc *sc = ic->ic_sc; 231 /* Call Vr routine */ 232 sc->sc_gf->gf_intr_disestablish(sc->sc_gc, arg); 233} 234 235int 236isa_intr_alloc(ic, mask, type, irq) 237 isa_chipset_tag_t ic; 238 int mask; 239 int type; 240 int *irq; 241{ 242 /* XXX not coded yet. this is temporary XXX */ 243 printf ("isa_intr_alloc:"); 244 bitdisp32(mask); 245 *irq = (ffs(mask) -1); /* XXX */ 246 return 0; 247} 248 249#ifdef DEBUG_FIND_PCIC 250#warning DEBUG_FIND_PCIC 251static void 252__find_pcic(void) 253{ 254 int i, j, step, found; 255 u_int32_t addr; 256 u_int8_t reg; 257 int __read_revid (u_int32_t port) 258 { 259 addr = MIPS_PHYS_TO_KSEG1(i + port); 260 printf("%#x\r", i); 261 for (found = 0, j = 0; j < 0x100; j += 0x40) { 262 *((volatile u_int8_t*)addr) = j; 263 reg = *((volatile u_int8_t*)(addr + 1)); 264#ifdef DEBUG_FIND_PCIC_I82365SL_ONLY 265 if (reg == 0x82 || reg == 0x83) { 266#else 267 if ((reg & 0xc0) == 0x80) { 268#endif 269 found++; 270 } 271 } 272 if (found) 273 printf("\nfound %d socket at %#x (base from %#x)\n", found, addr, 274 i + port - VR_ISA_PORT_BASE); 275 }; 276 step = 0x1000000; 277 printf("\nFinding PCIC. Trying ISA port %#x-%#x step %#x\n", 278 VR_ISA_PORT_BASE, VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE, step); 279 for (i = VR_ISA_PORT_BASE; i < VR_ISA_PORT_BASE+VR_ISA_PORT_SIZE; i+= step) { 280 __read_revid (0x3e0); 281 __read_revid (0x3e2); 282 } 283} 284#endif 285