isa_machdep.c revision 1.9 
1/*	$NetBSD: isa_machdep.c,v 1.9 2000/09/25 01:56:56 sato Exp $	*/
2
3/*
4 * Copyright (c) 1999, by UCHIYAMA Yasushi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. The name of the developer may NOT be used to endorse or promote products
13 *    derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/device.h>
31#include <sys/boot_flag.h>
32
33#include <machine/bus.h>
34
35#include <dev/isa/isavar.h>
36#include <dev/isa/isareg.h>
37
38#include <machine/platid.h>
39#include <machine/platid_mask.h>
40
41#include <hpcmips/hpcmips/machdep.h>
42#include <hpcmips/vr/vripreg.h>
43#include <hpcmips/vr/vripvar.h>
44#include <hpcmips/vr/vrgiureg.h>
45
46#include "locators.h"
47
48#define VRISADEBUG
49
50#ifdef VRISADEBUG
51#ifndef VRISADEBUG_CONF
52#define VRISADEBUG_CONF 0
53#endif /* VRISADEBUG_CONF */
54int vrisa_debug = VRISADEBUG_CONF;
55#define DPRINTF(arg) if (vrisa_debug) printf arg;
56#define DBITDISP32(mask) if (vrisa_debug) bitdisp32(mask);
57#define VPRINTF(arg) if (bootverbose || vrisa_debug) printf arg;
58#else /* VRISADEBUG */
59#define DPRINTF(arg)
60#define DBITDISP32(mask)
61#define VPRINTF(arg) if (bootverbose) printf arg;
62#endif /* VRISADEBUG */
63
64int	vrisabprint __P((void*, const char*));
65int	vrisabmatch __P((struct device*, struct cfdata*, void*));
66void	vrisabattach __P((struct device*, struct device*, void*));
67
68struct vrisab_softc {
69	struct device sc_dev;
70	vrgiu_chipset_tag_t sc_gc;
71	vrgiu_function_tag_t sc_gf;
72	int sc_intr_map[MAX_GPIO_INOUT]; /* ISA <-> GIU inerrupt line mapping */
73	struct hpcmips_isa_chipset sc_isa_ic;
74};
75
76struct cfattach vrisab_ca = {
77	sizeof(struct vrisab_softc), vrisabmatch, vrisabattach
78};
79
80#ifdef DEBUG_FIND_PCIC
81#include <mips/cpuregs.h>
82#warning DEBUG_FIND_PCIC
83static void __find_pcic __P((void));
84#endif
85
86int
87vrisabmatch(parent, match, aux)
88	struct device *parent;
89	struct cfdata *match;
90	void *aux;
91{
92	struct gpbus_attach_args *gpa = aux;
93	platid_mask_t mask;
94
95	if (strcmp(gpa->gpa_busname, match->cf_driver->cd_name))
96		return 0;
97	if (match->cf_loc[VRISABIFCF_PLATFORM] == VRISABIFCF_PLATFORM_DEFAULT)
98		return 1;
99	mask = PLATID_DEREF(match->cf_loc[VRISABIFCF_PLATFORM]);
100	if (platid_match(&platid, &mask))
101		return 2;
102	return 0;
103}
104
105void
106vrisabattach(parent, self, aux)
107	struct device *parent;
108	struct device *self;
109	void *aux;
110{
111	struct gpbus_attach_args *gpa = aux;
112	struct vrgiu_softc *chipset;
113	struct vrisab_softc *sc = (void*)self;
114	struct isabus_attach_args iba;
115	bus_addr_t offset;
116	int i;
117
118	sc->sc_gc = chipset = gpa->gpa_gc;
119	sc->sc_gf = gpa->gpa_gf;
120	sc->sc_isa_ic.ic_sc = sc;
121
122	iba.iba_busname = "isa";
123	iba.iba_ic	= &sc->sc_isa_ic;
124	iba.iba_dmat    = 0; /* XXX not yet */
125
126	/* Allocate ISA memory space */
127	iba.iba_memt    = hpcmips_alloc_bus_space_tag();
128	strcpy(iba.iba_memt->t_name, "ISA mem");
129	offset = sc->sc_dev.dv_cfdata->cf_loc[VRISABIFCF_ISAMEMOFFSET];
130	iba.iba_memt->t_base = VR_ISA_MEM_BASE + offset;
131	iba.iba_memt->t_size = VR_ISA_MEM_SIZE - offset;
132	hpcmips_init_bus_space_extent(iba.iba_memt);
133
134	/* Allocate ISA port space */
135	iba.iba_iot     = hpcmips_alloc_bus_space_tag();
136	strcpy(iba.iba_iot->t_name, "ISA port");
137	/* Platform dependent setting. */
138	offset = sc->sc_dev.dv_cfdata->cf_loc[VRISABIFCF_ISAPORTOFFSET];
139	iba.iba_iot->t_base = VR_ISA_PORT_BASE + offset;
140	iba.iba_iot->t_size = VR_ISA_PORT_SIZE - offset;
141
142	hpcmips_init_bus_space_extent(iba.iba_iot);
143
144#ifdef DEBUG_FIND_PCIC
145#warning DEBUG_FIND_PCIC
146	__find_pcic();
147#else
148	/* Initialize ISA IRQ <-> GPIO mapping */
149	for (i = 0; i < MAX_GPIO_INOUT; i++)
150		sc->sc_intr_map[i] = -1;
151	printf (":ISA port %#x-%#x mem %#x-%#x\n",
152		iba.iba_iot->t_base, iba.iba_iot->t_base + iba.iba_iot->t_size,
153		iba.iba_memt->t_base, iba.iba_memt->t_base + iba.iba_memt->t_size);
154	config_found(self, &iba, vrisabprint);
155#endif
156}
157
158int
159vrisabprint(aux, pnp)
160	void *aux;
161	const char *pnp;
162{
163	if (pnp)
164		return (QUIET);
165	return (UNCONF);
166}
167
168void
169isa_attach_hook(parent, self, iba)
170	struct device *parent, *self;
171	struct isabus_attach_args *iba;
172{
173}
174
175const struct evcnt *
176isa_intr_evcnt(isa_chipset_tag_t ic, int irq)
177{
178
179	/* XXX for now, no evcnt parent reported */
180	return NULL;
181}
182
183void *
184isa_intr_establish(ic, intr, type, level, ih_fun, ih_arg)
185	isa_chipset_tag_t ic;
186	int intr;
187	int type;  /* XXX not yet */
188	int level;  /* XXX not yet */
189	int (*ih_fun) __P((void*));
190	void *ih_arg;
191{
192	struct vrisab_softc *sc = ic->ic_sc;
193	int port, irq, mode;
194
195	/*
196	 * 'intr' encoding:
197	 *
198	 * 0x0000000f ISA IRQ#
199	 * 0x00ff0000 GPIO port#
200	 * 0x01000000 interrupt signal hold/through	(1:hold/0:though)
201	 * 0x02000000 interrupt detection level		(1:low /0:high	)
202	 * 0x04000000 interrupt detection trigger	(1:edge/0:level	)
203	 */
204#define INTR_IRQ(i)	(((i)>> 0) & 0x0f)
205#define INTR_PORT(i)	(((i)>>16) & 0xff)
206#define INTR_MODE(i)	(((i)>>24) & 0x07)
207	static int intr_modes[8] = {
208		VRGIU_INTR_LEVEL_HIGH_THROUGH,
209		VRGIU_INTR_LEVEL_HIGH_HOLD,
210		VRGIU_INTR_LEVEL_LOW_THROUGH,
211		VRGIU_INTR_LEVEL_LOW_HOLD,
212		VRGIU_INTR_EDGE_THROUGH,
213		VRGIU_INTR_EDGE_HOLD,
214		VRGIU_INTR_EDGE_THROUGH,
215		VRGIU_INTR_EDGE_HOLD,
216	};
217#ifdef VRISADEBUG
218	static char* intr_mode_names[8] = {
219		"level high through",
220		"level high hold",
221		"level low through",
222		"level low hold",
223		"edge through",
224		"edge hold",
225		"edge through",
226		"edge hold",
227	};
228#endif /* VRISADEBUG */
229	/*
230	 * ISA IRQ <-> GPIO port mapping
231	 */
232	irq = INTR_IRQ(intr);
233	if (sc->sc_intr_map[irq] != -1) {
234		/* already mapped */
235		intr = sc->sc_intr_map[irq];
236	} else {
237		/* not mapped yet */
238		sc->sc_intr_map[irq] = intr; /* Register it */
239	}
240	mode = INTR_MODE(intr);
241	port = INTR_PORT(intr);
242
243	VPRINTF(("ISA IRQ %d -> GPIO port %d, %s\n",
244	       irq, port, intr_mode_names[mode]));
245
246	/* Call Vr routine */
247	return sc->sc_gf->gf_intr_establish(sc->sc_gc, port,
248					    intr_modes[mode],
249					    level, ih_fun, ih_arg);
250}
251
252void
253isa_intr_disestablish(ic, arg)
254	isa_chipset_tag_t ic;
255	void *arg;
256{
257	struct vrisab_softc *sc = ic->ic_sc;
258	/* Call Vr routine */
259	sc->sc_gf->gf_intr_disestablish(sc->sc_gc, arg);
260}
261
262int
263isa_intr_alloc(ic, mask, type, irq)
264	isa_chipset_tag_t ic;
265	int mask;
266	int type;
267	int *irq;
268{
269	/* XXX not coded yet. this is temporary XXX */
270	DPRINTF(("isa_intr_alloc:"));
271	DBITDISP32(mask);
272	*irq = (ffs(mask) -1); /* XXX */
273	return 0;
274}
275
276#ifdef DEBUG_FIND_PCIC
277#warning DEBUG_FIND_PCIC
278static void
279__find_pcic(void)
280{
281	int i, j, step, found;
282	u_int32_t addr;
283	u_int8_t reg;
284	int __read_revid (u_int32_t port)
285		{
286			addr = MIPS_PHYS_TO_KSEG1(i + port);
287			printf("%#x\r", i);
288			for (found = 0, j = 0; j < 0x100; j += 0x40) {
289				*((volatile u_int8_t*)addr) = j;
290				reg = *((volatile u_int8_t*)(addr + 1));
291#ifdef DEBUG_FIND_PCIC_I82365SL_ONLY
292				if (reg == 0x82 || reg == 0x83) {
293#else
294				if ((reg & 0xc0) == 0x80) {
295#endif
296					found++;
297				}
298			}
299			if (found)
300				printf("\nfound %d socket at %#x (base from %#x)\n", found, addr,
301				       i + port - VR_ISA_PORT_BASE);
302		};
303	step = 0x1000000;
304	printf("\nFinding PCIC. Trying ISA port %#x-%#x step %#x\n",
305	       VR_ISA_PORT_BASE, VR_ISA_PORT_BASE + VR_ISA_PORT_SIZE, step);
306	for (i = VR_ISA_PORT_BASE; i < VR_ISA_PORT_BASE+VR_ISA_PORT_SIZE; i+= step) {
307		__read_revid (0x3e0);
308		__read_revid (0x3e2);
309	}
310}
311#endif
312