com.c revision 1.3.76.1 1 1.3.76.1 yamt /* $NetBSD: com.c,v 1.3.76.1 2008/05/18 12:32:04 yamt Exp $ */
2 1.1 igy
3 1.1 igy /*-
4 1.1 igy * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 1.1 igy * All rights reserved.
6 1.1 igy *
7 1.1 igy * This code is derived from software contributed to The NetBSD Foundation
8 1.1 igy * by Charles M. Hannum.
9 1.1 igy *
10 1.1 igy * Redistribution and use in source and binary forms, with or without
11 1.1 igy * modification, are permitted provided that the following conditions
12 1.1 igy * are met:
13 1.1 igy * 1. Redistributions of source code must retain the above copyright
14 1.1 igy * notice, this list of conditions and the following disclaimer.
15 1.1 igy * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 igy * notice, this list of conditions and the following disclaimer in the
17 1.1 igy * documentation and/or other materials provided with the distribution.
18 1.1 igy *
19 1.1 igy * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 igy * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 igy * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 igy * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 igy * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 igy * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 igy * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 igy * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 igy * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 igy * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 igy * POSSIBILITY OF SUCH DAMAGE.
30 1.1 igy */
31 1.1 igy
32 1.1 igy /*
33 1.1 igy * Copyright (c) 1991 The Regents of the University of California.
34 1.1 igy * All rights reserved.
35 1.1 igy *
36 1.1 igy * Redistribution and use in source and binary forms, with or without
37 1.1 igy * modification, are permitted provided that the following conditions
38 1.1 igy * are met:
39 1.1 igy * 1. Redistributions of source code must retain the above copyright
40 1.1 igy * notice, this list of conditions and the following disclaimer.
41 1.1 igy * 2. Redistributions in binary form must reproduce the above copyright
42 1.1 igy * notice, this list of conditions and the following disclaimer in the
43 1.1 igy * documentation and/or other materials provided with the distribution.
44 1.2 agc * 3. Neither the name of the University nor the names of its contributors
45 1.1 igy * may be used to endorse or promote products derived from this software
46 1.1 igy * without specific prior written permission.
47 1.1 igy *
48 1.1 igy * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
49 1.1 igy * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 1.1 igy * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 1.1 igy * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
52 1.1 igy * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 1.1 igy * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 1.1 igy * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 1.1 igy * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 1.1 igy * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 1.1 igy * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 1.1 igy * SUCH DAMAGE.
59 1.1 igy *
60 1.1 igy * @(#)com.c 7.5 (Berkeley) 5/16/91
61 1.1 igy */
62 1.1 igy
63 1.1 igy #include <sys/param.h>
64 1.1 igy
65 1.1 igy #include <lib/libsa/stand.h>
66 1.1 igy
67 1.1 igy #include <hpcmips/vr/vripreg.h>
68 1.1 igy #include <hpcmips/vr/cmureg.h>
69 1.1 igy
70 1.1 igy #include <dev/ic/comreg.h>
71 1.1 igy #include <dev/ic/ns16550reg.h>
72 1.1 igy #include <dev/ic/st16650reg.h>
73 1.1 igy #define com_lcr com_cfcr
74 1.1 igy
75 1.1 igy #include "extern.h"
76 1.1 igy
77 1.1 igy #if 0
78 1.1 igy #define VRCOM_FREQ 18432000 /* 18.432kHz */
79 1.1 igy #endif
80 1.1 igy
81 1.1 igy int
82 1.1 igy iskey(void)
83 1.1 igy {
84 1.1 igy return ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_RXRDY);
85 1.1 igy }
86 1.1 igy
87 1.1 igy int
88 1.1 igy getchar(void)
89 1.1 igy {
90 1.1 igy u_int8_t stat;
91 1.1 igy u_int8_t c;
92 1.1 igy
93 1.1 igy /* block until a character becomes available */
94 1.1 igy while (!ISKEY)
95 1.1 igy ;
96 1.1 igy
97 1.1 igy c = REGREAD_1(VR4181_SIU_ADDR, com_data);
98 1.1 igy stat = REGREAD_1(VR4181_SIU_ADDR, com_iir);
99 1.1 igy
100 1.1 igy return c;
101 1.1 igy }
102 1.1 igy
103 1.1 igy static void
104 1.1 igy comcnputc(int c)
105 1.1 igy {
106 1.1 igy int timo;
107 1.1 igy
108 1.1 igy /* wait for any pending transmission to finish */
109 1.1 igy timo = 150000;
110 1.1 igy while (!ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_TXRDY)
111 1.1 igy && --timo)
112 1.1 igy continue;
113 1.1 igy
114 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_data, c);
115 1.1 igy
116 1.1 igy /* wait for this transmission to complete */
117 1.1 igy timo = 1500000;
118 1.1 igy while (!ISSET(REGREAD_1(VR4181_SIU_ADDR, com_lsr), LSR_TXRDY)
119 1.1 igy && --timo)
120 1.1 igy continue;
121 1.1 igy }
122 1.1 igy
123 1.1 igy void
124 1.1 igy putchar(int c)
125 1.1 igy {
126 1.1 igy if (c == '\n')
127 1.1 igy comcnputc('\r');
128 1.1 igy comcnputc(c);
129 1.1 igy }
130 1.1 igy
131 1.1 igy /*
132 1.1 igy * Initialize UART for use as console or KGDB line.
133 1.1 igy */
134 1.1 igy void
135 1.1 igy comcninit(void)
136 1.1 igy {
137 1.1 igy int rate;
138 1.1 igy
139 1.1 igy /* enable divisor latch access and set bit rate */
140 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_DLAB);
141 1.1 igy rate = 10; /* 115200bps with VRCOM_FREQ */
142 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_dlbl, rate);
143 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_dlbh, rate >> 8);
144 1.1 igy
145 1.1 igy /*
146 1.1 igy * disable divisor latch access and,
147 1.1 igy * set "8bit non-parity 1 stop bit"
148 1.1 igy */
149 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_8BITS);
150 1.1 igy
151 1.1 igy /* disable all interrupt */
152 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_ier, 0);
153 1.1 igy
154 1.1 igy /* enable FIFO */
155 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_fifo,
156 1.1 igy FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
157 1.1 igy
158 1.1 igy /* set DTR and RTS low */
159 1.1 igy REGWRITE_1(VR4181_SIU_ADDR, com_mcr, MCR_DTR | MCR_RTS);
160 1.1 igy }
161