tx39xx.c revision 1.1 1 1.1 takemura /* $NetBSD: */
2 1.1 takemura
3 1.1 takemura /*-
4 1.1 takemura * Copyright (c) 1999 Shin Takemura, UCHIYAMA Yasushi
5 1.1 takemura * All rights reserved.
6 1.1 takemura *
7 1.1 takemura * This software is part of the PocketBSD.
8 1.1 takemura *
9 1.1 takemura * Redistribution and use in source and binary forms, with or without
10 1.1 takemura * modification, are permitted provided that the following conditions
11 1.1 takemura * are met:
12 1.1 takemura * 1. Redistributions of source code must retain the above copyright
13 1.1 takemura * notice, this list of conditions and the following disclaimer.
14 1.1 takemura * 2. Redistributions in binary form must reproduce the above copyright
15 1.1 takemura * notice, this list of conditions and the following disclaimer in the
16 1.1 takemura * documentation and/or other materials provided with the distribution.
17 1.1 takemura * 3. All advertising materials mentioning features or use of this software
18 1.1 takemura * must display the following acknowledgement:
19 1.1 takemura * This product includes software developed by the PocketBSD project
20 1.1 takemura * and its contributors.
21 1.1 takemura * 4. Neither the name of the project nor the names of its contributors
22 1.1 takemura * may be used to endorse or promote products derived from this software
23 1.1 takemura * without specific prior written permission.
24 1.1 takemura *
25 1.1 takemura * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 1.1 takemura * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 1.1 takemura * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 1.1 takemura * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 1.1 takemura * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 1.1 takemura * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 1.1 takemura * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 1.1 takemura * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 1.1 takemura * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 1.1 takemura * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 1.1 takemura * SUCH DAMAGE.
36 1.1 takemura *
37 1.1 takemura */
38 1.1 takemura
39 1.1 takemura #include <pbsdboot.h>
40 1.1 takemura
41 1.1 takemura extern void tx39xx_asm_code();
42 1.1 takemura extern void tx39xx_asm_code_end();
43 1.1 takemura void tx39xx_asm_code_holder __P((void));
44 1.1 takemura
45 1.1 takemura void
46 1.1 takemura tx39xx_init(SYSTEM_INFO *info)
47 1.1 takemura {
48 1.1 takemura /* 4KByte page */
49 1.1 takemura system_info.si_pagesize = info->dwPageSize;
50 1.1 takemura /* DRAM Bank 0/1 physical addr range */
51 1.1 takemura system_info.si_dramstart = 0x04000000;
52 1.1 takemura system_info.si_drammaxsize = 0x04000000;
53 1.1 takemura /* Pointer for bootstrap code */
54 1.1 takemura system_info.si_asmcode = (unsigned char*)tx39xx_asm_code;
55 1.1 takemura system_info.si_asmcodelen = (unsigned char*)tx39xx_asm_code_end
56 1.1 takemura - system_info.si_asmcode;
57 1.1 takemura system_info.si_boot = mips_boot;
58 1.1 takemura }
59 1.1 takemura
60 1.1 takemura void
61 1.1 takemura tx39xx_asm_code_holder()
62 1.1 takemura {
63 1.1 takemura /*
64 1.1 takemura * void
65 1.1 takemura * startprog(register struct map_s *map)
66 1.1 takemura * {
67 1.1 takemura * register unsigned char *addr;
68 1.1 takemura * register unsigned char *p;
69 1.1 takemura * register int i;
70 1.1 takemura *
71 1.1 takemura * addr = map->base;
72 1.1 takemura * i = 0;
73 1.1 takemura * while (p = map->leaf[i / map->leafsize][i % map->leafsize]) {
74 1.1 takemura * register unsigned char *pe = p + map->pagesize;
75 1.1 takemura * while (p < pe) {
76 1.1 takemura * *addr++ = *p++;
77 1.1 takemura * }
78 1.1 takemura * i++;
79 1.1 takemura * }
80 1.1 takemura * }
81 1.1 takemura *
82 1.1 takemura * register assignment:
83 1.1 takemura * struct map_s *map a0
84 1.1 takemura * unsigned char *addr a1
85 1.1 takemura * unsigned char *p a2
86 1.1 takemura * unsigned char *pe a3
87 1.1 takemura * int i t0
88 1.1 takemura *
89 1.1 takemura * struct map_s {
90 1.1 takemura * caddr_t entry; +0
91 1.1 takemura * caddr_t base; +4
92 1.1 takemura * int pagesize; +8
93 1.1 takemura * int leafsize; +12
94 1.1 takemura * int nleaves; +16
95 1.1 takemura * caddr_t arg0; +20
96 1.1 takemura
97 1.1 takemura * caddr_t arg1; +24
98 1.1 takemura
99 1.1 takemura * caddr_t arg2; +28
100 1.1 takemura
101 1.1 takemura * caddr_t arg3; +32
102 1.1 takemura
103 1.1 takemura * caddr_t *leaf[32]; +36
104 1.1 takemura *
105 1.1 takemura */
106 1.1 takemura __asm(
107 1.1 takemura " .set noreorder; "
108 1.1 takemura " .globl tx39xx_asm_code;"
109 1.1 takemura "tx39xx_asm_code:"
110 1.1 takemura " lui a0, 0x0000; "
111 1.1 takemura " ori a0, 0x0000; "
112 1.1 takemura
113 1.1 takemura /* addr = map->base; */
114 1.1 takemura "lw a1, 4(a0);"
115 1.1 takemura
116 1.1 takemura /* i = 0; */
117 1.1 takemura "ori t0, zero, 0;"
118 1.1 takemura
119 1.1 takemura " loop_start:"
120 1.1 takemura
121 1.1 takemura /* while (p = map->leaf[i / map->leafsize][i % map->leafsize]) { */
122 1.1 takemura /* t1 = map->leafsize */
123 1.1 takemura "lw t1, 12(a0);"
124 1.1 takemura
125 1.1 takemura /* lo = i / map->leafsize, hi = i % map->leafsize */
126 1.1 takemura "addu t3, zero, t0;"
127 1.1 takemura "div t3, t1;"
128 1.1 takemura /* t2 = map->leaf */
129 1.1 takemura "addiu t2, a0, 36;"
130 1.1 takemura /* t3 = i / map->leafsize */
131 1.1 takemura "nop;"
132 1.1 takemura "mflo t3;"
133 1.1 takemura /* t2 = map->leaf[i / map->leafsize] */
134 1.1 takemura "sll t3, t3, 2;"
135 1.1 takemura "addu t2, t2, t3;"
136 1.1 takemura "lw t2, 0(t2);"
137 1.1 takemura /* t3 = i % map->leafsize */
138 1.1 takemura "mfhi t3;"
139 1.1 takemura
140 1.1 takemura /* p = map->leaf[i / map->leafsize][i % map->leafsize] */
141 1.1 takemura "sll t3, t3, 2;"
142 1.1 takemura "addu t2, t2, t3;"
143 1.1 takemura "lw a2, 0(t2);"
144 1.1 takemura
145 1.1 takemura /* if (p == NULL) { */
146 1.1 takemura /* break; */
147 1.1 takemura /* } */
148 1.1 takemura "beq a2, zero, loop_end;"
149 1.1 takemura "nop;"
150 1.1 takemura
151 1.1 takemura /* register unsigned char *pe = p + map->pagesize; */
152 1.1 takemura "lw t1, 8(a0);"
153 1.1 takemura "add a3, a2, t1;"
154 1.1 takemura
155 1.1 takemura /* while (p < pe) { */
156 1.1 takemura "loop_start2:"
157 1.1 takemura "sltu t1, a2, a3;"
158 1.1 takemura "beq zero,t1,loop_end2;"
159 1.1 takemura "nop;"
160 1.1 takemura
161 1.1 takemura /* *addr++ = *p++; */
162 1.1 takemura "lw t1, 0(a2);"
163 1.1 takemura "sw t1, 0(a1);"
164 1.1 takemura "addi a2, a2, 4;"
165 1.1 takemura "addi a1, a1, 4;"
166 1.1 takemura
167 1.1 takemura /* } */
168 1.1 takemura "beq zero, zero, loop_start2;"
169 1.1 takemura "nop;"
170 1.1 takemura
171 1.1 takemura /* i++; */
172 1.1 takemura "loop_end2:"
173 1.1 takemura "addi t0, t0, 1;"
174 1.1 takemura "beq zero, zero, loop_start;"
175 1.1 takemura "nop;"
176 1.1 takemura
177 1.1 takemura " loop_end:"
178 1.1 takemura
179 1.1 takemura /*
180 1.1 takemura * Flush D-cache. TX3912 is write-through cache. no need to flush.
181 1.1 takemura */
182 1.1 takemura #if notyet
183 1.1 takemura /* Flush I-cache */
184 1.1 takemura ".space 32768;"
185 1.1 takemura #endif
186 1.1 takemura /* Jump to kernel entry */
187 1.1 takemura "lw t0, 0(a0);" /* entry addr */
188 1.1 takemura "lw a1, 24(a0);" /* arg1 */
189 1.1 takemura "lw a2, 28(a0);" /* arg2 */
190 1.1 takemura "lw a3, 32(a0);" /* arg3 */
191 1.1 takemura "lw a0, 20(a0);" /* arg0 */
192 1.1 takemura "jr t0;"
193 1.1 takemura "nop;"
194 1.1 takemura
195 1.1 takemura ".globl tx39xx_asm_code_end;"
196 1.1 takemura "tx39xx_asm_code_end: nop;"
197 1.1 takemura ".set reorder; "
198 1.1 takemura );
199 1.1 takemura }
200