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tx39.c revision 1.23.4.1
      1  1.23.4.1      fvdl /*	$NetBSD: tx39.c,v 1.23.4.1 2001/10/01 12:39:15 fvdl Exp $ */
      2       1.1       uch 
      3      1.17       uch /*-
      4      1.20       uch  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
      5      1.20       uch  * All rights reserved.
      6      1.20       uch  *
      7      1.20       uch  * This code is derived from software contributed to The NetBSD Foundation
      8      1.20       uch  * by UCHIYAMA Yasushi.
      9       1.1       uch  *
     10       1.1       uch  * Redistribution and use in source and binary forms, with or without
     11       1.1       uch  * modification, are permitted provided that the following conditions
     12       1.1       uch  * are met:
     13       1.1       uch  * 1. Redistributions of source code must retain the above copyright
     14       1.1       uch  *    notice, this list of conditions and the following disclaimer.
     15      1.16       uch  * 2. Redistributions in binary form must reproduce the above copyright
     16      1.16       uch  *    notice, this list of conditions and the following disclaimer in the
     17      1.16       uch  *    documentation and/or other materials provided with the distribution.
     18      1.20       uch  * 3. All advertising materials mentioning features or use of this software
     19      1.20       uch  *    must display the following acknowledgement:
     20      1.20       uch  *        This product includes software developed by the NetBSD
     21      1.20       uch  *        Foundation, Inc. and its contributors.
     22      1.20       uch  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23      1.20       uch  *    contributors may be used to endorse or promote products derived
     24      1.20       uch  *    from this software without specific prior written permission.
     25       1.1       uch  *
     26      1.20       uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27      1.20       uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28      1.20       uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29      1.20       uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30      1.20       uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31      1.20       uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32      1.20       uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33      1.20       uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34      1.20       uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35      1.20       uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36      1.20       uch  * POSSIBILITY OF SUCH DAMAGE.
     37       1.1       uch  */
     38       1.1       uch 
     39  1.23.4.1      fvdl #include "opt_vr41xx.h"
     40  1.23.4.1      fvdl #include "opt_tx39xx.h"
     41       1.1       uch #include "opt_tx39_debug.h"
     42       1.5       uch #include "m38813c.h"
     43       1.6       uch #include "tc5165buf.h"
     44       1.1       uch 
     45       1.1       uch #include <sys/param.h>
     46       1.1       uch #include <sys/systm.h>
     47       1.1       uch 
     48       1.1       uch #include <machine/locore.h>   /* cpu_id */
     49       1.1       uch #include <machine/bootinfo.h> /* bootinfo */
     50       1.1       uch #include <machine/sysconf.h>  /* platform */
     51       1.1       uch 
     52       1.6       uch #include <machine/platid.h>
     53       1.6       uch #include <machine/platid_mask.h>
     54       1.6       uch 
     55       1.1       uch #include <machine/bus.h>
     56       1.1       uch 
     57  1.23.4.1      fvdl #include <hpcmips/hpcmips/machdep.h> /* cpu_name, mem_cluster */
     58       1.1       uch 
     59       1.1       uch #include <hpcmips/tx/tx39biureg.h>
     60       1.1       uch #include <hpcmips/tx/tx39reg.h>
     61       1.1       uch #include <hpcmips/tx/tx39var.h>
     62       1.1       uch #ifdef TX391X
     63       1.1       uch #include <hpcmips/tx/tx3912videovar.h>
     64       1.1       uch #endif
     65       1.1       uch 
     66       1.1       uch #include <sys/termios.h>
     67       1.1       uch #include <sys/ttydefaults.h>
     68       1.1       uch #include <hpcmips/tx/tx39uartvar.h>
     69       1.1       uch #ifndef CONSPEED
     70       1.1       uch #define CONSPEED TTYDEF_SPEED
     71       1.1       uch #endif
     72       1.1       uch 
     73       1.5       uch /* console keyboard */
     74       1.5       uch #if NM38813C > 0
     75       1.5       uch #include <hpcmips/dev/m38813cvar.h>
     76       1.1       uch #endif
     77       1.6       uch #if NTC5165BUF > 0
     78       1.6       uch #include <hpcmips/dev/tc5165bufvar.h>
     79       1.6       uch #endif
     80       1.1       uch 
     81       1.1       uch struct tx_chipset_tag tx_chipset;
     82       1.1       uch 
     83       1.1       uch #ifdef TX39_DEBUG
     84       1.1       uch u_int32_t tx39debugflag;
     85       1.1       uch #endif
     86       1.1       uch 
     87      1.20       uch void	tx_init(void);
     88  1.23.4.1      fvdl #if defined(VR41XX) && defined(TX39XX)
     89  1.23.4.1      fvdl #define	TX_INTR	tx_intr
     90  1.23.4.1      fvdl #else
     91  1.23.4.1      fvdl #define	TX_INTR	cpu_intr	/* locore_mips3 directly call this */
     92  1.23.4.1      fvdl #endif
     93  1.23.4.1      fvdl 
     94  1.23.4.1      fvdl extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
     95  1.23.4.1      fvdl 
     96  1.23.4.1      fvdl void	tx39clock_cpuspeed(int *, int *);
     97       1.1       uch 
     98       1.1       uch /* TX39-specific initialization vector */
     99      1.20       uch void	tx_cons_init(void);
    100  1.23.4.1      fvdl void    tx_fb_init(caddr_t *);
    101      1.20       uch void    tx_mem_init(paddr_t);
    102      1.20       uch void	tx_find_dram(paddr_t, paddr_t);
    103      1.20       uch void	tx_reboot(int, char *);
    104      1.14      shin 
    105       1.1       uch void
    106       1.1       uch tx_init()
    107       1.1       uch {
    108       1.1       uch 	tx_chipset_tag_t tc;
    109       1.1       uch 	int model, rev;
    110       1.8       uch 	int cpuclock;
    111       1.1       uch 
    112       1.1       uch 	tc = tx_conf_get_tag();
    113       1.1       uch 	/*
    114       1.1       uch 	 * Platform Specific Function Hooks
    115       1.1       uch 	 */
    116  1.23.4.1      fvdl 	platform.cpu_intr	= TX_INTR;
    117  1.23.4.1      fvdl 	platform.cpu_idle	= NULL; /* not implemented yet */
    118  1.23.4.1      fvdl 	platform.cons_init	= tx_cons_init;
    119  1.23.4.1      fvdl 	platform.fb_init	= tx_fb_init;
    120  1.23.4.1      fvdl 	platform.mem_init	= tx_mem_init;
    121  1.23.4.1      fvdl 	platform.reboot		= tx_reboot;
    122  1.23.4.1      fvdl 
    123       1.1       uch 
    124      1.19       cgd 	model = MIPS_PRID_REV(cpu_id);
    125       1.1       uch 
    126       1.1       uch 	switch (model) {
    127       1.1       uch 	default:
    128      1.23       uch 		/* Unknown TOSHIBA TX39-series */
    129      1.19       cgd 		sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model);
    130       1.1       uch 		break;
    131       1.1       uch 	case TMPR3912:
    132       1.8       uch 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    133       1.8       uch 
    134      1.13      sato 		sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
    135      1.23       uch 		    cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    136      1.20       uch 		tc->tc_chipset = __TX391X;
    137       1.1       uch 		break;
    138       1.1       uch 	case TMPR3922:
    139       1.8       uch 		tx39clock_cpuspeed(&cpuclock, &cpuspeed);
    140       1.1       uch 		rev = tx_conf_read(tc, TX3922_REVISION_REG);
    141       1.8       uch 
    142      1.13      sato 		sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
    143      1.23       uch 		    "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
    144      1.23       uch 		    cpuclock / 1000000, (cpuclock % 1000000) / 10000);
    145      1.20       uch 		tc->tc_chipset = __TX392X;
    146       1.1       uch 		break;
    147       1.1       uch 	}
    148       1.1       uch }
    149       1.1       uch 
    150       1.1       uch void
    151  1.23.4.1      fvdl tx_fb_init(caddr_t *kernend)
    152       1.1       uch {
    153       1.1       uch #ifdef TX391X
    154      1.16       uch 	paddr_t fb_end;
    155       1.1       uch 
    156      1.16       uch 	fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start +
    157      1.23       uch 	    mem_clusters[0].size - 1);
    158      1.16       uch 	tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end);
    159      1.16       uch 
    160       1.1       uch 	/* Skip V-RAM area */
    161      1.16       uch 	*kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end);
    162       1.1       uch #endif /* TX391X */
    163       1.1       uch #ifdef TX392X
    164       1.1       uch 	/*
    165       1.1       uch 	 *  Plum V-RAM isn't accessible until pmap_bootstrap,
    166       1.7       uch 	 * at this time, frame buffer device is disabled.
    167       1.1       uch 	 */
    168       1.1       uch 	bootinfo->fb_addr = 0;
    169       1.1       uch #endif /* TX392X */
    170       1.1       uch }
    171       1.1       uch 
    172      1.14      shin void
    173  1.23.4.1      fvdl tx_mem_init(paddr_t kernend)
    174       1.1       uch {
    175  1.23.4.1      fvdl 
    176      1.14      shin 	mem_clusters[0].start = 0;
    177      1.14      shin 	mem_clusters[0].size = kernend;
    178      1.14      shin 	mem_cluster_cnt = 1;
    179      1.14      shin 	/* search DRAM bank 0 */
    180      1.14      shin 	tx_find_dram(kernend, 0x02000000);
    181       1.1       uch 
    182      1.14      shin 	/* search DRAM bank 1 */
    183      1.14      shin 	tx_find_dram(0x02000000, 0x04000000);
    184       1.5       uch 	/*
    185       1.5       uch 	 *  Clear currently unused D-RAM area
    186       1.5       uch 	 *  (For reboot Windows CE clearly)
    187       1.5       uch 	 */
    188      1.14      shin 	memset((void *)(KERNBASE + 0x400), 0, KERNTEXTOFF -
    189      1.23       uch 	    (KERNBASE + 0x800));
    190       1.2  takemura }
    191       1.2  takemura 
    192       1.2  takemura void
    193  1.23.4.1      fvdl tx_find_dram(paddr_t start, paddr_t end)
    194       1.2  takemura {
    195      1.14      shin 	caddr_t page, startaddr, endaddr;
    196      1.14      shin 
    197      1.14      shin 	startaddr = (void*)MIPS_PHYS_TO_KSEG1(start);
    198      1.14      shin 	endaddr = (void*)MIPS_PHYS_TO_KSEG1(end);
    199       1.1       uch 
    200       1.1       uch #define DRAM_MAGIC0 0xac1dcafe
    201       1.1       uch #define DRAM_MAGIC1 0x19700220
    202       1.1       uch 
    203       1.1       uch 	page = startaddr;
    204      1.14      shin 	if (badaddr(page, 4))
    205      1.14      shin 		return;
    206      1.14      shin 
    207      1.17       uch 	*(volatile int *)(page + 0) = DRAM_MAGIC0;
    208      1.17       uch 	*(volatile int *)(page + 4) = DRAM_MAGIC1;
    209      1.14      shin 	wbflush();
    210      1.14      shin 
    211      1.17       uch 	if (*(volatile int *)(page + 0) != DRAM_MAGIC0 ||
    212      1.17       uch 	    *(volatile int *)(page + 4) != DRAM_MAGIC1)
    213      1.14      shin 		return;
    214      1.14      shin 
    215      1.14      shin 	for (page += NBPG; page < endaddr; page += NBPG) {
    216      1.14      shin 		if (badaddr(page, 4))
    217      1.14      shin 			return;
    218      1.14      shin 
    219      1.17       uch 		if (*(volatile int *)(page + 0) == DRAM_MAGIC0 &&
    220      1.17       uch 		    *(volatile int *)(page + 4) == DRAM_MAGIC1) {
    221      1.17       uch 			goto memend_found;
    222       1.1       uch 		}
    223       1.1       uch 	}
    224      1.14      shin 
    225      1.17       uch 	/* check for 32MByte memory */
    226      1.17       uch 	page -= NBPG;
    227      1.17       uch 	*(volatile int *)(page + 0) = DRAM_MAGIC0;
    228      1.17       uch 	*(volatile int *)(page + 4) = DRAM_MAGIC1;
    229      1.17       uch 	wbflush();
    230      1.17       uch 
    231      1.17       uch 	if (*(volatile int *)(page + 0) != DRAM_MAGIC0 ||
    232      1.17       uch 	    *(volatile int *)(page + 4) != DRAM_MAGIC1)
    233      1.17       uch 		return; /* no memory in this bank */
    234      1.17       uch 
    235      1.17       uch  memend_found:
    236      1.17       uch 	mem_clusters[mem_cluster_cnt].start = start;
    237      1.17       uch 	mem_clusters[mem_cluster_cnt].size = page - startaddr;
    238      1.17       uch 
    239      1.17       uch 	/* skip kernel area */
    240      1.17       uch 	if (mem_cluster_cnt == 1)
    241      1.17       uch 		mem_clusters[mem_cluster_cnt].size -= start;
    242      1.17       uch 
    243      1.17       uch 	mem_cluster_cnt++;
    244      1.14      shin }
    245      1.14      shin 
    246      1.14      shin void
    247  1.23.4.1      fvdl tx_reboot(int howto, char *bootstr)
    248      1.14      shin {
    249       1.1       uch 
    250  1.23.4.1      fvdl 	goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
    251       1.1       uch }
    252       1.1       uch 
    253       1.1       uch void
    254       1.1       uch tx_cons_init()
    255       1.1       uch {
    256       1.1       uch 	int slot;
    257      1.20       uch #define CONSPLATIDMATCH(p)						\
    258       1.6       uch 	platid_match(&platid, &platid_mask_MACH_##p)
    259       1.1       uch 
    260       1.1       uch #ifdef SERIALCONSSLOT
    261       1.1       uch 	slot = SERIALCONSSLOT;
    262       1.1       uch #else
    263       1.1       uch 	slot = TX39_UARTA;
    264       1.1       uch #endif
    265       1.1       uch 	if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
    266      1.23       uch 		if(txcom_cnattach(slot, CONSPEED,
    267      1.23       uch 		    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
    268       1.1       uch 			panic("tx_cons_init: can't attach serial console.");
    269       1.1       uch 		}
    270       1.5       uch 	} else {
    271       1.6       uch #if NM38813C > 0
    272       1.6       uch 		if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
    273      1.23       uch 		    m38813c_cnattach(TX39_SYSADDR_CARD1)) {
    274      1.10       uch 			goto panic;
    275       1.6       uch 		}
    276       1.6       uch #endif
    277       1.6       uch #if NTC5165BUF > 0
    278      1.10       uch 		if(CONSPLATIDMATCH(COMPAQ_C) &&
    279      1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
    280      1.10       uch 			goto panic;
    281      1.10       uch 		}
    282      1.10       uch 
    283       1.6       uch 		if(CONSPLATIDMATCH(SHARP_TELIOS) &&
    284      1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
    285      1.10       uch 			goto panic;
    286      1.10       uch 		}
    287      1.10       uch 
    288      1.10       uch 		if(CONSPLATIDMATCH(SHARP_MOBILON) &&
    289      1.23       uch 		    tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
    290      1.10       uch 			goto panic;
    291       1.5       uch 		}
    292       1.5       uch #endif
    293       1.1       uch 	}
    294      1.10       uch 
    295      1.10       uch 	return;
    296      1.10       uch  panic:
    297      1.10       uch 	panic("tx_cons_init: can't init console");
    298      1.10       uch 	/* NOTREACHED */
    299       1.1       uch }
    300       1.1       uch 
    301       1.1       uch void
    302  1.23.4.1      fvdl tx_conf_register_intr(tx_chipset_tag_t t, void *intrt)
    303       1.1       uch {
    304       1.1       uch 
    305      1.20       uch 	KASSERT(t == &tx_chipset);
    306       1.1       uch 	tx_chipset.tc_intrt = intrt;
    307       1.1       uch }
    308       1.1       uch 
    309       1.9       uch void
    310  1.23.4.1      fvdl tx_conf_register_power(tx_chipset_tag_t t, void *powert)
    311       1.9       uch {
    312       1.9       uch 
    313  1.23.4.1      fvdl 	KASSERT(t == &tx_chipset);
    314       1.9       uch 	tx_chipset.tc_powert = powert;
    315       1.9       uch }
    316       1.9       uch 
    317       1.9       uch void
    318  1.23.4.1      fvdl tx_conf_register_clock(tx_chipset_tag_t t, void *clockt)
    319       1.9       uch {
    320       1.9       uch 
    321  1.23.4.1      fvdl 	KASSERT(t == &tx_chipset);
    322       1.9       uch 	tx_chipset.tc_clockt = clockt;
    323      1.11       uch }
    324      1.11       uch 
    325      1.11       uch void
    326  1.23.4.1      fvdl tx_conf_register_sound(tx_chipset_tag_t t, void *soundt)
    327      1.11       uch {
    328      1.11       uch 
    329  1.23.4.1      fvdl 	KASSERT(t == &tx_chipset);
    330      1.11       uch 	tx_chipset.tc_soundt = soundt;
    331      1.18       uch }
    332      1.18       uch 
    333      1.18       uch void
    334  1.23.4.1      fvdl tx_conf_register_video(tx_chipset_tag_t t, void *videot)
    335      1.18       uch {
    336      1.18       uch 
    337  1.23.4.1      fvdl 	KASSERT(t == &tx_chipset);
    338      1.18       uch 	tx_chipset.tc_videot = videot;
    339       1.9       uch }
    340       1.1       uch 
    341       1.1       uch int
    342  1.23.4.1      fvdl __is_set_print(u_int32_t reg, int mask, char *name)
    343       1.1       uch {
    344       1.9       uch 	const char onoff[2] = "_x";
    345       1.9       uch 	int ret = reg & mask ? 1 : 0;
    346       1.9       uch 
    347       1.9       uch 	printf("%s[%c] ", name, onoff[ret]);
    348       1.9       uch 
    349      1.23       uch 	return (ret);
    350       1.1       uch }
    351