tx39.c revision 1.27.4.2 1 1.27.4.2 nathanw /* $NetBSD: tx39.c,v 1.27.4.2 2002/01/11 23:38:25 nathanw Exp $ */
2 1.27.4.2 nathanw
3 1.27.4.2 nathanw /*-
4 1.27.4.2 nathanw * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 1.27.4.2 nathanw * All rights reserved.
6 1.27.4.2 nathanw *
7 1.27.4.2 nathanw * This code is derived from software contributed to The NetBSD Foundation
8 1.27.4.2 nathanw * by UCHIYAMA Yasushi.
9 1.27.4.2 nathanw *
10 1.27.4.2 nathanw * Redistribution and use in source and binary forms, with or without
11 1.27.4.2 nathanw * modification, are permitted provided that the following conditions
12 1.27.4.2 nathanw * are met:
13 1.27.4.2 nathanw * 1. Redistributions of source code must retain the above copyright
14 1.27.4.2 nathanw * notice, this list of conditions and the following disclaimer.
15 1.27.4.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright
16 1.27.4.2 nathanw * notice, this list of conditions and the following disclaimer in the
17 1.27.4.2 nathanw * documentation and/or other materials provided with the distribution.
18 1.27.4.2 nathanw * 3. All advertising materials mentioning features or use of this software
19 1.27.4.2 nathanw * must display the following acknowledgement:
20 1.27.4.2 nathanw * This product includes software developed by the NetBSD
21 1.27.4.2 nathanw * Foundation, Inc. and its contributors.
22 1.27.4.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.27.4.2 nathanw * contributors may be used to endorse or promote products derived
24 1.27.4.2 nathanw * from this software without specific prior written permission.
25 1.27.4.2 nathanw *
26 1.27.4.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.27.4.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.27.4.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.27.4.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.27.4.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.27.4.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.27.4.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.27.4.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.27.4.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.27.4.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.27.4.2 nathanw * POSSIBILITY OF SUCH DAMAGE.
37 1.27.4.2 nathanw */
38 1.27.4.2 nathanw
39 1.27.4.2 nathanw #include "opt_vr41xx.h"
40 1.27.4.2 nathanw #include "opt_tx39xx.h"
41 1.27.4.2 nathanw #include "opt_tx39_debug.h"
42 1.27.4.2 nathanw #include "m38813c.h"
43 1.27.4.2 nathanw #include "tc5165buf.h"
44 1.27.4.2 nathanw
45 1.27.4.2 nathanw #include <sys/param.h>
46 1.27.4.2 nathanw #include <sys/systm.h>
47 1.27.4.2 nathanw
48 1.27.4.2 nathanw #include <mips/cache.h>
49 1.27.4.2 nathanw
50 1.27.4.2 nathanw #include <machine/locore.h> /* cpu_id */
51 1.27.4.2 nathanw #include <machine/bootinfo.h> /* bootinfo */
52 1.27.4.2 nathanw #include <machine/sysconf.h> /* platform */
53 1.27.4.2 nathanw
54 1.27.4.2 nathanw #include <machine/platid.h>
55 1.27.4.2 nathanw #include <machine/platid_mask.h>
56 1.27.4.2 nathanw
57 1.27.4.2 nathanw #include <machine/bus.h>
58 1.27.4.2 nathanw
59 1.27.4.2 nathanw #include <hpcmips/hpcmips/machdep.h> /* cpu_name, mem_cluster */
60 1.27.4.2 nathanw
61 1.27.4.2 nathanw #include <hpcmips/tx/tx39biureg.h>
62 1.27.4.2 nathanw #include <hpcmips/tx/tx39reg.h>
63 1.27.4.2 nathanw #include <hpcmips/tx/tx39var.h>
64 1.27.4.2 nathanw #ifdef TX391X
65 1.27.4.2 nathanw #include <hpcmips/tx/tx3912videovar.h>
66 1.27.4.2 nathanw #endif
67 1.27.4.2 nathanw
68 1.27.4.2 nathanw #include <sys/termios.h>
69 1.27.4.2 nathanw #include <sys/ttydefaults.h>
70 1.27.4.2 nathanw #include <hpcmips/tx/tx39uartvar.h>
71 1.27.4.2 nathanw #ifndef CONSPEED
72 1.27.4.2 nathanw #define CONSPEED TTYDEF_SPEED
73 1.27.4.2 nathanw #endif
74 1.27.4.2 nathanw
75 1.27.4.2 nathanw /* console keyboard */
76 1.27.4.2 nathanw #if NM38813C > 0
77 1.27.4.2 nathanw #include <hpcmips/dev/m38813cvar.h>
78 1.27.4.2 nathanw #endif
79 1.27.4.2 nathanw #if NTC5165BUF > 0
80 1.27.4.2 nathanw #include <hpcmips/dev/tc5165bufvar.h>
81 1.27.4.2 nathanw #endif
82 1.27.4.2 nathanw
83 1.27.4.2 nathanw struct tx_chipset_tag tx_chipset;
84 1.27.4.2 nathanw
85 1.27.4.2 nathanw #ifdef TX39_DEBUG
86 1.27.4.2 nathanw u_int32_t tx39debugflag;
87 1.27.4.2 nathanw #endif
88 1.27.4.2 nathanw
89 1.27.4.2 nathanw void tx_init(void);
90 1.27.4.2 nathanw #if defined(VR41XX) && defined(TX39XX)
91 1.27.4.2 nathanw #define TX_INTR tx_intr
92 1.27.4.2 nathanw #else
93 1.27.4.2 nathanw #define TX_INTR cpu_intr /* locore_mips3 directly call this */
94 1.27.4.2 nathanw #endif
95 1.27.4.2 nathanw
96 1.27.4.2 nathanw extern void TX_INTR(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
97 1.27.4.2 nathanw
98 1.27.4.2 nathanw void tx39clock_cpuspeed(int *, int *);
99 1.27.4.2 nathanw
100 1.27.4.2 nathanw /* TX39-specific initialization vector */
101 1.27.4.2 nathanw void tx_cons_init(void);
102 1.27.4.2 nathanw void tx_fb_init(caddr_t *);
103 1.27.4.2 nathanw void tx_mem_init(paddr_t);
104 1.27.4.2 nathanw void tx_find_dram(paddr_t, paddr_t);
105 1.27.4.2 nathanw void tx_reboot(int, char *);
106 1.27.4.2 nathanw
107 1.27.4.2 nathanw void
108 1.27.4.2 nathanw tx_init()
109 1.27.4.2 nathanw {
110 1.27.4.2 nathanw tx_chipset_tag_t tc;
111 1.27.4.2 nathanw int model, rev;
112 1.27.4.2 nathanw int cpuclock;
113 1.27.4.2 nathanw
114 1.27.4.2 nathanw tc = tx_conf_get_tag();
115 1.27.4.2 nathanw /*
116 1.27.4.2 nathanw * Platform Specific Function Hooks
117 1.27.4.2 nathanw */
118 1.27.4.2 nathanw platform.cpu_intr = TX_INTR;
119 1.27.4.2 nathanw platform.cpu_idle = NULL; /* not implemented yet */
120 1.27.4.2 nathanw platform.cons_init = tx_cons_init;
121 1.27.4.2 nathanw platform.fb_init = tx_fb_init;
122 1.27.4.2 nathanw platform.mem_init = tx_mem_init;
123 1.27.4.2 nathanw platform.reboot = tx_reboot;
124 1.27.4.2 nathanw
125 1.27.4.2 nathanw
126 1.27.4.2 nathanw model = MIPS_PRID_REV(cpu_id);
127 1.27.4.2 nathanw
128 1.27.4.2 nathanw switch (model) {
129 1.27.4.2 nathanw default:
130 1.27.4.2 nathanw /* Unknown TOSHIBA TX39-series */
131 1.27.4.2 nathanw sprintf(cpu_name, "Unknown TOSHIBA TX39-series %x", model);
132 1.27.4.2 nathanw break;
133 1.27.4.2 nathanw case TMPR3912:
134 1.27.4.2 nathanw tx39clock_cpuspeed(&cpuclock, &cpuspeed);
135 1.27.4.2 nathanw
136 1.27.4.2 nathanw sprintf(cpu_name, "TOSHIBA TMPR3912 %d.%02d MHz",
137 1.27.4.2 nathanw cpuclock / 1000000, (cpuclock % 1000000) / 10000);
138 1.27.4.2 nathanw tc->tc_chipset = __TX391X;
139 1.27.4.2 nathanw break;
140 1.27.4.2 nathanw case TMPR3922:
141 1.27.4.2 nathanw tx39clock_cpuspeed(&cpuclock, &cpuspeed);
142 1.27.4.2 nathanw rev = tx_conf_read(tc, TX3922_REVISION_REG);
143 1.27.4.2 nathanw
144 1.27.4.2 nathanw sprintf(cpu_name, "TOSHIBA TMPR3922 rev. %x.%x "
145 1.27.4.2 nathanw "%d.%02d MHz", (rev >> 4) & 0xf, rev & 0xf,
146 1.27.4.2 nathanw cpuclock / 1000000, (cpuclock % 1000000) / 10000);
147 1.27.4.2 nathanw tc->tc_chipset = __TX392X;
148 1.27.4.2 nathanw break;
149 1.27.4.2 nathanw }
150 1.27.4.2 nathanw }
151 1.27.4.2 nathanw
152 1.27.4.2 nathanw void
153 1.27.4.2 nathanw tx_fb_init(caddr_t *kernend)
154 1.27.4.2 nathanw {
155 1.27.4.2 nathanw #ifdef TX391X
156 1.27.4.2 nathanw paddr_t fb_end;
157 1.27.4.2 nathanw
158 1.27.4.2 nathanw fb_end = MIPS_KSEG0_TO_PHYS(mem_clusters[0].start +
159 1.27.4.2 nathanw mem_clusters[0].size - 1);
160 1.27.4.2 nathanw tx3912video_init(MIPS_KSEG0_TO_PHYS(*kernend), &fb_end);
161 1.27.4.2 nathanw
162 1.27.4.2 nathanw /* Skip V-RAM area */
163 1.27.4.2 nathanw *kernend = (caddr_t)MIPS_PHYS_TO_KSEG0(fb_end);
164 1.27.4.2 nathanw #endif /* TX391X */
165 1.27.4.2 nathanw #ifdef TX392X
166 1.27.4.2 nathanw /*
167 1.27.4.2 nathanw * Plum V-RAM isn't accessible until pmap_bootstrap,
168 1.27.4.2 nathanw * at this time, frame buffer device is disabled.
169 1.27.4.2 nathanw */
170 1.27.4.2 nathanw bootinfo->fb_addr = 0;
171 1.27.4.2 nathanw #endif /* TX392X */
172 1.27.4.2 nathanw }
173 1.27.4.2 nathanw
174 1.27.4.2 nathanw void
175 1.27.4.2 nathanw tx_mem_init(paddr_t kernend)
176 1.27.4.2 nathanw {
177 1.27.4.2 nathanw
178 1.27.4.2 nathanw mem_clusters[0].start = 0;
179 1.27.4.2 nathanw mem_clusters[0].size = kernend;
180 1.27.4.2 nathanw mem_cluster_cnt = 1;
181 1.27.4.2 nathanw /* search DRAM bank 0 */
182 1.27.4.2 nathanw tx_find_dram(kernend, 0x02000000);
183 1.27.4.2 nathanw
184 1.27.4.2 nathanw /* search DRAM bank 1 */
185 1.27.4.2 nathanw tx_find_dram(0x02000000, 0x04000000);
186 1.27.4.2 nathanw }
187 1.27.4.2 nathanw
188 1.27.4.2 nathanw void
189 1.27.4.2 nathanw tx_find_dram(paddr_t start, paddr_t end)
190 1.27.4.2 nathanw {
191 1.27.4.2 nathanw caddr_t page, startaddr, endaddr;
192 1.27.4.2 nathanw u_int32_t magic0, magic1;
193 1.27.4.2 nathanw #define MAGIC0 (*(__volatile u_int32_t *)(page + 0))
194 1.27.4.2 nathanw #define MAGIC1 (*(__volatile u_int32_t *)(page + 4))
195 1.27.4.2 nathanw
196 1.27.4.2 nathanw startaddr = (void *)MIPS_PHYS_TO_KSEG1(start);
197 1.27.4.2 nathanw endaddr = (void *)MIPS_PHYS_TO_KSEG1(end);
198 1.27.4.2 nathanw
199 1.27.4.2 nathanw page = startaddr;
200 1.27.4.2 nathanw if (badaddr(page, 4))
201 1.27.4.2 nathanw return;
202 1.27.4.2 nathanw
203 1.27.4.2 nathanw do {
204 1.27.4.2 nathanw magic0 = random();
205 1.27.4.2 nathanw magic1 = random();
206 1.27.4.2 nathanw } while (MAGIC0 == magic0 || MAGIC0 == magic1);
207 1.27.4.2 nathanw
208 1.27.4.2 nathanw MAGIC0 = magic0;
209 1.27.4.2 nathanw MAGIC1 = magic1;
210 1.27.4.2 nathanw wbflush();
211 1.27.4.2 nathanw
212 1.27.4.2 nathanw if (MAGIC0 != magic0 || MAGIC1 != magic1)
213 1.27.4.2 nathanw return;
214 1.27.4.2 nathanw
215 1.27.4.2 nathanw for (page += NBPG; page < endaddr; page += NBPG) {
216 1.27.4.2 nathanw if (badaddr(page, 4))
217 1.27.4.2 nathanw return;
218 1.27.4.2 nathanw if (MAGIC0 == magic0 &&
219 1.27.4.2 nathanw MAGIC1 == magic1) {
220 1.27.4.2 nathanw goto memend_found;
221 1.27.4.2 nathanw }
222 1.27.4.2 nathanw }
223 1.27.4.2 nathanw
224 1.27.4.2 nathanw /* check for 32MByte memory */
225 1.27.4.2 nathanw page -= NBPG;
226 1.27.4.2 nathanw MAGIC0 = magic0;
227 1.27.4.2 nathanw MAGIC1 = magic1;
228 1.27.4.2 nathanw wbflush();
229 1.27.4.2 nathanw if (MAGIC0 != magic0 || MAGIC1 != magic1)
230 1.27.4.2 nathanw return; /* no memory in this bank */
231 1.27.4.2 nathanw
232 1.27.4.2 nathanw memend_found:
233 1.27.4.2 nathanw mem_clusters[mem_cluster_cnt].start = start;
234 1.27.4.2 nathanw mem_clusters[mem_cluster_cnt].size = page - startaddr;
235 1.27.4.2 nathanw
236 1.27.4.2 nathanw /* skip kernel area */
237 1.27.4.2 nathanw if (mem_cluster_cnt == 1)
238 1.27.4.2 nathanw mem_clusters[mem_cluster_cnt].size -= start;
239 1.27.4.2 nathanw
240 1.27.4.2 nathanw mem_cluster_cnt++;
241 1.27.4.2 nathanw #undef MAGIC0
242 1.27.4.2 nathanw #undef MAGIC1
243 1.27.4.2 nathanw }
244 1.27.4.2 nathanw
245 1.27.4.2 nathanw void
246 1.27.4.2 nathanw tx_reboot(int howto, char *bootstr)
247 1.27.4.2 nathanw {
248 1.27.4.2 nathanw
249 1.27.4.2 nathanw goto *(u_int32_t *)MIPS_RESET_EXC_VEC;
250 1.27.4.2 nathanw }
251 1.27.4.2 nathanw
252 1.27.4.2 nathanw void
253 1.27.4.2 nathanw tx_cons_init()
254 1.27.4.2 nathanw {
255 1.27.4.2 nathanw int slot;
256 1.27.4.2 nathanw #define CONSPLATIDMATCH(p) \
257 1.27.4.2 nathanw platid_match(&platid, &platid_mask_MACH_##p)
258 1.27.4.2 nathanw
259 1.27.4.2 nathanw #ifdef SERIALCONSSLOT
260 1.27.4.2 nathanw slot = SERIALCONSSLOT;
261 1.27.4.2 nathanw #else
262 1.27.4.2 nathanw slot = TX39_UARTA;
263 1.27.4.2 nathanw #endif
264 1.27.4.2 nathanw if (bootinfo->bi_cnuse & BI_CNUSE_SERIAL) {
265 1.27.4.2 nathanw if(txcom_cnattach(slot, CONSPEED,
266 1.27.4.2 nathanw (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8)) {
267 1.27.4.2 nathanw panic("tx_cons_init: can't attach serial console.");
268 1.27.4.2 nathanw }
269 1.27.4.2 nathanw } else {
270 1.27.4.2 nathanw #if NM38813C > 0
271 1.27.4.2 nathanw if(CONSPLATIDMATCH(VICTOR_INTERLINK) &&
272 1.27.4.2 nathanw m38813c_cnattach(TX39_SYSADDR_CARD1)) {
273 1.27.4.2 nathanw goto panic;
274 1.27.4.2 nathanw }
275 1.27.4.2 nathanw #endif
276 1.27.4.2 nathanw #if NTC5165BUF > 0
277 1.27.4.2 nathanw if(CONSPLATIDMATCH(COMPAQ_C) &&
278 1.27.4.2 nathanw tc5165buf_cnattach(TX39_SYSADDR_CS3)) {
279 1.27.4.2 nathanw goto panic;
280 1.27.4.2 nathanw }
281 1.27.4.2 nathanw
282 1.27.4.2 nathanw if(CONSPLATIDMATCH(SHARP_TELIOS) &&
283 1.27.4.2 nathanw tc5165buf_cnattach(TX39_SYSADDR_CS1)) {
284 1.27.4.2 nathanw goto panic;
285 1.27.4.2 nathanw }
286 1.27.4.2 nathanw
287 1.27.4.2 nathanw if(CONSPLATIDMATCH(SHARP_MOBILON) &&
288 1.27.4.2 nathanw tc5165buf_cnattach(TX39_SYSADDR_MCS0)) {
289 1.27.4.2 nathanw goto panic;
290 1.27.4.2 nathanw }
291 1.27.4.2 nathanw #endif
292 1.27.4.2 nathanw }
293 1.27.4.2 nathanw
294 1.27.4.2 nathanw return;
295 1.27.4.2 nathanw panic:
296 1.27.4.2 nathanw panic("tx_cons_init: can't init console");
297 1.27.4.2 nathanw /* NOTREACHED */
298 1.27.4.2 nathanw }
299 1.27.4.2 nathanw
300 1.27.4.2 nathanw void
301 1.27.4.2 nathanw tx_conf_register_intr(tx_chipset_tag_t t, void *intrt)
302 1.27.4.2 nathanw {
303 1.27.4.2 nathanw
304 1.27.4.2 nathanw KASSERT(t == &tx_chipset);
305 1.27.4.2 nathanw tx_chipset.tc_intrt = intrt;
306 1.27.4.2 nathanw }
307 1.27.4.2 nathanw
308 1.27.4.2 nathanw void
309 1.27.4.2 nathanw tx_conf_register_power(tx_chipset_tag_t t, void *powert)
310 1.27.4.2 nathanw {
311 1.27.4.2 nathanw
312 1.27.4.2 nathanw KASSERT(t == &tx_chipset);
313 1.27.4.2 nathanw tx_chipset.tc_powert = powert;
314 1.27.4.2 nathanw }
315 1.27.4.2 nathanw
316 1.27.4.2 nathanw void
317 1.27.4.2 nathanw tx_conf_register_clock(tx_chipset_tag_t t, void *clockt)
318 1.27.4.2 nathanw {
319 1.27.4.2 nathanw
320 1.27.4.2 nathanw KASSERT(t == &tx_chipset);
321 1.27.4.2 nathanw tx_chipset.tc_clockt = clockt;
322 1.27.4.2 nathanw }
323 1.27.4.2 nathanw
324 1.27.4.2 nathanw void
325 1.27.4.2 nathanw tx_conf_register_sound(tx_chipset_tag_t t, void *soundt)
326 1.27.4.2 nathanw {
327 1.27.4.2 nathanw
328 1.27.4.2 nathanw KASSERT(t == &tx_chipset);
329 1.27.4.2 nathanw tx_chipset.tc_soundt = soundt;
330 1.27.4.2 nathanw }
331 1.27.4.2 nathanw
332 1.27.4.2 nathanw void
333 1.27.4.2 nathanw tx_conf_register_video(tx_chipset_tag_t t, void *videot)
334 1.27.4.2 nathanw {
335 1.27.4.2 nathanw
336 1.27.4.2 nathanw KASSERT(t == &tx_chipset);
337 1.27.4.2 nathanw tx_chipset.tc_videot = videot;
338 1.27.4.2 nathanw }
339 1.27.4.2 nathanw
340 1.27.4.2 nathanw int
341 1.27.4.2 nathanw __is_set_print(u_int32_t reg, int mask, char *name)
342 1.27.4.2 nathanw {
343 1.27.4.2 nathanw const char onoff[2] = "_x";
344 1.27.4.2 nathanw int ret = reg & mask ? 1 : 0;
345 1.27.4.2 nathanw
346 1.27.4.2 nathanw printf("%s[%c] ", name, onoff[ret]);
347 1.27.4.2 nathanw
348 1.27.4.2 nathanw return (ret);
349 1.27.4.2 nathanw }
350